Test Benches in Verilog

Test benches in VerilogTest benches in Verilog

Test BenchTest Bench

• As digital systems become more complex itAs digital systems become more complex, itbecomes increasingly important to verify thefunctionality of a design before implementingfunctionality of a design before implementingit in a system

• HDLs have become extremely popular because• HDLs have become extremely popular becausethey can be used for both Designing andTestingTesting

The Device Under TestThe Device Under Test

• The DUT is the behavioral or gate levelThe DUT is the behavioral or gate levelrepresentation of a design

• This is also known as a Register Transfer Level• This is also known as a Register Transfer Levelor RTL description of the design

E h f f h d i h ld b d• Each feature of the design should be tested toensure that unexpected bugs have not beeni d d i h d iintroduced into the design

Role of a Test benchRole of a Test bench

• The Test benchThe Test benchprovides the stimulusto the DUT

Verilog Test bench givesStimulusto the DUT

• A waveform capture isused to monitor/displayused to monitor/displaythe results

RTL Design DUT

WaveformWaveform Capture

Test bench continuedTest bench continued

• Let us write a Test module mux 2to1(Y, A, B, sel);Let us write a Testbench for a 2:1 Mux

• Before going for the

module mux_2to1(Y, A, B, sel);output Y;input A, B;input sel;g g

Test Bench, let usrevisit the RTL of a

input sel;reg Y;

always @(A or B or sel)2:1 Mux if (sel == 1'b0)

Y = A;elseelseY = B;

endmodule

Let us write a Test BenchLet us write a Test Bench

`timescale 1ns / 100ps • Let us start from the top of the test module Test_mux_2to1; wire Y;reg A, B; reg sel;

pbench and try to understand it line by line.

reg sel;

mux_2to1 mydut(.Y(Y),.A( A), .B(B),.sel( sel));

initial begin Sel = 0; A = 0; B = 0;

#10 A 1’b1#10 A = 1’b1;#10 sel = 1’b1;#10 B= 1’b1;

endendendmodule

Understanding Test benchUnderstanding Test bench

`timescale 1ns / 100ps • This line is called the “timescalecompiler directive”module Test_mux_2to1;

wire Y;reg A, B; reg sel;

compiler directive

• This line is important in a Verilogsimulation, because it sets up the timescale and operating precision for areg sel;


scale and operating precision for amodule

• It causes the unit delays to be innanoseconds (ns) and the precision at

initial beginSel = 0; A = 0; B = 0;

#10 A 1’b1

nanoseconds (ns) and the precision atwhich the simulator will round theevents down to at 100 ps.

• This causes a #5 or #1 in a Verilog#10 A = 1’b1;#10 sel = 1’b1;#10 B= 1’b1;

end

• This causes a #5 or #1 in a Verilogassignment to be a 5 ns or 1 ns delayrespectively

• The rounding of the events will be toendendmodule

• The rounding of the events will be to.1ns or 100 pico seconds.


`timescale 1ns / 100ps • This line gives a name to our Test benchmodule Test_mux_2to1; wire Y;reg A, B; reg sel;

• Observe the difference between this lineof a test bench and normal verilog code

reg sel;


• Normal verilog code is like the line givenbelow

module mux_2to1(Y, A, B, sel);initial beginSel = 0; A = 0; B = 0;

#10 A 1’b1

• No need to give Ports in a testbench!!!!

#10 A = 1’b1;#10 sel = 1’b1;#10 B= 1’b1;

endendendmodule


`timescale 1ns / 100ps • There are two signal types in the test b h d t d i d it i l module Test_mux_2to1;


bench used to drive and monitor signals during the simulation

• These two types of signals are reg and wire types

reg sel;


• The reg data type holds a value until a new value is driven onto it

• The wire type is a passive data type that gives a value driven on it by a port


#10 A 1’b1

gives a value driven on it by a port• Since our aim is to simulate, inputs are

to be given by the user. So, the inputs in the RTL code become reg type in test bench in order to hold the value given #10 A = 1’b1;

#10 sel = 1’b1;#10 B= 1’b1;

end

bench in order to hold the value given by the user

• The outputs in the RTL become wire type in testbench so that the user can

it /di l th lendendmodule

monitor/display the value


`timescale 1ns / 100ps • The test bench applies stimulus to theDUTmodule Test_mux_2to1;


DUT• To do this the DUT must be instantiated

in the test bench• A name has to be specified duringreg sel;


p ginstantiation. (In this case, the name is‘mydut’ )

• Port mapping is done in instantiation• Port mapping is the logical connection of


#10 A 1’b1

• Port mapping is the logical connection ofthe names of the ports defined in RTLand in the Test bench

• The “.Y” represents the name of thet i RTL#10 A = 1’b1;

#10 sel = 1’b1;#10 B= 1’b1;

end

port in RTL• The “(Y)” represents the name of the

port in testbench• “.Y(Y)” logically maps the Y port of theend

endmodule( ) g y p p

RTL to the Y port in testbench


`timescale 1ns / 100ps module Test_mux_2to1; wire Y;reg A, B; reg sel;

• we can generate the required waveformon the A, B and SEL inputs in the initialblock

reg sel;


• Initial blocks start executing sequentiallyat simulation time 0

St ti ith th fi t li b t thinitial beginSel = 0; A = 0; B = 0;

#10 A 1’b1

• Starting with the first line between the“begin end pair” each line executesfrom top to bottom until a delay isreached.

#10 A = 1’b1;#10 sel = 1’b1;#10 B= 1’b1;

end

• When a delay is reached, the executionof this block waits until the delay timehas passed and then picks up executionend

endmodulep p p

again.

Understanding Test benchUnderstanding Test bench• Sel = 0; A = 0; B = 0;First of all, Sel is set to 0, then A, then B. Allthree are set to 0 at simulation time 0.

• #10 A = 1;;In terms of simulation, the simulator nowadvances by 10 time units and then assigns 1to A.

• #10 SEL = 1;#10 B = 1;

These two lines are similar to the one above. 10ti it ft A i t t 1 SEL i t t 1time units after A is set to 1, SEL is set to 1.Another 10 time units later (so we are now atsimulation time = 30 time units), B is set to 1.

Since our timescale compiler directive is set as`timescale 1ns / 100ps, one time unit is 1ns.

Waveforms captured in Xilinx ISimWaveforms captured in Xilinx ISim

Test bench for a 4 bit up counterTest bench for a 4 bit up counter

module my_counter (clock , reset , enable ,t t )

timescale 1ns / 100ps // timescale directivemodule my counter tb; // No portscounter_out );

input clock ; input reset ; input enable ;output [3:0] counter_out ;reg [3:0] counter out ;

module my_counter_tb; // No ports//Declare inputs as regs and outputs as wires

reg clock, reset, enable;wire [3:0] counter_out;

// Instantiation by giving a name and port mappingreg [3:0] counter_out ;always @ (posedge clock)beginif (reset == 1'b1) begin

// Instantiation by giving a name and port mappingmy_counter

mc1(.clock(clock),.reset(reset),.enable(enable),.counter_out(counter_out));Initial begin

counter_out <= 4'b0000; endelse if (enable == 1'b1) begin counter_out <=counter_out + 1; endend

Initial beginclock = 1; reset = 0; enable = 0;//Initialise values#5 reset = 1;#10 reset =0;#10 enable 1;end

endmodule#10 enable = 1;#100 enable = 0;endalways begin // clock pulse changes every 5ns#5 clock = ~clock;

endendmodule

Understanding the Test benchUnderstanding the Test bench

• In the above testbench for a counter we comeIn the above testbench for a counter we come across always block which is used to generate the clockthe clock

• initial and always blocks execute concurrently in every module at the start of simulationin every module at the start of simulation.

Waveforms captured in Xilinx ISimWaveforms captured in Xilinx ISim

Documents

Test Benches in Verilog