February 5, 2003

"Test and Debug""Test and Debug"sub-networksub-network

EUROSOC ProposalEUROSOC Proposal

February 5, 2003

Paradigm shiftsParadigm shiftsTesting cost may represent up to 50% of the Testing cost may represent up to 50% of the

manufacturing cost of SoCmanufacturing cost of SoC Sky-rocketing complexitiesSky-rocketing complexities Decreasing pin/gate ratioDecreasing pin/gate ratio Higher frequenciesHigher frequencies Decreasing product life cyclesDecreasing product life cycles

SoC TestingSoC Testing Hardware/software designsHardware/software designs IP-based designsIP-based designs Increasing use of analogIncreasing use of analog, mixed-signal, mixed-signal and RF and RF

IPs IPs

February 5, 2003

Paradigm shifts (2)Paradigm shifts (2)

New defects due to technology New defects due to technology evolutionevolution

Core-based testingCore-based testing Test of programmable (HW/SW) Test of programmable (HW/SW)

systemssystems Increase of temporary faults (transient Increase of temporary faults (transient

and timing faults)and timing faults)

February 5, 2003

Barriers to overcomeBarriers to overcome Development of nanometer fault models Development of nanometer fault models ATPG, BIST for real defectsATPG, BIST for real defects ReductionReduction of test of test executionexecution time time Power consumption during testPower consumption during test OOptimptimiizzed Test Resource Partitioning strategiesed Test Resource Partitioning strategies Obsolescence of IObsolescence of Iddqddq testing testing Analog BISTAnalog BIST Tolerance of temporary faults (Effects of cosmic Tolerance of temporary faults (Effects of cosmic

radiation, SEU defects)radiation, SEU defects) DfD methodologyDfD methodology

February 5, 2003

"Test and Debug" sub-network"Test and Debug" sub-network

Proposed Proposed Key Node:Key Node:– Christian Landrault (LIRMM/University of Christian Landrault (LIRMM/University of

Montpellier, France)Montpellier, France)– Erik-Jan Marinissen (Philips Research Erik-Jan Marinissen (Philips Research

Labs, The Netherlands)Labs, The Netherlands) 26 Institutions representing 26 Institutions representing 100+ 100+

researchersresearchers (most of our industrial (most of our industrial colleagues not yet includedcolleagues not yet included, 60+ and , 60+ and 200+ in QUEST EoI200+ in QUEST EoI))

February 5, 2003

Possible pPossible program of activitiesrogram of activitiesIntegrating activitiesIntegrating activities

Not yet formally defined between partners but almost all Not yet formally defined between partners but almost all participants have offered such activitiesparticipants have offered such activities

Activities designed to spread excellenceActivities designed to spread excellence Satellite-based E-learning on SOC Test and Dependability Satellite-based E-learning on SOC Test and Dependability

((TorinoTorino, INESC, LIRMM, Stuttgart, UPC), INESC, LIRMM, Stuttgart, UPC) Digital, Mixed-Signal and Memory Test Engineering Education Digital, Mixed-Signal and Memory Test Engineering Education

((LIRMMLIRMM, Agilent, Ljubljana, Stuttgart, Torino, UPC), Agilent, Ljubljana, Stuttgart, Torino, UPC)

Jointly executed researchesJointly executed researches Defect Based Test methods for nanometer ICs (Defect Based Test methods for nanometer ICs (Balearic Balearic

IslandsIslands, Bologna, Freiburg, INESC, LIRMM, UPC) , Bologna, Freiburg, INESC, LIRMM, UPC) + (Warsaw, + (Warsaw, Bratislava, TallinnBratislava, Tallinn))

Processor-based SoC Test and Debug (Processor-based SoC Test and Debug (TorinoTorino, Athens, INESC, , Athens, INESC, LIRMM, Piraeus) LIRMM, Piraeus) + LIP6+ LIP6

February 5, 2003

Possible pPossible program of activitiesrogram of activities

Jointly executed researches (cnt'd)Jointly executed researches (cnt'd)

Low Power TestingLow Power Testing ((LIRMMLIRMM, INESC, Stuttgart, UPC), INESC, Stuttgart, UPC) BIST of sequential circuits (BIST of sequential circuits (TallinnTallinn, Lingköping, Stuttgart), Lingköping, Stuttgart) Testing Techniques for Reconfigurable System-On-ChipTesting Techniques for Reconfigurable System-On-Chip

((LIRMMLIRMM, INESC, Innsbruck, Stuttgart, Torino, Twente, UPC) , INESC, Innsbruck, Stuttgart, Torino, Twente, UPC) Flexible Infrastructures for Testing Systems-on-a-ChipFlexible Infrastructures for Testing Systems-on-a-Chip

((SouthamptonSouthampton, ARM Ltd, Innsbruck, Stuttgart), ARM Ltd, Innsbruck, Stuttgart) Fault Tolerant SOCs (Fault Tolerant SOCs (BolognaBologna, Athens, LIRMM, Piraeus, , Athens, LIRMM, Piraeus,

Postdam, Torino, UPC)Postdam, Torino, UPC) Testable Design & Test of Embedded Analogue Cores in SoC Testable Design & Test of Embedded Analogue Cores in SoC

((TwenteTwente, INESC, LIRMM, Sevilla, TIMA) , INESC, LIRMM, Sevilla, TIMA) + (Cantabria)+ (Cantabria)

February 5, 2003

Possible pPossible program of activitiesrogram of activities

+ some orphans+ some orphans Hierarchical Test (Tallin)Hierarchical Test (Tallin) SOC testing of digital parts based e.g. on IEEE SOC testing of digital parts based e.g. on IEEE

P1500 standardP1500 standard (Bratislava)(Bratislava) Design of effective built‑in self‑test structures for Design of effective built‑in self‑test structures for

VLSI circuitsVLSI circuits (Gliwice)(Gliwice) CConvergence of verification and testingonvergence of verification and testing (Verona) (Verona)

February 5, 2003

List of top level researchers in List of top level researchers in this field this field

The European Test community is quite The European Test community is quite well organizedwell organized

European Group of the IEEE TTTC European Group of the IEEE TTTC ((CChairhair:: J. Figueras J. Figueras, Vice-Chair: Z. Peng, Vice-Chair: Z. Peng))

All top level European All top level European academic academic researchers included in the Eurosoc researchers included in the Eurosoc proposalproposal

Still to work on the industrial Still to work on the industrial participationparticipation

February 5, 2003

Academic participationAcademic participation

Athens (A. Paschalis)Athens (A. Paschalis) Balearic Islands (J. Segura)Balearic Islands (J. Segura) Bologna (C. Metra)Bologna (C. Metra) Freiburg (B. Becker)Freiburg (B. Becker) INESC (J.P. Teixeira)INESC (J.P. Teixeira) Innsbruck (S. Hellebrand)Innsbruck (S. Hellebrand) LIRMM (M. Renovell)LIRMM (M. Renovell) Piraeus (D. Gizopoulos)Piraeus (D. Gizopoulos) Postdam (M. Goessel)Postdam (M. Goessel) Sevilla (J.L. Huertas)Sevilla (J.L. Huertas)

Southampton (B. Al-Southampton (B. Al-Hashimi)Hashimi)

Stuttgart (H.J. Wunderlich)Stuttgart (H.J. Wunderlich) TIMA (S. Mir)TIMA (S. Mir) Politecnico di Torino (P. Politecnico di Torino (P.

Prinetto, M. Sonza Reorda)Prinetto, M. Sonza Reorda) Twente (H. Kerkhoff)Twente (H. Kerkhoff) UPC (J. Figueras)UPC (J. Figueras) ……………………