Temperature dependence of carrier transport in polycrystalline silicon

J.Y. Lee and F.Y. Wang * Hughes Research Laboratories, Malibu, California 90265, USA

The carrier transport in polycrystalline silicon was studied over a wide temperature range, from 20K to 300K, and for a number of dopant concentrations ranging from 1.3 x 1018/cm 3 to 2.6 x 101S/cm 3. A grain boundary carrier trapping model was used to explain the experimental results in this work. Carrier transport by thermionic emi- sion over the grain boundary potential barrier and thermionic field emission through the potential barrier were both included. Special attention was paid to carrier freeze- out a t low temperatures. The potential barrier height, VB, was shown to be an increas- ing function of temperature and a decreasing function of dopant concentration. The relative importance of thermionic emission and thermionic field emission was discus- sed.

1. Introduction

Polycrystalline silicon has many important applications in integrated circuit technology. Heavily doped films of polycrystalline silicon are used as gate electrodes and interconnections in silicon-gate integrated circuits. Lightly doped polycrystalline silicon films are frequently used as high value load resistors in static memory circuits. The carrier transport in polycrystal- line silicon has been investigated by a number of authors TM. Several models have been prop- osed to explain the electrical properties of polycrystalline silicon. The grain boundary carrier trapping model 1~4 postulates that there are a large number of trapping states at the grain boundary. These trapping states are capable of trapping carriers and thereby immobilizing them. Potential barriers are created at the grain boundaries which impede the motion of car- riers from one crystallite to the other and then limit the conductivity of polycrystalline silicon. The dopant segregation model 21'22 hypothesizes that the conductivity is limited by the segre- gation of dopant atoms to the grain boundaries where the dopant atoms become electrically inactive. There is also evidence 22'23 that both carrier trapping and dopant segregation play a role in determining the electrical properties of polycrystalline silicon. A drift-diffusion model proposed by Kim et al t5'17 regards the grain boundary as amorphous semiconductor in equilib- rium contact with crystalline grain. Most of the work on the electrical properties of polycrys- talline silicon in the literature was based on the carrier-trapping model. This approach was also adopted in this work. It should be noted that a certain portion of dopant atoms might be segregated at the grain boundaries. The effective dopant concentration was taken to be the total dopant concentration in this work.

Given the potential barrier at the grain boundary, there are a number of transport mechanisms by which carriers can move from one grain to the other. These mechanisms in- clude:

(i) thermionic emission (TE) over the potential barrier, (ii) thermionic field emission (TFE), or tunneling, through the potential barrier.

In order to explain their grain boundary resistivity at low temperatures Lu et al 7'9 introduced a grain boundary regular potential, q Z, representing the grain boundary scattering effect. The thermionic field emission through this grain boundary scattering potential was denoted

MICROELECTRONICS JOURNAL Vol. 17 No. 5 ~) 1986 Benn Electronics Publications Ltd, Luton 23

TFES. A similar grain boundary barrier was also used by Mandurah et al T M who attributed it to the higher energy gap of amorphous silicon. However, Lu et al found it necessary to vary both the scattering barrier height, X', and its width, 6 , as the temperature-d~anged in order to fit the . . . . experimental data. An effective numberl0 of grains, .Neff' was .als~ reqmred" in place of the physical numbers of grams, Nr, at high fields .The physlcal meaning of these parameters, X, ~ and Neff, are therefore not very clear. The reason that Lu et al introduced the grain boundary scattering potential was to compensate for the downward bending of In p versus l/ kT curve at low temperatures. However, there are a number of precautions that must be taken care of at low temperatures. First, it is usually assumed that the signal is small, i.e., the applied voltage across each grain, Va, is much smaller than 2 kT/q. This condition is recjuired for linearizing the I-V curve, which in turn gives rise to the concept of grain boundary resistiv- ity, p ~. However, the assumption of small signal is not a good approximation at low tempera- tures. For example, a 50/xm long polysilicon resistor with grain diameter of 0.1/xm has 500 grains along its length. At 5V bias, the applied voltage across each grain is 10 mV. This is equal to 2kT/q at about 600K. The voltage across each grain therefore becomes comparable to 2kT/q at low temperatures and high voltages. The I-V curve becomes increasingly non-linear and the exact magnitude of p ~ becomes increasingly more difficult to define. In this work, comparison of theoretical and experimental results was therefore based on the full I-V characteristic rather than the small signal resistivity, p u.

Secondly, carrier freeze-out becomes increasingly significant as temperature decreases z6. Clear distinction must be made between dopant concentration and carrier concentration. Freeze-out occurs first and unionized dopant atoms do not contribute to the carrier transport process. For this work, freeze-out of carriers was included in all of the discussions. Neglect of freeze-out will cause a significant difference at low temperatures as can be seen in the calcula- tion of the relative importance of TE and TFE current components. This will be discussed in Section 3.3. ,

It is thus clear that in order to fully understand the carrier transport mechanism in polycrys- talline silicon, investigation at low temperatures must be undertaken. Few attempts have

6 9 o 14 been made in the past. Lu et al �9 made measurements down to -150 C. Tarng measured the characteristics of oxygen-rich polycrystailine silicon films down to 233K. In this work, the measured temperature range was extended to 20K. Some of the result was reported previ- ously zS. In this paper, the polysilicon I-V characteristic was investigated as a function of both temperature and implant dosage and the carrier transport was studied in more detail.

�9 H u g h e s C a r l s b a d T e c h n o l o g y C e n t e r , C a r l s b a d , C A 92(~q8, U S A

2. Experiments Polycrystalline silicon film was deposited over thermally oxidised silicon wafers with a low pressure chemical vapor deposition (LPCVD) to a thickness of 400 nm. The deposition temp- erature was 630~ and the pressure was kept at 0.26 Torr.

12 2 14 "~ Phosphorus implant was made with doses ranging from 5• /cm to 3• /cm- at an 15 2 energy of 50 keV. A heavy phosphorus implant (2x 10 /cm ) was then made at both ends of

the polysilicon film to ensure proper ohmic contact. After implantation, the polysilicon film was patterned and thermally oxidized at 1000~ to give a surface oxide of 200 nm thickness. The total furnace time at 1000~ was 80 minutes. The final polysilicon film thus had a thick- ness of about 300 nm. Contacts were subsequently made to the heavily doped n + regions and aluminum metalization was used for interconnection.

The I-V characteristics for a number of samples with implant doses ranging from 4• 1013/ cm 2 to 8• 10t3/cmZ were measured at various temperatures between 20K and 300K. The low temperature measurement was made with a liquid Heli-Tran refrigerator (Air Products Model LT-3-110). The polycrystailine silicon grain size after process was studied with transmission electron microscopy. A similarly prepared polysilicon sample with 8• 1013/cm 2 phosphorus implant was examined by TEM. The grain size in this polycrystalline silicon sample was found to be ranging from 30 nm to 100 nm. For calculation purposes in this work, an average grain size of 50 nm was used. 24

3. Results

I V VB

-r(a)

3.1 I-V Characterist ics

The nett current resulting from an applied voltage for n-type polycrystalline silicon was shown to be4'6'9: (1) I = 2AA*T2e -- (Ec -- EF) / kT I

k2Ng kTI + J o " kT ' kT/'U(~.)d~.~

where

= current = applied voltage, = potential barrier height,

= e x p ( - -~VB y(a)] ,

t. E00 a = E/q VB,

E~ = (qh/8,'r) (ND/m*s lh

y(a) = ( l - - a ) V 2 + a l n [ / - - x ] l - ~ 1 _ V ~

ND = dopant concentration, A = polycrystalline silicon cross-sectional area perpendicular to current flow, A* = Richardson constant, Ng = total number of grains = D/L, D = polycrystalline silicon length, L = average grain diameter, e = permittivity of the semiconductor, E = electron energy, k = Boltzmann's constant = 8.62 • 10 -5 eVIK, T = absolute temperature and q = electronic charge = 1.602 • 10 19 coulomb.

An energy band diagram for n-type polycrystalline silicon is shown in Fig. 1. In the bracket of equation (1), the first term represents the thermionic emission component and the second term is due to thermionic field emission. The equation derived by Lu et al 6 differs from that of Martinez and Piqueras 4 in the expression Eoo. The two expressions of Eoo differ by a factor of 2. This arises from the semiconductor-to-semiconductor model assumed by Lu et al. This semiconductor-to-semiconductor model was used in the present work to compare with ex- perimental data. In this I-V expression, all parameters except VB are experimentally deter- mined. The Richardson constant A* is not known very well at low temperatures. But the de- pendence of current on A* is only linear and the curve-fitted barrier height was shown to be not overly sensitive to the Richardson constant 25. A value of 252 amp/cm~/K 2 was used in this work. A typical plot of polycrystalline silicon I-V characteristic is shown in Fig. 2. The dots represent measured data and the dashed lines represent least-square-fitted curves with grain boundary potential barrier height, VB, as the single varying parameter. When temperature is lowered below room temperature, the number of ionized carriers decreases due to freeze- out. The value of dopant concentration, ND, in the expression of E00 should be replaced by the actual carrier concentratign, n. This procedure was used in comparing experimental data with

25

E c

E F

E v

equation (1) in this work. Excellent curve fitting was achieved for temperatures above 60K. Below 60K, the quality of curve fitting was not as precise but was still quite reasonable, consid- ering the small magnitude of current involved. The sheet resistances, Rs,:~f polycrystalline silicon resistors measured at low voltages are shown in Fig. 3. The slopes of the In Rs versus 1/ T curves are continuously varying and no single activation energy can be deduced.

w I }"'--(DEPLETION ~ ! - " W I WIDTH) I I I

I ! i I I I I

,,~ [~ ~ ' /~

J J

L (GRAIN DIAMETER)

"~q V B

I I I I

J_

J i m I I ~ . ~ ~ . . . .

l i I I I I

- - t ~'-- (GRAIN BOUNDARY WIDTH)

X =~a

:l i i l I

I I

!J I -l-

I I I I I 1 1 I

x = O x = a t X

Fig. 1 Energy hand diagram for n-type polycrystalline silicon.

10-7

10 8

tO'9

_ _ . � 9 2 , J t K

f~

I / " . . . . . . .

I i t i i i 3 S 10 IS 2O

VOLTAGE (VOLT) Fig . 2 P o l y c r y s t a l l i n e s i l i c o n 1 - V c h a r a c t e r i s t i c s at v a r i o u s t e m p e r a t u r e s . T h e d o t s r e p r e s e n t m e a s u r e d d a t a a n d t h e

d a s h e d l i n e s r e p r e s e n t l e a s t - s q u a r e - f i t t e d - c u r v e s .

26

Er

EF~

E I

1011

':3 O to

1010

109

108

o.9. g Z

107

106

10 5

/ ' ,4 X 10131CM 2

�9 5 X 1013/CM 2

[ ] G X 1013/CM 2

O 8 X 1013/CM2

I 1 I 104 I I 10 20 3O 40 50

103/T (K -1)

Fig. 3 Polycr}+stalline silicon sheet resistance versus inverse temperature . The samples were implanted ~Hth 4 x 10 ~3, 5 x 1013, 6 x l 01~ and 8X 1013/r z phosphorus dosages, respectively.

141:28 . I

IMPLANT DOSAGE

4 x 1013/cm 2 5 x 1013/crn 2 6 x lol3/cm 2 7 x 1013/cm 2 8 x 1013/cm 2

0.192 0.18G O.179 0.175 0.170

0.153 0.146 0.138 0.133 0.128

0.126 0.119 0.114 0.108 0.103

0.091 0.084 0.079 0.075 0.07 I

0.059 0+053 0.047 0.043 0.040

0.037 0 032 0.026 0.025 0.023

0.012 0.009 0.007 0.OO5 0.002

297K

200K

150K

100K

60K

40K

20K

TABLE I Potential barrier height VB (expressed in volts) as functions of temperature and phosphorus implant dosage

27

3.2 Potential barrier height, VB

The potential barrier height, VB, of polycrystalline silicon was obtained by c emparing experi- mental data with equation (1). The values of V~ obtained for polysilicon resistors implanted with a phosphorus dose of 4 x 10 t3, 5 X ]0 ~3, 6x 10 ~3, ? • ]0 ~3 and 8x 10~3/cm 2 are shown in Table 1 and plotted in Fig. 4. For clarity, Vn values for only three of the five dosages are shown. For each of the implant dosages, Ve is shown to be an increasing function of temperature in the range between 20K and 300K. In Fig. 5, V~ is plotted as a function of implant dosage with temperature as the parameter. The grain boundary potential barrier height was shown to be a decreasing function of implant dosage, or equivalently, dopant concentration.

The grain boundary potential barrier height was calculated by Baccarani et al 3. When the dopant concentration is larger than the critical impurity concentration ND*. the po]ycrysta]- Iine silicon crystallites are partially depleted and the potential barrier height can be expressed as:

q VB = EF -- Et + kT In 2[q NJ(8e ND q VB) % -- ] ] , (2)

where Nt is the trap density and Et is the trap energy level referred to the intrinsic Fermi level. When ND < No*, the polycrystalline silicon grains are fully depleted. The potential barrier height is given by:

VB = qL 2 ND/8C (3)

A search of the literature shows that most of the values of trap density, Nt, at room tempera- ture were found to be of the order of 2x 10tZ/cm 2 to 4x 1012/cm 2. With this kin d of trap density, and assuming Et = 0, the polycrystailine silicon samples we have are partially depleted at room temperature. Substituting VB into equation (2), the trap density, Nt, was obtained. The result is shown in Table 2. The trap density, Nt, at room temperature is shown to group closely

12 2 around 4.5x10 /cm. This result is in good agreement with the trap density obtained by Seto 2, Lu et al s's and Baccarani et al 3. The trap density is seen to be a slightly increasing func- tion of implant dosage.

" - - I - I ' - I " I " " -1 . . . . . . . I ~ ' ! ~ - - - ~ ' ~

t m v t ^ t J l I)()~;AL;I

t I �9 �9 t O t 3 , o " 1

O 6 �9 t ~ l l ' l t ' m ?

>

<

2 3 4O 6O 100 1SO 29Q 2 5 0

T o)r

Fig. 4 Grain boundary potential harr ier height, V~, as a function of temperature . The pol)silicon resistors were implanted with 4X 10 t~, 6 • 10 t3 and 8X lOU/cm 2 phosphorus dosages.

28

II } [ I [ l --" I 1 l ' I 1~11.'-

>

I

0 0 5

~ 1 5 0 K

5 6 7 B Ir.~PLANT {)OSAGE, �9 1013/~ 2

Fig. 5 Grain boundary potential barr ier , VB, of polycrystalline silicon as a function of phosphorus implant dosage.

PHOSPHORUS DOPANT TRAP DENSITY IMPLANT CONCENTRATION, Nt ~ cm-2 DOSAGE, r

cm-2

4 x 1013 1.3 x 1018 4 .20 x 1012

5 x 1013 1.6 x 1018 4.42 x 1012

6x 1013 2 .0x 1018 4 .49x 1012

7 x 1013 2.3 x 1018 4.66 x 1012

8 x 1013 2.6 • 1018 4.75 x 1012

GRAIN BOUNDARY TRAP DENSITY N t AT ROOM TEMPERATURE AS A FUNCTION OF DOPANT CONCENTRATION

TABLE II Grain boundary trap density N I at room temperature as a function of dopant concentration

29

3.3 TFE/TE ratio

The two terms in the bracket of equation (1) represent thermionic emissioav'hnd thermionic field emission, respectively. Their ratio can be calculated and expressed as:

TFE/TE = (qVB/kT)(1 e (1 - -*~) (~ .V~/kT)"E(~)d~ (4) ) v

The TFE/TE ratios were calculated for the polycrystalline silicon resistors used in this work. The result is listed in Table 3 and plotted in Fig. 6 for three of the implant dosages. For clari~y, TFE/TE ratios for samples implanted with the other two dosages are not shown. At low lemp- erature, the TFE current is much smaller than the TE current. As temperature increases, this ratio increases and reaches a maximum of around 150K. A further increase of temperature de- creases this ratio slightly.

O I- < a:

LId

"l 1.4-

1.3-

1.2-

1.1-

1.0-

0.9-

0.8-

0.7-

0.6

0.5

0.4

0.3

0.2

0 , I -

0 0

I I | I

IMPLANT DOSAGE

ZX 8 x 1013/cm 2

[ ] 6 x 1013/cm 2

O 4 x 10131cm 2

20 40 60 100 150 200 250 300

T,~

/

Fig. 6 The ratio of thermionic field emission (TFE) and thermionic emission (TE) current components as a function of temperature. The polysilicon resistors were implanted ~i th 4X 10 t3, 6x1013 and 8• 10t3/cm z phosphorus dosages.

Lu et al 9 suggested that the thermionic field emission was significant at room temperature and became dominant at low temperatures. A similar opinion was expressed by Mandurah et al tl. The result from this work shows that this is not the case. The TFE/TE ratio as shown in equation 4 depends on the relative magnitude of the potential barrier height, qVB, and the thermal energy, kT. Although it is true that the electrons have lower energies at low tempera- tures, the potential barrier also decreases with temperture. The ratios of qVB/kT as calculated from Table 1 show a,maximum around 100K and have a temperature dependence very similar to that of TFEfTE. This temperature dependence can be understood as follows. At low temp-

30

297K

200K

150K

100K

60K

40K

20K

IMPLANT DOSAGE

4 x 10131crn 2 5 x 1013/cm 2 6 x 1013/cm 2 7 x 1013/crn 2 6 x 1ol3/cm 2

1.07 1.11 1.15 1.17 1,19

1.22 1.26 1.26 1.31 1.33

1.24 1.28 1.31 1.33 1.34

1.08 1.09 1.11 !.12 1.13

0.66 0.66 0.65 0.65 I 0.64

0.29 0.30 0.30 0.31 0.30

0.0 t 6 0.015 0.008 0 00 O 0.020

TABLE III TFE/TE ratio as functions of temperature and phosphorus implant dosage

eratures, the number of free carriers increases with temperature and, provided that the trap density does not change very rapidly with temperature, the depletion region width at the grain boundary decreases with temperature. Therefore, there are more energetic electrons that can tunnel through a thinner potential barrier as temperature increases. This goes up to the temperature where most of the electrons are energetic enough to cross over the barrier rather than through it. From this temperature on, TFE/TE starts to decrease with increasing temperature. Lu et al 6"9 calculated the ratio of thermionic field emission and thermionic emis- sion components'(TFE/TE) for their sample from 150~ to -150~ They showed a sharply decreasing TFE/TE ratio with increasing temperature. We found that their result was a con- sequence of assuming a constant dopant concentration in the expression orE00 for all temper- atures. In this work the actual carrier concentration was used to replace No in E00.

4. Conclusion

We investigated the polycrystalline silicon I-V characteristic as a function of temperature and implant dosage over a wide temperature range from 20K to 300K. The I-V curves were analysed with a carrier transport model based on thermionic emission and thermionic field emission at the grain boundaries using a single parameter, VB. The potential barrier height, VB, was shown to be an increasing function of temperature between 20K and 300K. VB was also shown to be a decreasing function of dopant concentration. The TFE/-/'E ratio was shown to be an increasing function of temperature at low temperatures and had a maximum around 150K. The value of trap density, NI, calculated at room temperature was in good agreement with results obtained by other authors. The trap density was shown to increase slightly with implant dosage.

5. References

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31

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