Embed Size (px)
DESCRIPTION
TELL40 VELO time ordering. Pablo Vázquez , Jan Buytaert , Karol Hennessy , Marco Gersabeck, Pablo Rodríguez. Time ordering. Packet (34b)=ASIC(4b)+ SuperpixelAddress (13b )+BCID(9b)+Hitpattern(8b) Data packets arrive to the TELL40 disordered in time - PowerPoint PPT Presentation
Citation preview
P. Vazquez (U. Santiago) 1
TELL40 VELO time ordering
Pablo Vázquez, Jan Buytaert, Karol Hennessy, Marco Gersabeck, Pablo
Rodríguez
12/12/2013
P. Vazquez (U. Santiago) 2
Time ordering
• Packet(34b)=ASIC(4b)+SuperpixelAddress(13b)+BCID(9b)+Hitpattern(8b)
• Data packets arrive to the TELL40 disordered in time• Time ordering = grouping of packets by 9bit BCID value• Grouping is done in 2 steps:
– Router based on 4-bits of BCID (MSB or LSB, see later) – Memory storage remaining 5-bits BCID
12/12/2013
Goal of this talk
Decoding routing memory
Data processing
“Standard LHCb” “VELO”
P. Vazquez (U. Santiago) 3
4-bit BCID VELO packet router
• Non blocking scheme using internal memory (FIFO’s)• Different number of input links considered:
– 16 @160 MHz (320) for a half (full) module as described in the TDR
– 10 @320 MHz for a full module, when reducing optical links
• 2 architectures under study:– “Cascade” of 1-bit router elements. Each element routes
packets based on 1-bit– “crossbar” : single stage N x 2M ports routes packets based on
all bits
• Use of altera library megafunctions: lpm_scfifo, lpm_compare...
12/12/2013
P. Vazquez (U. Santiago) 4
1-bit router elements
12/12/2013
Data 0
w0FlipFlop0
FlipFlop1
Out 0
Out 1
r0
r1
If (BID[i]=0) Write FlipFlop0else Write FlipFlop1
FIFO_00
FIFO_01Data 0
Data 1
w0
w1
If (BID[i]=0) Write FIFO_00else Write FIFO_01
FIFO_10
FIFO_11
MUX2-to-1
FLIPFLOP
MUX2-to-1
FLIPFLOP
Out 0
Out 1
r0
r1If (BID[i]=0) Write FIFO_10else Write FIFO_11
MoreFull?
MoreFull?
2x2 router element uses 4 fifos while 1x1 router element doesn’t use fifos
P. Vazquez (U. Santiago) 5
10x16 router with “1-bit router elements”
12/12/2013
xxxx
xxxx
xxx1
xxx0
2x2 port 1-bit router
xx11
xx01
1x2 port1-bit router
1111
0000
P. Vazquez (U. Santiago) 6
FPGA resources and max speed
• Several configurations compiled for the actual device: altera stratix V 5SGXEA7N3F45C2
• Router can run @ 320 MHz with 1-5% of resources with a cross-sectional bandwidth 1.6-2.6 higher than required (2G pakets/s peak for full module)
12/12/2013
In x Out links 16x16 (TDR) 10x16 (Optimized)Fifo depth (words) 512 512Logic utilization (in ALMs) 3,582 ( 2 % ) 2,722 ( 1 % )Total registers 3839 4305Total block memory bits 58,920 ( < 1 % ) 1,274,940 ( 2% )M20K blocks 128 ( 5 % ) 84 ( 3 % )Fmax 85ºC (MHz) 340 361Bandwidth links x 320MHz (G packet/s) 5.12 3.2
P. Vazquez (U. Santiago) 7
Simulation
• Generate simulated input data using the known distribution of the event size and latency (see next slides)
• Aim: the dependency of packet loss vs fifo depth and routing strategy (MSB vs LSB bits) – Aim: data packet loss << 0.1%?
• Every 34-bit FIFO is allocated on a M20K memory block => optimal is 512 x 40bit. Could be extended
• We will start simulating the 10x16 @320 MHz case
12/12/2013
8
Event size distribution
• The 20 inputs of a full module are below 40% of peak packet rate capacity
12/12/2013 P. Vazquez (U. Santiago)
Data from M
artin van Beuzekom
At the input of router @320 MHz
Links 1-8 mean 0.37 pkt/clkLinks 9-12 mean 0.31 pkt/clkLink 13,14 mean 0.25 pkt/clkLink 15,16 mean 0.30 pkt/clkLink 17,18 mean 0.26 pkt/clkLink 19,20 mean 0.16 pkt/clk
P. Vazquez (U. Santiago) 9
Simulation latency
• Packets arrive at the tell40 with variable latency:
• Routing with the MSB bits generates data rate peaks 10 times higher than routing with LSB bits – increases packet loss probability
(but maybe still acceptable),– but is nicer for MEP: consecutive
events are stored in the same memory
– Maybe better suited for data-processing (idle time between peaks)
12/12/2013
prob
abili
ty
P. Vazquez (U. Santiago) 10
Summary
• TELL40 VELO router block has been investigated
• Compilation of designs based on 1-bit router elements shows that with 1-5% of FPGA resources, the router can handle easily the required bandwidth
• Simulations with self-generated data will show the packet loss (with respect to fifo depth and MSB/LSB routing strategy)
12/12/2013
P. Vazquez (U. Santiago) 11
backup
12/12/2013
P. Vazquez (U. Santiago) 12
10x16 router 1 stage
12/12/2013
FIFO_0Data 0
Data 9
w0
w9
FIFO_9
MUX10-to-1
FLIPFLOP
MUX10-to-1
FLIPFLOP
Out 0
Out 15
r0
r15
BCID=0000
BCID=1111
