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Telematics – Navigation – Multimedia
July 2010
www.BDTIC.com/ST
Basic GPS system
SMA661
Position
LNA
RF frontend
Baseband
Antenna
LNA
STA5620
STA2058
www.BDTIC.com/ST
nom. 2.7 V
SMA661In Out
1.57542 GHz18 dB
NF = 1.4 dB
This device is qualified according to AEC-Q100 but cannot be tested in automotive grade (waiver needed).
1.2mm
1.6
mm
SM
A 6
61
SOT666 package
SM
A 6
61
SMA661 – low-noise amplifier
Gain 18 dB
Noise figure 1.4 dB (1.15 typ.)
1 external component
1.2 x 1.6 mm footprint
www.BDTIC.com/ST
~~PLL
~~~ Clk
1.575 GHz 4.092 MHz
1.571328 GHz
16.368 MHz
2-bit ADC~~~
AGCIF filter
0° 90°
RFA
SPI
SIGN
MAG
GPSCLK
CE
SCLK
MOSI
Polyphase filter
~~ System clock
RFin+
16.368/19.2 MHz
XCLK
Divider
16.368/19.2 MHz
MISO
Test
TST_CLKTST_EN1TST_EN2TCXO STA5620C = Consumer
STA5620A = Automotive10 to 40 MHz
BiC
MO
S default
Local oscillator
STA5620 HP-GPS frontend
www.BDTIC.com/ST
~~PLL
~~~ Clock
1.575 GHz 4.092 MHz
1.571328 GHz
Local oscillator
16.368 MHz
3-bit ADC~~~
AGCIF filter
0° 90°
LNA
SPI
SIGN
MAG1
GPSCLK
CE
SCLK
MOSI
Polyphase filter
~~ System clock
LNAin+
16.368 MHz
XCLK
Divider
26.0/19.2 MHz
MISO
Test
TST_CLKTST_EN1TST_EN2TCXO
RFin+
26.0 MHz
MAG2
Mode
RFsel
BWsel
GPS: 2 MHz
Galileo: 4 MHz
65
nm
CM
OS
Total power consumption < 25 mW
LNA
included
16.368/26.0
default
GPS/Galileo
bandwidth
3-bit
ADC
QFN32
default
STA5630 – Galileo GPS frontend
www.BDTIC.com/ST
Highly-integrated solution: embedded memories, CAN, GPS
ARM7TDMIFlash
256K
+ 16K
SR
AM
64
K
EM
I
ARM7 native bus
APB 1 APB 3 APB 2
Vreg
VStdby
Standby/
wake-up
controller
PLL/clock
controller
JTAG
STA2058 Teseo
www.BDTIC.com/ST
0.18 µm technology, 3.3 V single supply, low power, -40 to +85 °C
ARM7TDMI, 32-bit RISC engine, JTAG
Embedded 256 Kbyte + 16 Kbyte Flash, 64 Kbyte SRAM
External memory interface: 4 banks and up to 64 Mbytes
16-channel, high-performance GPS correlator and DSP (STMicroelectronics IP)
Electrically isolated real-time clock with wake-up capability
Two CAN controllers (CAN protocol rev. 2.0 part A and B) up to 1 Mbit/s
Four 16-bit multipurpose timers (capture, compare, count, PWM)
Four UARTs, two SPI, two I²C and USB for serial communications
Smartcard interface capability (ISO 7816-3 including clock generation)
Watchdog and wake-up controller (RTC or/and external event)
HDLC controller (including NRZI, FM0 and Manchester encoder)
4-channel 12-bit analog-digital converter (sigma-delta)
On-chip voltage regulators for CPU and core logic
STA2058 Teseo
www.BDTIC.com/ST
STA2058 Teseo – two chips – one package – no stacked die
Automotive qualification according to AEC-Q100
STA2058
STA5620
Baseband
Frontend0.8 pitch
11 m
m
7 mm
Multi-chip solutions
www.BDTIC.com/ST
Vreg
32.768 kHz
TCXO
2.7 V
Vant 2.7 V
Vcc
Antenna
UART
USB
CAN
3.3 V
16.368 MHz
F.Henkel / 22.11.2010
Gnd
SPI
I²C
2.7 V
JTAG
nRSTIN
nSTDBYIN
BOOTEN
Basic circuit diagram
STA2058 Teseo multi-chip module
SMA661
www.BDTIC.com/ST
ARM926 EJ
DSP and
Java
extension
128-K
byte
SR
AM
+
512-b
yte
sta
nd
by
32-Kbyte
ROM
4 x MSP Dual
8-chan. DMA
DDR RAM
controller
I-Cache
16K
JTAG
traceD-Cache
16K
1 x IrDA
3 xUART
2 x CAN
2 x SSP
3 x I²C
NOR/NAND
Flash
controller
AHB/APB
bridge
32-channel
high-
performance
GPS correlator
with DSP
LCD
ctrl.
FS-USB
HS-USB
SR
CAHB/APB
bridge
AHB/APB
bridge
AHB/APB
bridge
AHB bus, 5 x 32-bit buses
STA2062 Cartesio
www.BDTIC.com/ST
ARM926 EJ-S CPU @ 260/351 MHz
90 nm HCMOS process
ARM DSP (single-cycle MAC) and Jazelle Java extension for fast processing
SDRAM/mDDR-DRAM, NAND/NOR Flash support
High-performance, 32-channel GPS correlator with DSP + ARM7TDMI
Rich offer of serial communication channels (UART, SSP, I²C)
Two CAN controller (CAN 2.0 B)
Two USB dual-mode controller (On-The-Go and device mode, 1xFS,1xHS)
Hardware sample rate converter (44.1 kHz < > 48 kHz, etc.)
Multi serial ports (for I²S, PCM, T1/D1, SPI, AC97 programmable)
Two Secure Digital and MultiMediaCard interfaces
C3/block decoder for CD drive
LFBGA 361 package (0.8 pitch)
STA2062 Cartesio
www.BDTIC.com/ST
STA2062
SDRAMFlash
Power supply USB SDIO
Audio codec
STW5094
Bluetooth
ULPI
L 9
61
6
Ph
y
CAN PHY
CAN
Audio USBAnalogue
12 Mbit
Full Speed
480-Mbit
High Speed
to car radio,
hands free car kit
to car body
to mobile phone,
iPOD, MP3 player
to Memory Stick
to SD Card
MOST
bus
Mu
ltic
ha
nn
el
se
ria
l p
ort
MOST
USB PHY
High Speed
STULPI01
Bluetooth
STA2500D
Multichannel
serial port
max. 1024 x 1024
TFT screen
L 9
61
6
Ph
y
STw42xxPower controller
Non automotive
Communication gateway
www.BDTIC.com/ST
STA 2064/65 Cartesio+Telematics and navigation processor
Blocks in green are new to Cartesio+
DDR2 Flash
ARM1176 JZ
JAVA
extension
32
-Kb
yte
SR
AM
+
51
2-b
yte
sta
nd
by
32
-Kb
yte
RO
M
4 x MSP4 x DMA
DD
R/D
DR
2
co
ntr
oll
er
I-Cache
32K
JTAG
ETraceD-Cache
32K
Smartcard
3 xUART
2 x CAN
2 x SSP
3 x I²C
NO
R/N
AN
D
Fla
sh
co
ntr
oll
er
AHB/APB
bridge
32-channel
high-
performance
GPS correlator
GPS/Galileo
2/3 D
graphics
USB
USB
AHB/APB
bridge
AHB/APB
bridge
AHB Bus / 9 x 32 Bit Buses
32
Bit
Phy.2.0
Phy. 1.1
ULPI
16
Bit
533 MHz
Video in
LC
D
ITU
BT
65
6
US
B2
.0
SR
C.
STA2064/65 Cartesio+
www.BDTIC.com/ST
STA 2064/65 Cartesio+
ARM1176 JZF CPU @ 533 MHz (automotive)
55 nm HCMOS process
Jazelle extension for fast Java processing and floating point unit
Mobile DDR and DDR2-DRAM (2xCS, 1 Gbit each), NAND/NOR Flash support
High-performance, 32-channel GPS correlator with DSP + ARM966
Video input port, JPEG and 2D/3D graphics accelerator and LCD controller
Rich offer of serial communication channels (UART, SSP, I²C)
Two CAN controllers (CAN 2.0 B)
Two USB 2.0 dual-mode controllers (2xHS, 1x 2.0 Phy, 1 x 1.1 Phy)
Hardware sample rate converter (44.1 kHz < > 48 kHz, etc.)
Multi serial ports (for I²S, PCM, T1/D1, SPI, AC97 programmable) and S/PDIF
Three Secure Digital and MultiMediaCard interfaces
10-bit ADC with 8 inputs (touchscreen support)
C3/block decoder for CD drive
STA2064: TFBGA 289 package (0.8 pitch), limited functions
STA2065: LFBGA 372 + 100 package (0.65 pitch), full functionality
www.BDTIC.com/ST
GPS
Subsyst.
DDR2-DRAM
NOR Flash CPU
ARM 1176
2D/3D
TFT
STA5630
UL
PI
DDR
ctrl.
Flash
ctrl.
HS USBCAN 1
L 9616
CAN 2
L 9616
FS USB
GPS/Galileo
Comms
A/DTouch
4 x UART
3 x I²C
2 x SSP
PLLs
PMC4 x MSP
S/PDIF
GPIO
480 Mbit/s 12 Mbit/s1 Mbit/s1 Mbit/sHS USB
480 Mbit/s
USB0USB1
3x
ES
DC
AN
24
-2B
L
US
BL
C6-4
max. 1024 x 1024
Touchscreen
Basic Cartesio+ system
STA 2065
US
BL
C6-4
www.BDTIC.com/ST
Feature STA2062 Cartesio STA2064/5 Cartesio+
Main processor ARM946 ARM1176
Main processor speed/automotive 325 MHz/351 MHz 533 MHz/624 MHz
Caches 16k + 16k 32k + 32k
Floating point unit no yes
SRAM embedded 64 Kbyte 32 Kbyte
Number of system buses 5 x 32 bits 9 x 32 bits
System bus speed 166 MHz 208 MHz
DRAM support SDRAM/mobile DDR Mobile DDR/DDR II
DRAM bus width 16 bit 16/32 bit
2D/3D graphics accellerator none yes
JPEG H/W accellerator none yes
Video input port none CCIR 656
USB controller (dual role) 1 x USB1.1 ,1 x USB2.0 2 x USB 2.0
USB physical layer device 1 x USB 1.1 1 x USB 2.0, 1 x USB 1.1
SD/MMC card interfaces 2 x 3 x
A/D converter and touchscreen control none 10 bit, 8 channel
Smart card interface none yes
GPS processor ARM7TDMI ARM946
GPS correlator GPS GPS and Galileo
GPIO domain voltages 1.8 V and 2.5 V 1.8 V, 2.5 V and 3.3 V
Cartesio versus Cartesio+
www.BDTIC.com/ST
3GNSS systems and telematics controller
GNSS RF
SQI
ARM946
Fle
xib
le s
tati
c
me
mo
ry c
on
tro
lle
r
AHB bus
APB 1 APB 3 APB 2
PLL/clock
controllerJTAG
I-Cache
16K
D-Cache
8K SR
AM
25
6 K
byte
or
tig
htl
y c
ou
ple
d S
RA
M
16-Kbyte
boot
ROM
SD/MMC
card interface
NOR, SRAM
10-bit
ADC
Se
ria
l q
ua
d
me
mo
ry i
nte
rfac
e
208 MHz
LNA
V core
V stdby
V low
Standby/wake-up
controller WAKE
STDBY
1.62-3.6 V
1.8 V
1.8 V/3.3V
STA8088 Teseo II
www.BDTIC.com/ST
STA8088 Teseo II
55 nm technology, 1.8 V single supply, -40 to +85 °C, AEC-Q100
ARM946, 32-bit RISC engine with 16K I-Cache + 8K D-Cache (opt. TCM)
Embedded 256 Kbyte SRAM and 16 Kbyte boot-ROM
FSMC for static memories (NOR-Flash, SRAM) and SQI (serial SQI-Flash)
32+2-channel, high-performance G3 correlator (GPS, Galileo, GLONASS)
Embedded GPS/Galileo/GLONASS radio frontend
Isolated real-time clock with wake-up capability
CAN controller (CAN protocol rev. 2.0 part A and B) up to 1 Mbit/s
10-bit successive approximation A/D with up to 500 ksps, 8 inputs
Four 16-bit multipurpose timers (capture, compare, count, PWM)
Three UARTs, SPI, I²C, MSP (I²S) and USB 2.0 OTG for serial communications
SD/MMC card interface
Watchdog and wake-up controller (RTC or/and external event)
LFBGA 153 package, 9 x 9 mm, 0.65 mm pitch
www.BDTIC.com/ST
1 RF path, 2 IF paths
GPS/GAL SAW
GLONASS SAW
Dual filter solution
SAW BPF
Phone reject
L1 Band
1601.718 GHz
1575.42 GHz
Sensitivity: -161 dBm
TTFF hot: 1 sec.
TTFF cold: 35 sec.
GPS Galileo GLONASS
1575.42 1602.0(K = 0)
1598.0625(K = -7)
1605.375(K = +6)
1MHz
2MHz
-4MHz +3MHz
Target specification
STA8088 Teseo II
GPS – Galileo – GLONASS
www.BDTIC.com/ST
ADC
DAC
Audio DSP
Class D
amplifier
I²CI²CLED
driver
14.4 V
5.0 V
TESEO IIFDA001
1.8 V
5.0 V
USB
Vcore
1.2 V
Vbkp
1.2 V
VRF
1.2 V
GPS
GalileoGLONASSI²S
Charger
CAN
RTC
Audio
AUX
Output
amp.
GPIO
CA
N 1
CA
N 2
I²S
Airbag
signal
SOS
GSM
HSDPA
UMTS
LTE
Standardized modem
with common API
eCall specific
software
Common modem API
14.4 V
4.6 V
eCall/Telematics system
www.BDTIC.com/ST
Radio/navigation
processor
Navi, multimedia,
storage, connectivity
Telematics
GPS, Galileo,
GLONASS
eCALL
GPS, Galileo,
Glonass
Analog tuner
AM/FM
TMC
Digital tuner
AM/FM/DAB
Sat radio
Connectivity
Bluetooth, Wi-Fi
Power
managementRegulator,
supervision
Telematics/navitainment systems
www.BDTIC.com/ST
www.st.com/gps
More information
www.BDTIC.com/ST