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Dr. Hugh Blanton

ENTC 4307/ENTC 5307

Dr. Blanton - ENTC 4307 - Phase Lock Loop 2


Phase-Locked Loops

• A phase-locked loop (PLL) uses a feedback control circuit to allow a voltage-controlled oscillator to precisely track the phase of a stable reference oscillator, with the important feature that the output oscillator can be made to run at a multiple of the reference oscillator frequency.


• Phase-locked loops are used • as FM demodulators, • in carrier recovery circuits, and • as frequency synthesizers for modulation

and demodulation. • Phase-locked loops have very good frequency

accuracy and phase noise characteristics, but suffer from the fact that settling times (between changes in frequency) can be long.


• The basic circuit of a phase-locked loop consists of • a reference oscillator, • a phase detector

• produces an output voltage proportional to the difference in phase of the inputs,

• a loop amplifier and filter, • a voltage-controlled

oscillator (VCO), and• operating at the desired

output frequency• a frequency divider.


• In operation, the output of the VCO is divided by N to match the frequency of the reference oscillator.

• The phase detector produces a voltage proportional to the difference in phase of these two signals, and is used to make small corrections in the frequency of the VCO in order to align the phase of the VCO with that of the reference source.

• The output of the phase-locked loop thus has a phase noise characteristic similar to that of the reference source, but operates at a higher frequency.

• If a programmable frequency divider is used, it is possible to synthesize a large number of closely spaced frequencies with a relatively simple circuit. • This makes the phase-locked loop very useful for commercial

wireless applications, especially those involving mu ltiple channels.


• Phase-locked loops can be implemented in either digital or analog form, but we will only discuss analog PLLs because they are the only type capable of operating at RF and microwave frequencies.


• There are several characteristics of phase-locked loops that are important in practice. • The capture range is the range of input frequency

for which the loop can acquire locking.• The lock range is the input frequency range over

which the loop will remain locked; • this is typically larger than the capture range.

• The settling time is the time required for the loop to lock on to a new frequency.


Practical Synthesizer Circuits• The AMPS cellular system requires a local

oscillator in the 800 MHz band to receive one of several hundred voice channels having 30 kHz spacing. • Using a standard phase locked loop would

require a reference source operating at 30 kHz and a VCO operating near 870 MHz, with a programmable divider providing a division ratio of more than 24,000.

• This would be impractical because of the large number of addresses required as well as the high frequency at which the divider would have to operate.


• Instead, a phase-locked loop supplemented with a mixer and frequency multiplier is used


• In this synthesizer the VCO operates at the frequency fo, which ranges from 217.5 to 222.5 MHz.

• The VCO output is frequency multiplied by four to achieve the desired synthesizer output in the range of 870 MHz.

• Part of the VCO output is mixed with a fixed reference crystal oscillator at f1 = 228.02250 MHz.

• The filtered difference frequency of 6 to 11 MHz is low enough to be digitally divided with an inexpensive programmable counter. • The division ratio is selected with a 10-bit address to lie

between 737 < N < 1402, according to the desired channel.


• The output of the divider is compared to a stable 7.5 kHz oscillator, f2 , and the phase error is used to control the VCO. • When the loop is in lock, the output

frequency is fout = 4(f1 f2). • Thus the output can be stepped in

increments of 4 f2 = 30 kHz. • The stability of the output is set by the stability

of the reference sources f1 and f2.


• If it is desired to produce an output frequency of fout = 870.180 MHz. for example, then we solve the equation

870.180 MHz = 4(f1 N f2) = 4[228.02250 N(0.0075)]

• This yields N = 1397. which is the required setting of the programmable divider.


Phase Detectors• A phase detector provides an output voltage

that is dependent on the phase difference between two input signals. • Two input signals of nominally the same

frequency (o), but different phases (1 and 2), are applied to the input ports of a 90 hybrid coupler.


• The output voltages developed across the mixer diodes can be written as

)sin()cos()cos()cos()(

21

211 90

tt

tttv

oo

oo

)sin()cos()cos()cos()(

12

122 90

tt

tttv

oo

oo


• If we assume a square-law response for the mixer diodes, and retain only the quadratic terms, the diode currents can be written as:

• The negative sign of i2 accounts for the reversed diode polarity.

)(sin)sin()cos()(cos

)()(

22

2112

211

2

ttttK

tKvti

oooo

)(sin)sin()cos()(cos

)()(

12

1222

222

2

ttttK

tKvti

oooo


• After combining the diode currents and low-pass filtering, the output voltage can be expressed as

)()sin()()()(

2121

21

dd

o

KKtititv


• This result shows that the output voltage of the phase detector is proportional to the sine of the difference in phase of the two input signals. • If this difference is small, then the sine function

can he approximated by its argument, so that the phase detector output is proportional to the phase difference. • This is referred to as the linearized phase detector

model.


• The constant K, is the phase detector gain factor, and accounts for the diode square-law constants and current-to-voltage conversion. • It has dimensions of volts/radian.


Transfer Function for the Voltage-Controlled Oscillator

• We can assume that the VCO has an output frequency o that is offset from its free-running frequency, c,by an increment :

• where the offset frequency is controlled by the control voltage vc applied to the VCO. • The constant Ko is the VCO gain factor, and has

dimensions of HZ/V.

cocco vK


• We define the phase of the offset frequency of the VCO as

• Writing frequency as the time derivative of phase then gives

tvKtt coo )(

coo vKdt

td )(


• The integral yields the output phase in terms of the control voltage:

• The Laplace transform yields:

t

coo dvKt0

)()(

)()( sVs

Ks co

o


• Assume a reference input voltage given by:

• where i is the phase of the input waveform.

)cos()( ioi ttv


• The output voltage of VCO can be written as

• where o is the phase of the output waveform. • Note that the output frequency is N times the

input (reference) frequency, due to the use of the frequency divider in the loop feedback path.

)cos()( ooo tNtv


• The phase detector output voltage can be expressed in the Laplace transform domain as:

))()(()()()( ssKsVKtv fidddo 21


• Since the divider divides the frequency by N, and phase is the derivative of frequency, the phase will also be divided by N. • So the relation between the feedback phase f

and the output phase, o, is

)()( sN

s of 1


• The control voltage, Vc(s), applied to the VCO is

)()()( sVsHsV dc


• The transfer function is:

Ns

KsV

sHsVs

K

sK

sV

sVs

K

ss

o

d

d

do

fd

d

co

i

o)()(

)()(

)()(

)(

)()(

NsHKKs

sHKK

N

sHsVs

K

KsV

sHsVs

K

ss

do

do

do

d

d

do

i

o)()(

)()()(

)()(

)()(


NsHKKs

sHKKNN

NsHKKs

sHKKss

do

do

do

do

i

o)(

)(

)()(

)()(

)()(

)(

)(

)()(

sKHssNKH

NsHKKs

sHKKNN

ss

do

do

i

o

NKKK do


)()()()( ssKHs

sNKHs io


• The VCO control voltage is then found as

• The loop phase error is:

)()()()( ssKHssHsKsV i

dc

)()(

)( ssKHs

ss i


• Consider a step change in the frequency, so that the input voltage is:

• The input phase function is

• where U(t) is the unit step function.

)cos()cos()( ttttv oioi

)()( ttUti


• The Laplace transform is:

21

ssssi

)(


First-Order Loop• First consider the simplest case of a PLL with no

loop filter. • Then H(s) = 1, and the VCO control voltage for a step

change in frequency, reduces to

• due to partial fraction expansion.

KssK

ssKHssHsKs

sKHssHsKsV dd

id

c

2)(

)()()()()(

KssK

KKss

KsV ddc

11)(


• Since there is a maximum of one pole, the system is a first-order loop.

• This result shows how the VCO control voltage varies in response to a step change in the input frequency. • At t = 0, vc(t) = 0. • The output frequency is = c,the free-running VCO

frequency. • In the limit as t→, the control voltage exponentially converges

to

)()()( tUeKK

KssKKtvsV Ktdd-

cc-

11111 LL

d

dc K

NKKtv

)(


• Then the output voltage of the VCO is, after locking, given by:

• which shows that the output frequency has tracked the input step in frequency, and is multiplied by N.

tNtNtv oooo )(cos)cos()(


• The time required for the output of the PLL to respond to the step change in input frequency is called the acquisition time.



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