696 IEEE ELECTRON DEVICE LETTERS, VOL. 12, NO. 12, DECEMBER 1991

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Technology Limitations for N+ /P' Polycide

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Gate CMOS due to Lateral Dopant Diffusion in Silicide/Poly silicon Layers

Charles L. Chu, Goodwin Chin, Krishna C. Saraswat, Fellow, IEEE, S. Simon Wong, Member, IEEE, and Robert Dutton, Fellow, IEEE

Abstract-The device degradation of dual-polycide-gate N+/P+ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NM0S:PMOS gate area ratios and thermal processing conditions. The simula- tions show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide tech- nologies using low-temperature or short higher temperature fur- nace steps. Simulations show that CoSi, and TiSi,.appear to be better candidates for submicrometer dual-gate applications com- pared to WSi,.

I. INTRODUCTION

OR submicrometer CMOS devices, optimum surface F channel NMOS and PMOS transistors require the use of dual N+/P+ polycide gate material [I]. Recently the lateral diffusion of dopants in various silicides has been reported for the first time and was found to be extremely high [2], [3]. Due to the extremely rapid diffusion of dopants in the silicide layers it is no longer clear that traditional post silicide furnace anneals are possible. This rapid diffusion can cause gate work-function shift as well as the formation of a deple- tion capacitor at the polysilicon gate oxide interface. Hayashida et al. show that it may be necessary to eliminate all furnace anneals above 800°C [4].

To examine the process limitations of using silicides, SUPREM-IV [5] and PISCES [6] simulations are used to study the diffusion of dopants in silicides and their impact on scaled dual-gate CMOS devices. A new version of SUPREM-IV is developed with additional material layers to permit the simulation of silicide layers. The diffusion in the silicide layers is modeled as a concentration and oxidation independent diffusion phenomenon with a single preexponen- tial constant and activation energy. The lateral diffusion values used in the simulations are shown in Fig. 1 [2], [3]. The accuracy of these values is verified by simulating MOS transistor structures used in previous studies [4], [7]. The simulated and measured results (Table I) show good agree- ment.

Manuscript received July 15, 1991; revised October 8, 1991. The authors are with the Center for Integrated Systems, Stanford Univer-

IEEE Log Number 9104896. sity, Stanford, CA 94305.

0741-3106/91$01.00 0 1991 IEEE

CHU et al . : TECHNOLOGY LIMITATIONS FOR N +/P+ POLYCIDE GATE CMOS

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TABLE I MEASURED A N D SIMULATED PMOS AVr DUE TO LATERAL DIFFUSION

OF As FROM A LARGE N + POLYCIDE RESERVOIR TO A P + POLYCIDE GATF PMOS WHICH ARE SPACED A DISTANCE XLo,

Diffusion cond [Ref ] Meas AV,(X, , , ) Sim A V r ( X L , , )

- 110 mV ( 1 2 pm) - 1 1 V ( I O pm)

-400 mV (15 pm) - 100 mV (20.0 pm)

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Fig. 2. Minimum spacing between a MOS transistor and an oppositely doped large reservoir for a maximum A V , of 100 mV .

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apart. These results confirm the findings of Pfiester et al. [7] and Hayashida et al. [4] that the scaling of dual-gate-poly- cide CMOS devices will be impossible if high-temperature post silicide furnace anneals are used. The apparent lack of B diffusion into an As-doped WSi, gate shown by the "+" symbol in Fig. 2 is a result of the extremely high segregation coefficient of B into WSi, /oxide layers that results in a low effective diffusivity [81, 191.

The large spacing requirements shown in Fig. 2 represent worst-case design rules. In most VLSI layouts this type of gate configuration is rarely found, and a more realistic struc- ture is one with similar-sized NMOS and PMOS polycide gate areas. The conclusion that the scaling of dual-gate technologies will be impossible is extrapolated from results with large-area dopant reservoirs, which may not apply to more realistic equally sized devices.

Similar process and device simulations are conducted for a

4:1, and 8: l . Fig. 3 shows a plot of the simulated minimum spacing required between a PMOS and a NMOS transistor with a gate ratio of 2: l for a maximum V , shift of 100 mV. Compared to Fig. 2 for a large dopant reservoir, the mini- mum required spacing is significantly reduced for the more equally sized gates. This large reduction in spacing is due to the limited dopant source supplying the species diffusing into the oppositely doped gate region. As the diffusion proceeds the dopants in the NMOS and PMOS gate areas are depleted, lowering the effective source concentration and reducing the extent of the degradation due to counter doping. The simula- tions indicate that for a WSi, or a CoSi, dual-gate technol- ogy the minimum NMOS-to-PMOS spacings will still be large if any post silicide anneal occurs at or above 900°C. At 800°C the minimum NMOS-to-PMOS spacing is on the order of 2 pm for CoSi, polycide gates annealed for 60 min or less, and for WSi, polycide gates annealed for less than 45 min. The asymptotic-behaviorfor the spacing of the TiSi, polycide gates is due to the lack of any B diffusion from the CMOS structure with PM0S:NMOS gate area ratios of 2:1,

698 IEEE ELECTRON DEVICE LETTERS, VOL. 12, NO. 12, DECEMBER 1991

PMOS gate. Therefore, the MOS degradation is a result of only the As depletion out of the NMOS region and counter- doping of the PMOS gate. Since the As concentration begins to fall off for longer anneals, the minimum separation dis- tance saturates very quickly for longer anneals.

Simulations for PM0S:NMOS gate ratios of 4:l and 8: l show similar spacing requirements. For a gate ratio of 4 : l the minimum required spacings between the NMOS and PMOS are roughly 50% greater than those for the 2: 1 gate ratio, and for the 8:l gate ratio the minimum spacings are similar to those for the large dopant reservoir case shown in Fig. 2.

The minimum gate spacing between PMOS and NMOS gates with a gate area ratio of 2: l is obtained with TiSi, or CoSi, polycide for longer furnace anneals. For TiSi, this is due to lack of B diffusivity in the silicide layer, while for CoSi, this is due to the slower diffusion for B and As than in either WSi, or TiSi,. Simulations indicate that 1 pm and submicrometer gate spacings will be possible at temperatures as high as 1000°C provided anneal times are kept shorter than 30 s. For a 900°C anneal of several minutes, a mini- mum spacing of 1-pm gate is required, while at 800°C, furnace anneals up to 20 min are feasible. These high-tem- perature limitations will require the reexamination of such standard processes as oxide reflow for planarization, and will limit the use of techniques such as diffusion from a doped silicide to form shallow junctions [lo], [ 111.

111. CONCLUSIONS We have examined the technology limitations of using

silicides for scaled MOS devices due to lateral dopant diffu- sion in polycide gates. The simulation results illustrate the problems faced with the continued use of silicides to strap

differently doped polysilicon regions as the distances between the differently doped regions are reduced. Previous experi- mental results indicate that the reduction of the spacing to 1 pm and smaller will be impossible. New simulation results show that micrometer and submicrometer spacing between differently doped polycide regions should be feasible pro- vided that the two regions are of similar size and the post silicide thermal budget is carefully controlled.

REFERENCES [l] G. Hu and R. H. Bruce, “Design tradeoffs between surface and

buried-channel FET’s.” IEEE Trans. Electron Devices, vol. ED-32,

[31

[41

191

1111

no. 3 , p. 584, 1985. C. L. Chu, K. C. Saraswat, and S . S . Wong, “Characterization of lateral dopant diffusion in silicides,” in ZEDM Tech. Dig., 1990, p. 245. C. Chu, “Measurement and modeling lateral dopant diffusion in silicides,” Ph.D. dissertation, Stanford Univ., Stanford, CA, Tech. Rep. ICL91-007, June 1991. H. Hayashida et al., “Dopant redistribution in dual gate W-polycide CMOS and its improvements by RTA,” in Symp. VLSI Technology Dig., 1989, p. 29. M. E. Law, C. S. Rafferty, and R. W. Dutton, “SUPREM-IV users manual,” Stanford Univ., Stanford, CA, Tech. Rep., Dec. 1988. M. R. Pinto, C. S . Rafferty, and R. W. Dutton, “PISCES 11: Poisson and continuity equation solver,” Stanford Univ., Stanford, CA, Tech. Rep., Sept. 1984. J . R. Pfiester et al.. “A TiN strapped polysilicon gate cobalt silicide CMOS process,” in IEDM Tech. Dig., 1990, p. 241. F. C . Shone, S . E. Hansen, D. B. Kao, K. C. Saraswat, and J . D. Plummer, “Modeling dopant redistribution in SiO, /WSi, /Si struc- ture,” in IEDM Tech. Dig., 1986, p. 534. F. C. Shone, “Physics and modeling of dopant redistribution in silicide/silicon shallow junction devices,” Ph.D. dissertation, Stan- ford Univ., Stanford, CA, Dec. 1987. F. C. Shone, K. C. Saraswat, and J . D. Plummer, “Formation of 0.1 gm N f / P and P + / N junctions by doped silicide technology,” in IEDM Tech. Dig., 1985, p. 407. D. L. Kwong et al., “Silicided shallow junction formation by ion implantation of impurity ions into the silicide layers and subsequent drive in,” J . Appl. Phys., vol. 61, no. 11, p. 5084, 1987.