Oxidation

Thin gate oxide ~ 1 nm in MOSFETsTunnel barriers in flash memoryDielectrics in capacitorsElectrical isolation of componentsPassivation layer to protect the circuitsOxide masks for diffusion and implantation

Native oxide ~ 1 nm grows in air in hours but is not good quality

Thermal oxide - grows slowly, best quality

Deposited oxide - grows quicker, less quality

The properties of SiO2 were more important than Si in making Si the dominant semiconductor material.

Institute of Solid State PhysicsTechnische Universität Graz

Dry oxidation

1 hour at 900 C produces 30 nm of thermal oxide.

Used for gate oxide in MOSFETs and tunnel oxide flash memories.

Good layer control. Low defect density at the Si/SiO2 interface.

Si (s) + O2 (g) → SiO2 (s)

Wet oxidation

The water is steam.

1 hour at 900 C produces 130 nm of thermal oxide.

Faster growth than dry oxidation.

Si (s) + 2H2O (g) → SiO2 (s) + 2H2 (g)

http://en.wikipedia.org/wiki/Thermal_oxidation

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CVD oxides

Can be deposited at lower temperature

Rougher surfaces, lower breakdown field, higher etch rate in HF

Deal-Grove oxidation model

2 4( )2

A A Btz t − + +=

00

exp expA A

B B

E EB BB Bk T A A k T

− − = =

Oxide thickness z is first linear then grows like a square root

The constants are thermally activated

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Deal-Grove oxidation model

Wet

Dry

Linear dependence: Limited by the reaction rate of Si and O2 to SiO2

Square root behavior:Limited by oxygen diffusion through the oxide.

http://www.nanolabtechnologies.com/

SiO2 is amorphous

gate oxide

Dit 109–1011/cm2

defects at the interface

1015 atoms/cm2

Post oxidation anneal (N2 then H2) to passivate dangling bonds

Fransila

Oxides are under compressive stress

Typical stress is 300 MPaStress will bow the wafer

densityquartz 2.65 g/cm3

oxide 2.2 g/cm3

Young's modulusquartz 107 GPaoxide 87 GPa

Stoney's formula

2

6 (1 )s s

ff s

E hh

κσν

=−

The stress σf in the film depends on Es Young's modulus in the substratevs Poisson's ratio of the substratehs thickness of the substratehf thickness of the filmκ curvature Only holds for uniform curvature

Local Oxidation of Silicon (LOCOS)

thin pad oxide for stress relief

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Controlled removal of Si

1. Thermal oxidation (good control of thickness)

2. Etch Oxide with HF

Period doubling of pattern

Controlled removal of Si

Fransila

Complementary Metal Oxide Semiconductor (CMOS)

The dominant technology for microprocessors

Low power dissipation through the use of n-type and p-type MOSFETs

Institute of Solid State PhysicsTechnische Universität Graz

CMOS inverter

2dd ddE QV CV= =

Dissipates little power except when it is switching

CMOS inverter

out

p

p+ p+p+n

n+n+n+

Vdd

in

inverter

CMOS inverter

out

p

p+ p+p+n

n+n+n+

Vdd

in

Gate delay

Gate delay is limited by CgateVdd/I.

Ring oscillator

Mask oxide LithographyEtching oxideResist strip and cleaningDopant predeposition

(for instance 1013 cm-2

@ 40keV)Drive-in

(500 mi. 1000 C)Oxide etching

Well formation

np

Pad oxide (thermal)Mask nitride (LPCVD)LithographyEtching nitride/oxide/siliconResist strip and cleaningLiner oxide (thermal) CVD oxide depositionCMP planarization of the oxideNitride etchingOxide etching

Shallow Trench Isolation (STI)

http://de.wikipedia.org/wiki/Grabenisolation

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Shallow Trench Isolation (STI)

http://de.wikipedia.org/wiki/Grabenisolation

p-Si 100 wafer

Self-aligned fabrication

p-Si

SiO2 gate oxide

Dry oxidation

p-Si

SiO2

polysilicon

TiN (CVD)30–70 μΩ·cm Conductive diffusion barrier

photoresist

CVD: SiH4 @ 580 to 650 °C

p-Si

SiO2

polysilicongate

TiN

Implant

Expose resistDevelopEtch poly and TiNStrip resistImplant source and drain

p-Si

n+ n+

polysilicongate

Self-aligned fabrication

PredepositionDrive-in

p-Si

n+ n+

Spacer

polysilicongate

SiNx

PECVD SiNx

p-Si

n+ n+

Spacer

polysilicongate

SiNx

Etch back to leave only sidewalls

p-Si

polysilicongate

Implant

n+ n+

p-Si

polysilicongate

n+ n+

TiSi2 (metal)

Salicide (Self-aligned silicide)

Transition metal (Ti, Co,W) is deposited (CVD). During a high temperature step is reacts to a silicide (TiSi2). Not silicide is formed on nitride or oxide.

CMOS

Fransila

Gate dielectric

Thinner than 1 nm:electrons tunnel

Large dielectric constant desirableεr(SiO2) ~ 4

εr(Si3N4) ~ 7

The heat dissipation problem

Microprocessors are hot ~ 100 CHotter operation will cause dopants to diffuse

When more transistors are put on a chip they must dissipate less power.

Power per transistor decreases like L2.

Constant E-field Scaling

L ~ 45 tox

1975 - 1990: "Days of happy scaling"

Gate length L, transistor width Z, oxide thickness tox are scaled down.

Vds, Vgs, and VT are reduced to keep the electric field constant.

Power density remains constant.

Constant E-field scaling

( )oxDm n G T

G ox

dI Zg V VdV L t

εµ= = −

( )2

2ox

sat n G Tox

ZI V VL t

εµ= −

Power per transistor decreases like L2. Power per unit area remains constant. Maximum operating frequency remains constant.

, , , ox ox th thL sL Z sZ t st V sV⇒ ⇒ ⇒ ⇒

sat satI sI⇒

Transconductance stays the same.

Isat gets smaller

www.iwailab.ep.titech.ac.jp

Equivalent oxide thickness (EOT)

2

2

Si0high-k Si0EOT t t

εε

= +

Scaling can continue using oxides too thick to tunnel if they have a higher dielectric constant.

http://nano.boisestate.edu/research-areas/gate-oxide-studies/

High-k dielectrics

Subthreshold current

For VG <VT the transistor should switch off but there is a diffusion current. The current is not really off until ~ 0.5 V below the threshold voltage.

( )exp G TD

B

e V VI

k T−

∝

Subthreshold swing: 70-100 mV/decade

Weak inversion

Short channel effects

SOI: silicon on insulator