Techniques for Low Voltage High Output

Impedance Current Mirror Girish Kumar Ajmera

CARE, Indian Institute of Technology, Delhi,

New Delhi – 110016 India.

girish.kumar.ajmera@gmail.com

Abstract – In this paper various methods for

designing a low voltage high output

impedance current mirror are proposed and

compared. This Paper presents three such

schemes Bulk driven, self cascode, and, sub

threshold [1-2].

Keywords – Cascode, Current mirror, Analog

Integrated Circuits, MOSFET.

I. INTRODUCTION

Current Mirror is an essential part of any CMOS

analog integrated circuit. It is used widely in

analog integrated circuits for biasing, current

amplifications, active loading and level shifting

etc. To supply a regulated current to load which

is the basic requirement of any analog integrated

circuit, there are many ways and current mirror

is one of them. Current Mirror can be defined as

a black box whose output current is linearly

proportional to input current and independent of

output voltage.

As the portability of electronic gadgets is

gaining popularity need of low voltage and low

power devices is increasing [1-3]. In various

applications low voltage signal analysis is

needed such as medical instrumentation. In

conventional 5 V MOSFET circuits the high

gain and high output impedance can be simply

achieved by the cascode structure of MOSFETs

but this cannot be done in low voltage circuits as

cascode structure of MOSFETs increases the

minimum voltage substantially, required for

proper operation of circuit. Another way is to do

cascading but that induces stability issues in the

circuit because at every stage there will be a pole

in the circuit, they may degrade the overall

circuit performance at the high frequency [4].

The one most basic approach to achieve low

voltage design is reduction in threshold voltage

but that will reduce the noise margin and results

in poor SNR [2]. Compactness of analog

integrated circuits has increased substantially in

the last few years but the corresponding scaling

in voltage is still in research. Minimum voltage

needed is limited by the sum of absolute value of

threshold voltages of different MOS in the

circuit. The research in the area of battery less

system can also boost up if the low voltage

analog circuit design is achievable to the level

that voltage level provided by solar cell, RF

power and so forth, is adequate. High impedance

is needed to mitigate the loading effect so that

optimum amplification can be done.

Another way to operate MOSFETs for low

voltage application is to operate the MOSFETs

itself in some other regions instead of strong

inversion region so that the fundamental

limitation on the input voltage is relaxed. For

MOSFETs operating in weak inversion region

the trans-conductance efficiency (gm/ID) is

maximum and the quiescent current magnitude

is much smaller as compared to MOSFETs

operating in strong inversion region [5]. So

operation of MOSFETs weak inversion region is

a potential area to research so that low voltage

circuits can be designed.

The basic desirable properties for a current

mirror circuit are I) As much as possible high

output impedance. II) As much as possible

Output voltage swing, which is limited by the

saturation voltage of the MOSFETs used in

circuit. III) Voltage needed at the input to

operate the current mirror, which is limited by

the voltage required to bias the MOSFETs or to

start the operation of MOSFET.

In this paper the main focus is kept on to design

current mirror circuit which works well at low

voltages and consume low power. Since an ideal

current source has infinite impedance so in the

current mirror it is desired to have as high output

impedance as possible to get the constant current

at the output. When implementing a current

mirror in a design it is desired to have high

output impedance, low operation voltage. Brief

introduction about various low voltage

techniques such as sub threshold, bulk driven,

and, self cascode will be discussed [1-2]. The

main issues using these techniques were that

many popular circuits which are frequently used

in 5V analog integrated circuits have lost their

important properties and performance in low

voltage environment. So designers using these

low voltage techniques have to struggle a lot to

devise the alternative circuit structures. Another

issue in low voltage circuits is the poor dynamic

range as the swing as well as voltage needed for

operation of circuit both decreases substantially

but the noise level is intact. This causes poor

dynamic range. These techniques are still in the

evolution phase and many new improvements

are under research to overcome these limitations.

A simple low voltage and high impedance

current mirror using these schemes will be

discussed. Each one of them have certain

advantages and disadvantages.

II. SIMPLE CURRENT MIRROR

The following diagram shows a simple current

mirror circuit [5].

Figure 1: A simple Current Mirror [5]

The basic current mirror can be implemented

using MOSFETs as shown in the figure 1. Here

the MOSFET 1 is operating in saturation region

so that a constant current flows through it. The

gate to drain connection of M1 ensures that it

always remains in saturation region. The Gates

of both the MOS are connected and drain

voltage of M2 is maintained such that M2 will

also remain in the saturation region so that a

constant current flows through it. As both the

MOS are fabricated in the same process and

their gate to source voltage are same so Iout is a

scaled version of Iref.

( )

( )

( )

( )

If channel length modulation effect is not taken

into account (λ = 0) then from equation (1) and

(2) it can be easily shown that

But this simple current mirror have the

limitations as output impedance is not high, a

basic requirement is for the current source is.

Also, on taking into account the channel length

modulation effect output current may not be

proportional to input current. As the fabrication

process is improving and compactness in circuits

is increasing the trend is towards decreasing the

channel length. But in short channel length

devices the channel Length modulation

parameter becomes more prominent that

decreases the output impedance.

To get over these limitations cascode structure

can be used as shown in figure 2. On using the

cascode structure the output impedance can be

increased from ro (in simple current mirror) to

approximately gmro2. Since in order to ensure

current mirroring function the MOSFETs should

operate in the saturation region, so at the drain

end of M4 the voltage has to be at least equal to

twice of saturation voltage plus threshold

voltage. The additional term of threshold voltage

requires a higher voltage to be present at the

drain terminal of M4. Also, the effect of channel

length modulation is still there which makes the

current mirroring poor as current increases with

VDS.

Figure 2: Cascode Current Mirror [5]

This requirement of additional voltage makes

this conventional current mirror less qualified

for low voltage applications. To get over these

limitations various improvisation has been done

in the cascode current mirror configuration. In

literature various methods have been proposed

to increase the output impedance that leads to

Wilson current mirror, modified Wilson current

mirror, cascode current mirror, regulated

cascode current mirror, folded cascode current

mirror and so on [5]. These all techniques are

effective to increase the output impedance and

do increase the output swing up to some extent

but does not provide any improvement over the

minimum input voltage required to successfully

operate the circuit. In these schemes there is a

tradeoff between operational voltage and output

impedance.

III. BULK DRIVEN MOSFETs

In a standard MOSFET operation the drain

current is controlled by the applied gate voltage,

so they are called gate driven. In this technique

of bulk driven MOSFETs the drain current is

modulated by the bulk voltage instead of gate

voltage. In a standard Gate driven MOS due to

modulation through gate voltage it is necessary

to have the magnitude of input voltage which is

to be applied at gate to be more than the

magnitude of threshold voltage so that inversion

of layer under gate is ensured for flow of charge

carriers through channel. This limitation on

minimum magnitude of input voltage is not

required in bulk driven technique. Hence low

voltage input signal can be used to drive the

circuit. For a typical Bulk driven MOSFET only

0.1 V is sufficient at input and it will provide the

same drain to source voltage as in case of

standard gate driven operation.

Due to fixed gate bias voltage there exist a

constant width channel and the bulk terminal

controls the channel width according to input

voltage, or we can say that it is acting as virtual

gate terminal but there is no limitation of

threshold voltage. For bulk driven operation it is

necessary that MOSFET is fabricated in a

separate well. [6-8].

Figure 3 : Cross section of P-MOS in n-well

Figure 3 shows a cross section of the p type

MOSFET fabricated in n-well. A sufficient

voltage needs to be applied at the gate terminal

to form the channel under gate area. In gate

driven MOS thickness of the channel is

controlled by setting up the appropriate level of

gate voltage. In bulk driven mode of operation

thickness of the channel is controlled by the bulk

potential. On varying the bulk to source

potential the bias voltage between the bulk (n-

type) and source (p-type) varies that modulate

the depletion region width of source-bulk p-n

junction. By modulation of depletion region

width, the channel width can also be modulated.

When bulk is at higher potential then source the

source bulk junction is reverse biased. On

making this potential difference VBS small the

depletion region width starts decreasing that will

decrease the drain current. The bulk to source

junction is kept under weakly forward biased

region very small amount of current flows

through this junction and almost the whole

current flows through channel. Typical current

flow in the bulk source junction is in the range

of pA for |VBS| ≤ 0.3 Volt and it is of no

significance compared to drain current.

Thus, in bulk driven operation MOS is kept in

strong inversion and source bulk junction is

weakly forward biased. Then by varying source

bulk potential drain current is controlled. The

drain current in N type MOSFET is given by

(

) ( )

(

)

VT is the threshold voltage which varies with

source to bulk potential as follows

(√ √ )

Since in bulk driven mode of operation gate to

source voltage is fixed and bulk to source

potential is varied so the equation (4) can be re

written as, it gives the drain current expression

in the saturation mode in bulk driven mode of

operation.

(

) ( √ √ )

From the equation (6) the small signal trans-

conductance is given by

√

Where gm is the small signal trans-conductance

for standard gate driven MOSFET. For the N

type MOSFET source is of n type and bulk is of

p type. In Bulk driven mode of operation the

bulk source junction is kept in weakly forward

bias region so VBS is Positive. This causes the

denominator in the equation (7) to decrease

thereby increasing the trans-conductance (gmb).

Figure 4 Simple Bulk Driven Current Mirror [6]

Figure 8 shows a current mirror circuit using

MOSFETs operated in the bulk driven mode of

operation. The gates of both the MOSFETs are

connected to VDD to ensure the formation of

inversion layer under gate area. Gate to source

voltage for both the MOSFETs is same. Bulk

and drain of M1 are connected so VDS1 and VBS1

are same, this ensures that M1 is always

operated in the linear region. The bulk of both

M1 and M2 are connected together and so the

source, hence, VBS1 and VBS2 are also same. The

drain voltage of M2 is maintained such that it

remains in the saturation region. For M1

operating in the linear region, if channel length

modulation effect is not considered, the Iin

current is given by

(

) (( ) )

From this equation

( )

( )

Gate to source voltage of both M1 and M2 are

same and M2 is operating in saturation region so

current through M2 is given by

(

)(

( )

)

The input impedance of bulk driven MOSFET is

given by [6-8].

√

IV. SELF CASCODE MOSFETs

In a conventional current mirror structure to

maintain both the MOSFETs in saturation region

the output compliance voltage required is given

by

√

So in order to maintain the MOS in saturation

the compliance voltage required has an

additional term Vth, which is a significant term

in magnitude. To increase the output impedance

cascode structures are used, but using a cascode

structure further degrades the compliance

voltage. So in low voltage applications it is

difficult to use conventional cascode structures.

Also as the scaling in MOSFETs is increasing,

the output impedance also decreasing for short

channel MOSFETs. Since short channel

MOSFETs cannot provide high output

impedance, and so cannot provide high gain

structures. Cascode structures are used to

overcome these limitations but they reduce the

available output swing as well as requires more

power.

Figure 5 cascode MOS structure [6]

In a conventional Cascode structure as shown in

figure 5 two MOSFETs are operated in the

saturation region. The fundamental limitation is

to have the magnitude of gate to source voltage

to be more than the magnitude of threshold

voltage. This limitation ensures that MOSFETs

are biased in strong inversion region. If an

another structure is used in which the devices

are operated in weak inversion region then this

fundamental limitation of having magnitude of

gate to source voltage more than magnitude of

threshold voltage can be relaxed as in weak

inversion gate to source voltage is kept lower

than threshold voltage.

In the figure 6 two MOSFETs are connected in

cascode fashion with their gate connected to

same potential. If these two MOSFETs are in

strong inversion region then at a time only one

of the MOS will be in saturation region while

the other one will be in linear region. This does

not provide any advantage in the output

impedance as it remain same as in case of a

single MOSFET. Instead of biasing both the

MOSFET in the strong inversion region if M2 is

biased in weak inversion region, this structure

itself provides high output impedance.

Figure 6 Self Cascode Structure [9]

For MOSFETs biased in weak inversion region

the drain to source voltage required to keep it in

saturation is only larger than Thermal voltage

(VT), which is 26 mV at room temp. This

structure is very much similar to conventional

cascode structure but here M2 does not require

an additional biasing voltage. Gates of M2 and

M1 are connected to one single voltage. The

circuit is self cascode structure when M2 is in

weak inversion region and M1 is in weak or

moderate inversion region.

When both M1 and M2 are biased in saturation

the circuit operates similar to the conventional

Cascode structure and provides a scaling factor

of gmro to output impedance. To ensure that both

the MOSFETs are operating in the saturation

region proper scaling is expected. For M1 it is

biased in the sub threshold region and to keep

M2 in the weak inversion region the gate to

source voltage drop across M2 should be as

small as possible, this is done by enhancing the

aspect ratio of M2 by a factor m. This factor m

is the main design parameter in self cascode

MOSFET structures.

Figure 6 also shows the equivalent N type

MOSFET for self cascode N-type MOSFET

structure. The effective trans-conductance of the

structure is given by

Equivalent MOSFET will work in saturation

region when M1 is operating in linear region and

M2 is operating in the saturation region. Current

through M1 and M2 is given by

(

) ( )

(

) ( )

Since Both MOSFETs are connected in cascode

fashion so I1 and I2 are same. On comparing

equation (15) and (16):

(

)

Where

and

The equation () can be approximated as

(

)

Which is equivalent to a single MOSFET current

equation operating in saturation region. Also,

M1 is always operated in the linear region so the

drain to source voltage drop across M1 is small.

The length of the equivalent MOSFET increases

that gives a long channel MOSFET from the

composite of two short channel MOSFETs and

this equivalent long channel helps in increasing

the output impedance. Thus Self cascode

structures provides high output impedance

without lowering the output voltage swing in

comparison to typical cascode structures. [9-11]

Figure 7 shows a simple current mirror using

self cascode MOSFET which is operable at low

voltage and there is no need of extra burden in

the fabrication. The circuit works in a similar

fashion to simple current mirror as the input

current is replicated as the load current. The pair

M2 and M3 is connected in self cascode fashion

and thus provide high output impedance and

high output swing.

Figure 7: Self Cascode Current Mirror [9]

The gates of M2 and M3 which are connected

together are connected to supply voltage VDD.

The aspect ratio of M2 is similar to M1 whereas

aspect ratio of M3 is m time aspect ratio of M1

and M2. Gate and drain of M1 are connected to

ensure that it is always in saturation mode. As

the gate and drain of M1 are connected so

voltage at the drain of M1 will be Vt1 + Von1 and

the same voltage is applied to gate of M3. In

order to keep the composite self cascode

structure in the saturation region the minimum

voltage required at the drain of M3 will be Vt1 +

Von1 -Vt3. Since aspect ratio of M3 is high

compared to M1 and M2, or in other way

channel length of M3 is smaller than channel

length of M1 and M2. The smaller length of M3

lowers the Von voltage required to keep the

MOSFET in saturation that in turn lowers the

saturation voltage. Thus the available swing at

the output increases. So here we are able to get

better output swing at lower bias voltage without

any compromise over output impedance. Further

improvements over the output impedance can be

made by using the self cascode structure in

improvised current mirror circuits as discussed

in section I. Thus this technique provides

substantial improvements in current mirror to be

used for low voltage and low power

applications.

V.SUB THRESHOLD CIRCUIT

In sub-threshold region which is also known as

weak inversion region the gate to source bias

voltage is below threshold voltage. This region

of operation has become important as the

magnitude if input voltage required to operate

MOS in this region is only few tenths of volt. In

conventional operation Of MOSFET where gate

to source voltage is always kept above threshold

voltage the drain to source current is always a

strong function of gate to source bias voltage.

Similarly in case of sub threshold region of

operation where gate to source voltage is kept

below threshold voltage the drain to source

current varies exponentially with the gate to

source bias voltage. In digital circuit it may be

assumed the no current flows in this region but

in case of analog circuits this region is an

efficient operating region because in this region

also there is a finite current flowing in the

channel even of very small magnitude which is

given by

(

) (

)

(

)

Where parameters K’ (µnCox), W, L, n, K, T, q,

VTN are trans-conductance parameter, channel

width, channel length, sub-threshold factor,

Boltzmann constant, temperature, electronic

charge, and, threshold voltage of NMOSFET

respectively.[2] The trans-conductance

efficiency (gm/ID) is high in this region as

compared to in strong inversion that will help in

power consumption. The saturation voltage in

this region of operation is also low that helps in

providing additional voltage swing at the

output.[2]

A typical current mirror circuit can use this

technique with inclusion of the fact that all the

MOSFETs are operating in the sub threshold

region. This relaxes the limit on input voltage

magnitude as well as on the output swing. The

input compliance in the circuit can be further

improved by using various current mirror circuit

improvisation techniques such as level

Shifter.[6]

There are also limitations on the MOSFETs

operating in the sub threshold region in the sense

that unity current gain cutoff frequency (fT) is

not good. This causes limitation on MOSFETs

to be operated in the high frequency circuits. But

this limitation can be mitigated as with the

current technology standards and fabrication

improvisations modern CMOS devices have

achieved values of fT up to 100 GHz which is a

range suitable enough for most of the

applications.[12]

VI. CONCLUSION

Three promising schemes for low voltage

application were discussed. Each one of them

certain advantages and disadvantages. Due to

Depletion Mode operation in Bulk Driven Mode,

larger range for input voltage is there but that

comes at an additional cost of extra fabrication

processing steps for depletion MOSFET. Sub

threshold Scheme provide better trans-

conductance efficiency which is not available in

bulk driven scheme. Transitional frequency

issues are there in the sub threshold scheme

which is not issue in Self cascode approach.

Depending on the particular type of application

designer may incorporate any scheme or a

combination of these schemes. A typical

approach is followed for low voltage circuit is

that the whole design in decomposed in smaller

sub systems and each sub systems is designed

using any of the low voltage scheme. Various

modifications may be made to the theoretical

explanation of operation of these schemes. As

the low voltage applications are increasing the

designers are also working in towards better

implementation of these schemes in the practical

circuits.

VII. REFERNECES

1. Shouli YAN and Edgar SANCHEZ-

SINENCIO. “Low Voltage Analog Circuit

Design Techniques: A Tutorial”, IEICE

Trans. Analog Integrated Circuits and

Systems, Vol. E00-A, No.2 February 2000.

2. S. S. Rajput and S. S. Jamuar, “Design

Techniques For Low Voltage Analog Circuit

Structures”,NSM-2001/IEEE, Malaysia,

Nov. 2000

3. S.S. Jamuar and S.S. Rajput, “Low-voltage

Current-mode Anlog Circuit structures and

their applications”.

4. E. Sánchez-Sinencio and A. G. Andreou,

Ed. Low-Voltage/Low-Power Integrated

Circuits and Systems, IEEE Press, 1999.

5. Behzad Razavi, Design of Analog CMOS

integrated Circuits: Tata McGraw Hill

Edition, 2002.

6. P. E. Allen, B. J. Blalock, and G, A. Rincon,

"A 1 V CMOS Op Amp Using Bulk-Driven

MOSFETs," Proc. ISSCC, 1995

7. Naresh Lakkamraju, Ashis Kumar Mal. “A

low voltage High output impedance Bulk

Driven Regulated Cascode Current Mirror”,

978-1-4244-8679-3/11/$26.00 ©2011 IEEE

8. Li Yani, Yang Yintang, Zhu Zhangming, ”

A Novel Low-voltage Low-power Bulk

Driven Cascade Current Mirror” , 978-1-

4244-6542-2/$26.00 © 2010 IEEE

9. M.T.Sanz, S.Celma, B.Calvo and D.

Flandre:’ Self-cascode SOI versus graded-

channel SOI MOS transistors’, IEE Proc.-

Circuits Devices Syst., Vol. 153, No. 5,

October 2006

10. Ichiro Fujimori, Sagamihara Japan, “Low

Voltage Self Cascode Current Mirror ” ,

United States Patent No. 5,966,005

11. Bedabrata Pain, Robert C. Schober, and Eric

R. Fossum. “A Self-Cascoding CMOS

Circuit for Low-Power Applications”.

12. Syed Kamrul Islam and Mohammad Rafiqul

Haider.,sensors and Low power Signal

Processing, ISBN-13: 978-0387793917