Technical Report

DIGITAL SIGNAL PROCESSOR BASED CONTROL OF PERMANENT

MAGNET MACHINE USING TMS320F240

Geeta Athalye

Ali Keyhani

The Ohio State University

Mechatronic Systems Laboratory

Electrical Engineering Department

Columbus Ohio 43210

Keyhani.1@osu.edu

Tel: 614-292-4430

Fax: 614-292-7596

May 2000

ii

ABSTRACT

This report presents an implementation of Field Oriented Control (FOC) of

permanent magnet machine on a DSP (Digital Signal Processor) based system

manufactured by Texas Instruments. The processor used is the 16-bit fixed point

TMS320F240. The system integrates into a single board the computational power of a

TMS320F240 DSP with extra peripherals needed in vector control application, and

therefore requires minimal hardware development. The control algorithm implemented is

the discrete time sliding mode control. Simulation and Experimental results are

presented. The paper also discusses a technique for the position sensorless control of a

brushless permanent magnet machine.( 119 papes)

iii

ACKNOWLEDGMENT

This work has been supported by Delphi Automotive Systems, National Science

Foundation, Ford Motor Company, TRW Controls, General Electric and American

Electric Power, through the Mechatronics Program at the Ohio State University. I would

like to thank the Department of Electrical Engineering for all the educational and

technical support.

iv

TABLE OF CONTENTS

Page ABSTRACT........................................................................................................................ ii ACKNOWLEDGMENT.................................................................................................... iii LIST OF TABLES ............................................................................................................vii LIST OF FIGURES..........................................................................................................viii CHAPTERS: 1. INTRODUCTION......................................................................................................... 11

1.1 Motivations ............................................................................................................. 11 1.2 Objectives ............................................................................................................... 12 1.3 Literature Review ................................................................................................... 13

2. FUNDAMENTALS OF BRUSHLESS PERMANENT MAGNET MOTOR CONTROL........................................................................................................................ 16

2.1 Modeling of 3-phases Brushless DC Machine ....................................................... 16 2.2 Control of a DC Machine ....................................................................................... 22 2.3 Principles of Field Oriented Control....................................................................... 25 2.4 Fundamentals of Sliding Mode Control: ................................................................ 27

2.4.1. Concept of Discrete time Sliding Mode Control......................................... 28 2.4.1.a. Definition............................................................................................ 28 2.4.1.b. Stability Criterion............................................................................... 29 2.4.1.c. Proof of Convergence......................................................................... 31

3. CLOSED LOOP CONTROL OF PERMANENT MAGNET BRUSHLESS DC MOTOR WITH SPEED SENSOR ................................................................................... 32

3.1 Speed Regulation .................................................................................................... 32 3.2 Current Regulation.................................................................................................. 33 3.3 Description of the power converter ........................................................................ 38 3.4 Theory of SV PWM Technique .............................................................................. 39 3.5 Simulation Studies .................................................................................................. 44

v

4. OVERVIEW OF THE TMS320F240 DSP................................................................... 49 4.1 DSP Architecture .................................................................................................... 49 4.2 Memory................................................................................................................... 51

4.2.1 Dual-access RAM (DARAM)...................................................................... 51 4.2.2 Flash EEPROM............................................................................................ 51

4.3 CPU (Central Processing Unit)............................................................................... 55 4.3.1 Input Scaling Shifter..................................................................................... 56 4.3.2 Multiplier...................................................................................................... 56 4.3.3 Central Arithmetic Logic Unit (CALU) ....................................................... 56 4.3.4 Auxiliary Register Arithmetic Unit (ARAU)............................................... 57

4.4 Peripherals .............................................................................................................. 59 a. External Memory Interface................................................................................ 59 b. Event-Manager (EV) Module............................................................................ 60

1. General-purpose (GP) Timers: ................................................................... 60 2. Full Compare Units: ................................................................................... 63 3. Simple Compare Units: .............................................................................. 63 4. Compare/ PWM Waveform Generation:.................................................... 63 5. Capture Unit: .............................................................................................. 64 6. Quadrature-Encoder Pulse (QEP) Circuit: ................................................. 64

c. Dual Analog-to-Digital Converter (ADC)......................................................... 64 d. Serial Peripheral Interface (SPI) Module .......................................................... 66 e. Serial Communications Interface (SCI) Module ............................................... 67 f. Watchdog timer (WD) ....................................................................................... 68

4.5 General purpose I/O ports....................................................................................... 69 4.6 TMS320F240 Instruction Set.................................................................................. 70

4.6.1 Addressing Modes........................................................................................ 71 Direct Addressing:........................................................................................... 71 Indirect Addressing ......................................................................................... 71 Immediate Addressing..................................................................................... 72 Register Addressing ........................................................................................ 72

4.7 Fixed Point Arithmetic ........................................................................................... 72 4.7.1 Fixed Point Representation .......................................................................... 72 4.7.2 Arithmetic operations................................................................................... 74

Addition........................................................................................................... 74 Multiplication.................................................................................................. 75

5. EXPERIMENTAL SETUP ........................................................................................... 76

5.1 DSP System Environment ...................................................................................... 76 5.2 Experimental setup for the Brushless Permanent Magnet Motor Drive ................. 78

5.2.1. Power Converter.......................................................................................... 79 5.2.2. PWM Signal Interface ................................................................................. 80 5.2.3. Analog Signals Interface ............................................................................. 80

vi

6. IMPLEMENTATION OF THE FOC CONTROL........................................................ 82 WITH SPEED SENSOR................................................................................................... 82

6.1 Permanent Magnet Brushless Machine and Its Parameters. ................................... 82 6.2 Control Program Flowchart .................................................................................... 82

6.2.1 Initialization Module Description ................................................................ 86 6.2.2 Interrupt Module Description....................................................................... 86

The INIT Mode................................................................................................ 86 The RUN Mode............................................................................................... 88 Current Sensing and scaling............................................................................ 88 Determination of rotor position and speed...................................................... 90 Transformations Clarke, Park and Inverse Park........................................... 92 Implementation of the DTSM Algorithm........................................................ 93 Implementation of the SPWM Algorithm....................................................... 94

6.3 Experimental Results .............................................................................................. 97 7. SENSORLESS CONTROL OF PERMANENT MAGNET BRUSHLESS DC MOTOR101

7.1 Control of Brushless DC Motor without Position Sensors................................... 101 7.2 Sensorless Control Algorithm............................................................................... 102

7.2.1 Motor Model .............................................................................................. 104 7.2.2 Transformation from γ-δ axes to the three phase uvw axes. ...................... 106 7.2.3 Motor Equations in γ-δ Reference Frame................................................... 107 7.2.4 Estimation of Rotor Speed ......................................................................... 109 7.2.5 Flowchart for Sensorless Control Algorithm ............................................. 111 7.2.5 Simulation Study........................................................................................ 112

8. CONCLUSIONS AND FUTURE WORK.................................................................. 113

8.1 Conclusions........................................................................................................... 113 8.2 Future Work.......................................................................................................... 114

BIBLIOGRAPHY ........................................................................................................... 116 APPENDIX 1169

vii

LIST OF TABLES

Table Page

3.1 Switching patterns for all six sectors......................................................................... 42 3.2 Switching command for all six transistors. ............................................................... 43 4.1 Global Data Memory Map for TMS320F240 ........................................................... 54 6.1 Stator Voltages in βα − for all switching combinations.......................................... 94 6.2 Sector time duration .................................................................................................. 96

viii

LIST OF FIGURES

Figure Page

2.1 Two pole Three Phase PM machine.......................................................................... 17 2.2 Time domain block diagram of a brushless DC machine ......................................... 22 2.3 Separately excited dc machine .................................................................................. 22 2.4 DC motor speed control system with current source input ....................................... 24 2.5 DC motor speed control system with 2 PID nested loop........................................... 25 3.1 DTSM Current Controller for Permanent Magnet Motor ......................................... 38 3.2 Three-phase bridge inverter....................................................................................... 38 3.3 Switching States Corresponding to the 8 possible Switching States of the Inverter. 39 3.4 Output Voltage Space Vectors Corresponding to the 8 possible Switching States of

the Inverter................................................................................................................. 40 3.5 Space Vector Representation of the Switching times required to produce vector Vref41 3.6 Optimum pulse pattern of space vector PWM for sector I........................................ 43 3.7 Simulink block diagram for computer simulation studies ........................................ 44 3.8 Simulink Block diagram for Motor Model ............................................................... 45 3.9 Setup for Step Response Test.................................................................................... 46 3.10 DTSM Controller Simulink Block Diagram ........................................................... 47 3.11 Simulation results for Speed ................................................................................... 47

ix

3.12 Simulation results for Iqs.......................................................................................... 48 3.13 Simulation results for Vab........................................................................................ 48 4.1 TMS320F240 Block Diagram................................................................................... 50 4. 2 Program Memory Map of TMS320F240 ................................................................. 52 4.3 Local Data Memory map for TMS320F240.............................................................. 53 4.4 I/O Memory Map for the TMS320F240.................................................................... 54 4.5 Block Diagram of the TMS320F240 Central Processing Unit (CPU) ...................... 55 4.6 Block Diagram of the ARAU for the TMS320F240................................................. 58 4.7 Block Diagram of the Event Module for the TMS320F240 ..................................... 62 4. 8 Analog to Digital Converter Module Block Diagram .............................................. 65 4.9 Shared Pin Configuration .......................................................................................... 70 5.1 Block Diagram of the TMS320F240 Evaluation Board............................................ 78 5.2 DSP System Setup..................................................................................................... 79 5.3 PWM Interface .......................................................................................................... 80 5.4 Analog Interface ........................................................................................................ 81 6.1 Block diagram for implemented control system ....................................................... 83 6.2 Flowchart for "Initialization Module" ....................................................................... 84 6.3 Flowchart for "Interrupt Module".............................................................................. 85 6.4 Rotor magnetic stall .................................................................................................. 87 6.5 Current Sensing Scale Translation ............................................................................ 89 6.6 Representation of Current Scaling Factor ................................................................. 90 6.7 Mechanical Speed Scale............................................................................................ 92

x

6.8 Space Vector Representation of Voltages ................................................................. 95 6.9 Rotor Speed ............................................................................................................... 98 6.10 Experimental Results for Rotor Speed before and after filtering............................ 98 6.11 q-axis current........................................................................................................... 99 6.12 Line to Line voltage............................................................................................... 100 7.1 Analytical Model of Brushless DC motor ............................................................... 102 7.2 Flowchart for the sensorless control algorithm ....................................................... 111 7.3 Comparison of actual rotor speed with estimated rotor speed. ............................... 112

11

CHAPTER 1

INTRODUCTION

1.1 Motivations

The permanent magnet brushless dc motors are becoming very popular as small

horsepower control motors. These motors cater to a wide range of applications ranging

from appliances (washers, blowers, compressors), HVAC (heating, ventilation and air

conditioning), industrial servo drives (motion control, robotics) to automotive control

(power steering, anti-lock brakes). Therefore, a considerable amount of research is being

done in the field of permanent magnet motor control.

Control of brushless permanent magnet (PM) machines using the vector control

techniques is becoming more popular. Due to the wide availability of high-speed digital

signal processors (DSP), the need for extensive calculations no longer poses a hurdle in

the Field Oriented Control (FOC) implementation. Now-a-days, digital signal processors

with instruction cycles in the range of 50ns are common. In order to implement FOC

control of a permanent magnet machine, certain interface peripherals must be specifically

built into the DSP system. These peripherals include analog to digital converters for

12

feedback signal acquisition, a set of timers for PWM generation, a speed encoder

interface, and digital to analog converters for tracing of signals. Previously, the time and

effort in FOC implementation was greatly increased because all the peripherals had to be

compiled. Therefore, a single board that would integrate the DSP with all the above-

mentioned peripherals is highly desirable

In order to implement the vector control of PM machine the shaft speed signal is

required to perform a closed-loop control of the motor speed or position. Speed

transducers such as shaft-mounted incremental encoders or resolvers are commonly used

for this purpose. These however are prone to wear and tear, have temperature limitations

and consume power, which reduces the efficiency of the drive. In addition, the speed

sensors have associated with them the high cost that goes with mounting arrangements

and maintenance. This has led researchers to seek ways of implementing vector control

without speed sensors or "sensorless control".

1.2 Objectives

The objective of this thesis is to design and implement a DSP based an

experimental setup for the field-oriented control of a brushless DC permanent magnet

motor. The DSP system is based on the TMS320F240 16-bit fixed point DSP offered by

Texas Instruments.

A sensorless control technique for the control of PM machine has also been

discussed.

13

1.3 Literature Review

The concept of FOC or vector control was first introduced by Blasche in 1972 [1,

2, 12]. However, due to the computational complexity, this control did not gain

popularity immediately. In recent times, due to the progress in semiconductor

technology, the implementation of vector control in permanent magnet machine drives is

becoming more common. Considerable amount of research is being done in

implementation of digital control for vector control drives as discussed in [21, 22]. With

the introduction of digital signal processors (DSP), the DSP controller based

implementation of permanent magnet motor drives has received a lot of popularity and

considerable amount of literature has been published on this topic. [3] gives a detailed

description of the DSP controller implementation of FOC of a Permanent Magnet

Synchronous Machine using PI control. In [20] several different implementations of the

vector controller for a permanent magnet synchronous motor drive are evaluated and their

effects on maximum speed of the drive is presented. [16] discusses the implementation

of two different vector control strategies of the permanent magnet motor. A maximum

efficiency control algorithm based on an optimum d-axis controller is presented in [17].

Research based on efficiency control of PM machine drives at high speeds is presented in

[15]. With the high computational power of the DSP controllers, implementation of

complex algorithms for optimal control PM machine drives is now possible. Therefore,

research is being carried out in the study of different control algorithms. [19] provides

experimental results for a permanent magnet motor drive with a hysteresis current

controller; the paper also discusses operation in the flux weakening region. A technique

14

for the design of a speed controller that takes care of parameter variations in a permanent

magnet motor drive is presented in [18]. Of late, significant research effort has been

devoted to the technique of sliding mode control for AC drives. This control approach

circumvents the problem of parameter variation that exists in motor drives, with

minimum implementation complexity. The aspects of continuous time sliding mode

control and discrete time sliding mode control of permanent magnet motor drives has

been discussed in [2]. The theoretical and experimental results for sliding mode control

of permanent magnet machine drives are presented in [24].

In vector control of a PM machine, the rotor position is crucial for the

implementation of the control. The rotor position is usually sensed by means of shaft-

mounted sensors such as incremental encoders or resolvers. However, these sensors have

associated with them the problems of aging, wear and tear, maintenance. The sensors are

not feasible in harsh environments, where motor applications may be required. In

addition, the speed sensor and its mounting arrangement add to the expense of the entire

drive. All these problems have led to research in the area of sensorless control of

permanent magnet motor drives. A number of techniques for sensorless control have

been published. [29] discusses the sensorless control of a Brushless Permanent Magnet

DC motor where the rotor position is sensed based on the measurement of the trapezoidal

back EMF. This technique however, is not efficient at low speeds. Another technique

based on the flux estimation and observer algorithm is presented in [27]. The FOC in

[27] is applied by controlling the torque angle, which is obtained as a result of the flux

estimation. [26] presents another technique of sensorless control based on the principle

15

of torque angle estimation. A microprocessor-based implementation of a sensorless real

time observer control of PM synchronous motor is presented in [28]. This control utilizes

a sensorless full-state observer for the generation of controller feedback information. The

experimental results for a sensorless control technique based on the Shouse and Taylor

algorithm are presented in [25]. A modification to this algorithm is also proposed. [8]

presents the DSP based implementation of a position sensorless algorithm for control of a

Brushless DC motor. This control strategy is developed based on the instantaneous

voltage equation of a brushless dc motor with a sinusoidal flux distribution. This control

can be employed over the entire speed range, unlike the schemes based on induced EMF.

The control strategy in [8] has been discussed in this thesis.

16

CHAPTER 2

FUNDAMENTALS OF BRUSHLESS PERMANENT MAGNET MOTOR CONTROL

The Field Oriented Control (FOC) consists of controlling the stator currents

represented by a vector [11]. The main objective of this vector control is to transform the

three-phase time and speed dependent system into a two coordinate time invariant system

[1]. This enables control of the permanent magnet machine just like a pure DC machine.

This chapter describes the modeling of a 3-phase permanent magnet motor, the

principle of FOC and the fundamentals of a pure DC machine. The concept of sliding

mode control is also discussed.

2.1 Modeling of 3-phases Brushless DC Machine

A two-pole 3-phase brushless dc motor is shown in Figure 2.1 below [1].

17

Figure 2.1: Two pole Three Phase PM machine

The stator windings are identical, displaced by 120º, and sinusoidally distributed.

The voltage equations for this machine are as follows:

dtd

irv asassasλ

+= (2.1)

dtd

irv bsbssbsλ

+= (2.2)

dtd

irv cscsscsλ

+= (2.3)

In matrix form:

abcsabcssabcs pλirv += (2.4)

For currents, voltages and flux linkages:

( ) [ ]csbsasTabcs ffff = (2.5)

18

���

�

�

���

�

�

=

s

s

s

s

rr

r

000000

r (2.6)

The flux linkage is expressed as:

asmcsascsbsasbsasasasas iLiLiL λλ +++= (2.7)

bsmcsbscsbsbsbsasbsasbs iLiLiL λλ +++= (2.8)

csmcssbscsbsascsascs iLiLiL λλ +++= csc (2.9)

In matrix form:

'mλiLλ += abcssabcs (2.10)

������

�

�

������

�

�

+

−=���

�

�

���

�

�

=

)32sin(

)32sin(

sin'

πθ

πθ

θ

λλλλ

r

r

r

m

csm

bsm

asm'mλ (2.11)

'mλ is the amplitude of flux linkages established by the permanent magnet as

viewed from the stator phase windings.

With assumption of a round rotor, i.e. uniform air gap, the inductance matrix can

be expressed as [1]:

������

�

�

������

�

�

+−−

−+−

−−+

=

mslsmsms

msmslsms

msmsmsls

LLLL

LLLL

LLLL

21

21

21

21

21

21

sL (2.12)

where, Lls represents the leakage inductance and Lms the magnetizing inductance.

19

The expression for torque is [1]:

( )���

�

���

�−+�

�

�

� −−= rcsbsrcsbsasme iiiiiPT θθλ sin

23cos

21

21

2' (2.13)

In the analysis of ac electrical machinery, it is customary to apply Park's

transformation to transform the machine equations in from the abc frame to a new

coordinate system called the rotor reference frame. This is done to remove the

dependency of the stator and rotor inductances on the rotor mechanical angle. In this

case, however, it is done to make 'mλ independent of rθ . The transformation is given by:

abcsrs

rsqd fKf =0 (2.14)

( ) [ ]rsrdsrqsTr sqd fff 00 =f (2.15)

�������

�

�

�������

�

�

��

�

� +��

�

� −

��

�

� +��

�

� −

=

21

21

21

32sin

32sinsin

32cos

32coscos

32 πθπθθ

πθπθθ

rrr

rrr

rsK (2.16)

( )

�������

�

�

�������

�

�

��

�

� +��

�

� +

��

�

� −��

�

� −=−

132sin

32cos

132sin

32cos

1sincos1

πθπθ

πθπθ

θθ

rr

rr

rr

rsK (2.17)

Substituting these values in equation abcsabcssabcs pλirv += (2.4), we have,

])[()( 11 rqdosrs

rqdoss

rqdos

rs p λKirvK

−− += (2.18)

20

���

�

�

���

�

�

+���

�

�

���

�

�

������

�

�

������

�

�

+

+

=010

00

0230

0023

'0

rm

ros

rds

rqs

ls

msls

msls

rsqd

iii

L

LL

LL

λλ (2.19)

Thus, in matrix form the equations for a 3-phase permanent magnet machine can

be written as:

���

�

�

���

�

�

+���

�

�

���

�

�

���

�

�

���

�

�

++−

+=

���

�

�

���

�

�

00

0000 'rmr

ros

rds

rqs

sss

sssssr

ssrsss

ros

rds

rqs

iii

pLrpLrLLpLr

vvv λω

ωω

(2. 20)

where, rθ is the rotor displacement.

where r sqdf 0 denote the stator machine variables (currents, voltages, or fluxes) in

the rotor reference frame, and denote the variables in the abc reference frame. When

a balance three phase condition is assumed, the quantities in the 0-axis disappear, leaving

only the d-q axis variables

The expression for electromagnetic torque can be obtained from equation (2.13)

as:

rqs

rme i

PT '22

3 λ= (2. 21)

The torque and speed are related as-

Lrmr

e TPB

dtd

PJT +�

�

���

�+��

���

�= ωω 22 (2. 22)

Choosing the rotor speed (ωr) and the stator currents (iqs, ids) as the state variables

of the system, the following state space can be derived:

21

rqs

ssr

ss

'rmr

dsrrqs

ss

srqs v

Lω

Lλ

iωiLr

dtdi 1+−−−= (2.23)

rds

ss

rqsr

rds

ss

srds v

Liωi

Lr

dtdi 1++−= (2.24)

JTPi

JλPω

JB

dtdω Lr

qs

'rm

rr

22

2

−��

���

�+−= (2.25)

The above equations (2. 20) to (2. 22) can be rearranged in order to write a time

domain block diagram:

rrm

rdsrss

rqsss

rqs iriprv ωλωττ

')1( +++= (2. 26)

rqsrss

rdsss

rds iriprv ωττ −+= )1( (2. 27)

rmLe JpBPTT ω)(2 +=− (2. 28)

where, τs = Lss/rss. Solving for iqs, ids and ωr,

)(1

1 'r

rm

rdsrss

rqs

s

srqs irvp

ri ωλωτ

τ−−

+= (2.29)

)(1

1 rqsrss

rds

s

srds irvp

ri ωτ

τ+

+= (2.30)

)(2 Lem

r TTBJpP −+

=ω (2.31)

Using equations (2. 26) through (2.31), the time domain block diagram for a

brushless DC machine can be obtained [1] as in figure below:

22

Figure 2.2: Time domain block diagram of a brushless DC machine

2.2 Control of a DC Machine

Figure 2.3 shows a diagram of a separately excited dc machine [4, 12].

Figure 2.3: Separately excited dc machine

23

State space equations describing the dynamics of the dc machine in Figure 2.3 are

given by:

JT

JBi

JK

JT

JB

JT

dtd L

afTLe −ω−Φ=−ω−=ω (2.32)

afa

Ea

a

aa vLKi

LR

dtdi +ωΦ−−= (2.33)

fff

ff vLR

dtd

+Φ−=Φ

(2.34)

where the speed ω, the armature current ai , and the field flux fΦ are the state variables,

and the armature voltage av and the field voltage vf are the control inputs. The torque

produced by the motor is [4]

afTafTe iiKiKT ⋅⋅=⋅Φ⋅=' (2.35)

It can be seen from the above equations, that the dynamics of the dc machine are

in fact non-linear due to the multiplicative terms ' af iφ ' and ' ωφ f ' in equations (2.32)

and (2.33) respectively. However, in a dc machine, the field flux fΦ is always kept

constant by applying a constant dc voltage at the field terminal vf. With a constant

fΦ = constΦ , the dynamics of ω and ia become:

LaL

aconstT Tcbia

JT

JBi

JK

dtd ⋅−ω⋅−⋅=−ω−�

�

���

� Φ=ω (2.36)

aaaconsta

Ea

a

aa vkikvLKi

LR

dtdi +ω⋅−⋅=+ω��

�

����

�Φ−−= 54 (2.37)

24

which represent a second order linear time invariant (LTI) system with and ia as the

state variables and va as the input.

If a current source is used to drive the dc motor, then the current ia becomes the

input to the system and its dynamic in equation (2.37) vanishes. The system reduces to a

first order system given in (2.36) and the current ia can then be used to force the speed to

follow the reference speed. A speed feedback loop with a PID controller can be used to

shape the speed response as shown in Figure 2.4.

Figure 2.4: DC motor speed control system with current source input

In practice, a current source is seldom used to drive a dc motor, and a variable

voltage source is used instead. For this case, an inner current loop controller can be

added to force the armature current to follow the commanded current as shown in Figure

2.5.

25

Figure 2.5: DC motor speed control system with 2 PID nested loop

2.3 Principles of Field Oriented Control

The brushless DC motor is a current controlled Permanent Magnet Synchronous

motor, which belongs to the category of alternating current drives. The control of a

brushless dc motor performed in the d-q reference frame is termed as field-oriented

control (FOC). FOC is also termed as vector control, implying that a current vector

should be controlled rather than only one current component as in the case of a pure DC

motor. The vector control of brushless dc motor aims at controlling it like a dc machine.

This is achieved by transforming the machine equations into a coordinate frame

(reference frame), which rotates along with the rotor fluxes. This transformation is

referred to as the Park's transformation [1]. Using this transformation, the flux dynamics

can be controlled independently from the torque/speed dynamics, and, just like a dc

machine, once the flux is kept constant; the torque/speed dynamics becomes a linear time

invariant system (LTI). Thus, it can be said that FOC is an approach that uses a state

transformation after which the decoupling and linearization tasks can be performed easily

[2].

26

In the vector control of a brushless permanent magnet machine, the state space

model can be obtained by referring to equations (2.29) to (2.31) as follows:

rds

ss

rqsr

rds

ss

srds v

Lii

Lr

dtdi 1++−= ω (2.38)

rqs

ssr

ss

rmr

dsrrqs

ss

srqs v

LLii

Lr

dtdi 1' +−−−= ωλω (2.39)

JTPi

JP

JB

dtd Lr

qs

rm

rr

22

'2−�

�

���

�+−=λωω (2.40)

and the expression for torque is given by:

rqs

rme i

PT '22

3 λ= (2.41)

The system given in equations (2.38) to (2.41) is still non-linear and coupled.

However, if the machine is driven by ideal current sources, the stator dynamics (2.40) and

(2.41) vanish. In addition, the rotor angle dynamics plays no role in determining the

speed and flux dynamics. Moreover, the form of equation (2.40) is similar to that of the

speed of a dc machine presented in equation (2.36). In case of a permanent magnet

machine, the rotor flux is constant and is supplied by the magnet and therefore, ideally

0=dsi . Once the rotor flux is constant, the speed dynamics becomes a linear time

invariant (LTI) system, and it can be controlled just like in the case of the dc machine

described earlier.

The goal of current control is to design a current controller to track the desired

current that is provided by a speed controller in the outer loop. Modern techniques

proposed for this purpose include the continuous time sliding mode controllers

27

(CTSM)[2]. These have the advantages of ease of implementation, robustness to

parameter variation and good dynamic response. However, some deterioration in

microprocessor-based implementation is observed due to the limitation of the maximum

sampling time, which in turn limits the minimum-switching interval of the sliding mode

controller. This problem can be solved by employing a discrete time Sliding mode

(DTSM) controller [2] in conjunction with hardware PWM. This control has been

implemented for the system under study. DTSM control is an adaptation of CTSM

control for systems that operate at discrete time samples as in digital controllers. It is

based on the prediction of the trajectory at the next state and therefore exhibits almost

perfect tracking and a very good dynamic response, but has the disadvantage of being

sensitive to parameter variations. This is further discussed in detail in the next chapter.

2.4 Fundamentals of Sliding Mode Control:

Sliding modes appear in a dynamic system governed by ordinary differential

equations with discontinuous right hand sides [2]. Sliding mode is the motion that occurs

when the control as a function of the system state switches at a very high frequency.

Consider the first order tracking relay system.

uxfx += )(� (2.42)

with the bounded function 0)( fxf < = constant and control of the tracking error

e = r(t) x, where r(t) is the reference input and u is given by

u = u0 sign(e) where, u0 = constant.

28

Thus, e and de/dt have different signs for u0 > f0 + mod(r) or in other words,

magnitude of tracking error decays to zero at a finite rate. e=0, after a finite time interval

T. The motion for t>T is termed as sliding mode.

2.4.1. Concept of Discrete time Sliding Mode Control

2.4.1.a. Definition

Consider a general continuous time system:

),,( tuxfx =� (2.43)

with a switching function,

��

���

, the state trajectory belongs to the sliding

manifold with,

29

)(0)( smk kkxs ≥∀= (2.47)

This motion is termed as "discrete time sliding mode"[2].

A control input u needs to be selected such that at each sampling point k, select

ku such that this control input, to be constant during the next sampling interval t∆ , will

achieve 0)( 1 =+kxs at the next sampling point (k+1).

)(

),(1

kk

kkk

xuu

uxFx

=

=+ (2.48)

Thus in a discrete time system the state hits the sliding manifold at each sampling

point. The manifold is reached after a finite number of steps ksm and thereafter the state xk

remains on the manifold.

2.4.1.b. Stability Criterion

In order to design a DTSM control for a system, let us assume that a sliding mode

manifold is linear for an nth-order discrete system-time system )(1 kk xFx =+ , i.e.

kk Cxs = . Then the condition for existence of sliding mode is of the form:

))((1 kk xFCs =+ (2.49)

To design a DTSM law based on the condition in equation (2.49), consider a

linear time-invariant system,

)()()()( tDrtButAxtx ++=� (2.50)

where, x (t) is the state vector, u(t) is the control, r(t) is the reference input and A,

B and D are constants. This can be represented in discrete for with a sampling interval

t∆ as:

30

kkkk rDuBxAx***

1 ++=+ (2.51)

where, ��∆

−∆∆

−∆∆ ===t

ttAt

ttAtA DdeDBdeBeA0

)(*

0

)(** ττ

According to equation (2.49), discrete-time sliding mode exists if the matrix *CB

has an inverse and the control uk is defined as the solution of:

)()(

0

**1*

***1

kkk

kkkk

rCDxCACBu

uCBrCDxCAs

+−=�

=++=

−

+ (2.52)

In order to compute the bounds on the control in order to achieve stability [2],

suppose that the control can vary within 0uuk ≤ and the available control resources are

such that,

0**1* )(.)( urCDxCCACB kk

≤

=00

0

uuforu

uu

uuforu

u

eq

eq

eq

eqeq

k

k

k

kk

k (2.54)

where, eqk

u is represented as,

))(()()( **1*1* kkkk rCDxCCACBsCBu eq +−−−=−− (2.55)

and

31

kkkkk uCBrCDxCCAss***

1 )(( ++−+=+ (2.56)

2.4.1.c. Proof of Convergence

To prove convergence of this domain [2], consider the case when 0uu eqk > and

equation (2.54)is satisfied. Then, from (2.55) and (2.56) we have,

)1)()(( 0**

1

eq

eq

k

kkkkk

u

uurCDxCCAss −+−+=+ (2.57)

Thus,

k

kkk

k

kkkkk

s

CBurCDxCCAs

u

uurCDxCCAss

eq

eq

<

−+−+≤

−+−+=

−

+

1*0**

0**

1

)())(

)1())((

(2.58)

Hence, ks decreases monotonically and after a finite number of steps, 0uu eqk <

is achieved. Discrete sliding mode now takes place from the next sampling point.

The following chapter has a detailed discussion of how the discrete time sliding

mode control is applied for the current control of a permanent magnet machine.

32

CHAPTER 3

CLOSED LOOP CONTROL OF PERMANENT MAGNET BRUSHLESS DC MOTOR WITH SPEED SENSOR

This chapter discusses the design of the discrete time sliding mode controllers for

the d-axis and q-axis currents. The theory of Space Vector Pulse Width Modulation

(SPWM) is also discussed. The last section describes the simulation studies performed

for validation of the design and presents the results of the simulation.

3.1 Speed Regulation

Determination of q-axis command current *qsi :

From equation (2.25), the state equation for rotor speed is given by:

JTPi

JλPω

JB

dtdω Lr

qs

'rm

rr

22

2

−��

���

�+−= (3. 1)

A PI controller has been implemented for the speed loop in order to compute the

command current for the q-axis *qsi . The reference speed tracked is rω .

� −+−= dtKKi rrirrpqs )()(*** ωωωω (3.2)

33

Determination of d-axis command current *dsi :

The machine under consideration has uniform air gap i.e. it does not have salient

poles. For this construction, in order to obtain the maximum possible torque for a given

stator current, the d-axis current must be zero. Therefore, the d-axis command current is

defined as:

0* =dsi (3. 3)

3.2 Current Regulation

As discussed earlier, the equations for the brushless dc motor are as follows:

rrm

rdsrss

rqsss

rqs iriprv ωλωττ

')1( +++= (3. 4)

rqsrss

rdsss

rds iriprv ωττ −+= )1( (3. 5)

rmLe JpBPTT ω)(2 +=− (3. 6)

rqs

rme i

PT '22

3 λ= (3. 7)

For the d-axis we have,

ss

dsqsrds

ss

sds

LV

iiLr

dtdi

++−= ω (3. 8)

This can be represented as,

dss

dsss

sds uL

iLr

dtdi 1+−= (3. 9)

where,

rdsddecpldd vvu += (3.10)

34

qsrssddecpld iLv ω= (3.11

Thus in state space form we have,

ddsds ubiai +=� (3. 12)

where,

ss

sLr

a −= and ssL

b 1=

In discrete form equation (3. 12) can be written as:

kkk ddsds uBiAi**

1+=

+ (3. 13)

TLr

aT sss

eeA−

==* (3.14)

ssss

TssLsr

LrL

ea

AbB

−− −=−= 1]1[

1** (3.15)

where T is time sampling time.

As per equation 2.49, we select the condition for existence of sliding mode as:

11 +=+ kdsk is (3. 16)

with kdsk ix = and C=1.

Thus, as per equation 2.52, the control can be defined as:

kk

k

dsd

kkd

iBAu

rCDxCACBu

*

*

**1* )()(

−=

+−= −

(3. 17)

Thus, from equation 2.56 it follows:

35

0

)1(

)((

1

*

***

1

***1

=

��

�

�

��

�

�−+−+=

++−+=

+

+

+

kds

kdskdskdskds

kkkkk

i

iBABiAii

uCBrCDxCCAss

(3. 18)

Thus, the sliding manifold s=0, is reached in the next step and the control can be

said to be stable.

Substituting values in equation (3. 17), the control voltage for the d-axis can be

computed as:

kddecpldkds

kds VBiA

V −−

= *

*

(3. 19)

Substituting values of A* and B*,

kddecpldTssLsr

s

kds

TssLsr

kds V

er

ieV −

−

−=

−

−

)1(1

(3.20)

Approximating TLr

ess

sT

Lr

ss

s

−=−

1 , we can compute the d-axis command voltage

as,

kddecpldss

skdssskds VL

rT

iLV −

��

���

��

���

��

���

−−= 1 (3.21)

Similarly, for q-axis:

ss

rqs

ss

rmr

dsrqsss

sqs

Lv

Lii

Lr

dtdi

+−−−='λωω (3. 22)

This can be represented as:

36

qss

qsss

sqs uL

iLr

dtdi 1+−= (3. 23)

where,

rqsqdecpldq vvu += (3.24)

)('

ss

rmr

dsrssdecpld LiLv

λωω −−= (3. 25)

Thus in state space form we have,

qqsqs ubiai +=� (3. 26)

where,

ss

sLr

a −= and ssL

b 1=

In discrete form equation (3. 26) can be written as:

kkk qqsqs uBiAi**

1+=

+ (3. 27)

TLr

aT sss

eeA−

==* (3.28)

sssss

TssLsr

LrL

ea

AbB

−− −=−= 1]1[

1** (3.29)

where T is time sampling time.

As per equation 2.49, we select the condition for existence of sliding mode as:

1*

1 ++ −= kqsqsk iis (3. 30)

where, *qsi is the reference current of the q-axis.

with C=-1.

37

Thus, as per equation 2.55, the control can be defined as:

*

**

**1*1* ))(()()(

BiAi

u

rCDxCCACBsCBu

kqskqseqkq

kkkkeqq

−=

+−−−= −−

(3.31)

Thus, from equation 2.56 it follows:

In order to have a stable system, the control has to be bounded as per equation

2.54 as below:

���

�

���

�

�

>

≤

=

00

0

uuforu

uu

uuforu

u

eqqk

eqqk

eqqk

eqqkeqqk

qk (3.32)

where, u0 is defined as:

0**1* )(.)( urCDxCCACB kk

38

Approximating TLr

ess

sT

Lr

ss

s

−=−

1 , we can compute the q-axis command voltage,

kk

k qdecpldss

skqsqsssqs VL

rT

i

Ti

LV −��

���

��

���

��

���

−−= 1

*

(3. 37)

The basic control scheme can be summarized in the following block diagram:

Figure 3.1: DTSM Current Controller for Permanent Magnet Motor

3.3 Description of the power converter

Figure 3.2: Three-phase bridge inverter

39

In practice, the variable voltage source shown in Figure 3.1 is implemented using

a three-phase bridge inverter as shown in Figure 3.2. A pulse width modulation (PWM)

scheme is needed to ensure that the instantaneous voltages applied to the machine

approximate those commanded from the controller.

Various types of PWM schemes that have been developed so far. An approach to

PWM modulation, called the Space Vector PWM (SPWM) [5] is has been implemented

and discussed below. This method refers to a way of determining the switching sequence

of the upper three power transistors of a three-phase VSI. It has been shown to generate

less harmonic distortion in the output voltages and currents in the windings of the motor

load as compared to other techniques such as direct sinusoidal modulation technique.

3.4 Theory of SV PWM Technique

The SV PWM technique is based on the space vector approach to the analysis of

rotating machine [5]. Here, a space vector represents the three machine voltages. Due to

the discrete switching nature of the inverter, this vector can attain only six spatial

positions plus two zero vectors. The eight states of this vector according to the eight

switching positions of the inverter are represented in figure below.

Figure 3.3: Switching States Corresponding to the 8 possible Switching States of the Inverter

40

Figure 3.4: Output Voltage Space Vectors Corresponding to the 8 possible Switching States of the Inverter

As in figure above, the nonzero vectors form the axes of a hexagonal. The angle

between any adjacent two non-zero vectors is 60 degrees. The zero vectors are at the

origin and apply zero voltage to a three-phase load. These eight vectors are called the

Basic Space Vectors and are denoted here by V1, V2, V3, V4, V5, V6, V7 and V8.A

PWM modulation technique is said to be optimum when:

- The current vector has minimum deviation through the various switching states,

which assures low harmonic content.

- The cycle time is as short as possible, as this implies high order harmonics that are

easy to filter out.

41

In a switching state, the deviation current is defined as:

dt)V(VL

∆Ib

a

t

tref� −=

1 (3. 38)

where, ta and tb are the beginning and end of switching state respectively.

In SV PWM, the above requirements are met when only the 3 switching states

adjacent to the reference vector are employed and only three successive switching states

comprise the cycle required for the average voltage to be equal to the reference voltage.

To understand this, consider the example when the position command for Vref

instantaneously lies between V1 and V2 as shown in Figure 3.5

Figure 3.5: Space Vector Representation of the Switching times required to produce vector Vref

Thus, in a switching interval T,

dtVdtVdtVVdtdtVT

TT

TT TTref ��� ��

+++==

1

21

21

70

20 0

10

(3. 39)

42

Since V1 and V2 are constants and V7 =0,

22

11 V

TTV

TTVref += (3. 40)

Thus, the two adjacent vectors are weighted with respect to time in order to

achieve the output voltage.

In rectangular co-ordinates, the space vectors can be represented as:

��

���

�=��

���

�+��

���

�

αα

ππ

sincos

32

3sin3cos

32

01

32

21 dcdcdc VTVTVT (3. 41)

dc

ref

V

Va = (3. 42)

Thus,

087

2

1

3sin)sin(

3sin)3sin(

TTT

TaT

TaT

==

=

−=

πα

παπ

(3. 43)

Referring to fig, the hexagon can be divided into six distinct sectors depending on

the value of the angle α. The switching pattern in each sector is summarized in Table 3.1.

Sector No. Range of α (deg) Switching Pattern I 0° to 60° 8217218 II 60° to 120° 8327238 III 120° to 180° 8347438 IV 180° to 240° 8547458 V 240° to 300° 8567658 VI 300° to 360° 8167618

Table 3.1: Switching patterns for all six sectors.

43

The transistor state for each switching command is summarized in Table 3.2

below:

Switch Command Q1 Q2 Q3 Q4 Q5 Q6 1 0 1 1 1 0 0 2 0 0 1 1 1 0 3 1 0 1 0 1 0 4 1 0 0 0 1 1 5 1 1 0 0 0 1 6 0 1 0 1 0 1 7 0 0 0 1 1 1 8 1 1 1 0 0 0

Table 3.2: Switching command for all six transistors.

The switching pattern for sector I is shown in Figure 3.6 below:

Figure 3.6: Optimum pulse pattern of space vector PWM for sector I

44

3.5 Simulation Studies

The simulation studies are performed using Matlab Simulink. Simulink block

diagrams are constructed for the equivalent feedback control systems shown in Figure

3.1. A block diagram of the complete SIMULINK system is shown in Figure 3.7.

Figure 3.7 Simulink block diagram for computer simulation studies

The motor has been modeled as explained in chapter 2 employing the following

equations.

)(1

1 'r

rm

rdsrss

rqs

s

srqs irvp

ri ωλωτ

τ−−

+= (3. 44)

)(1

1 rqsrss

rds

s

srds irvp

ri ωτ

τ+

+= (3. 45)

)(2 Lem

r TTBJpP −+

=ω (3. 46)

45

The Simulink block diagram for the motor model is shown in Figure 3.8.

Figure 3.8 Simulink Block diagram for Motor Model

The parameter estimation was carried out by performing the step response test [6]

as shown in Figure 3.9.

46

Figure 3.9 Setup for Step Response Test

The test was set up to apply a step input DC step voltage to two phases of the

motor. The values of V and I were observed on the oscilloscope based on the steady state

values, "rs" was computed. The rise time of the transient was observed in order to

calculate the value of "Lss". The values that were thus obtained and employed in the

simulation are:

rs = 0.097Ω. Lss = 0.19 mH.

The following PI controller parameters have been obtained for the speed

controller:

Speed controller: 5.=PK 3.=IK .

The DTSM blocks are implemented as in discussed in section 3.1. The following

figure shows the Simulink diagram for the DTSM (discrete time sliding mode control.)

for q-axis. The Space Vector PWM has been implemented as per the logic explained in

section 3.2. This function has been coded in MATLAB.

47

Figure 3.10: DTSM Controller Simulink Block Diagram

The results of simulation for a speed reference of 1000 rpm are presented in

Figures 3.11 3.13.

Figure 3.11 Simulation results for Speed

48

Figure 3.12 Simulation results for Iqs

Figure 3.13 Simulation results for Vab

49

CHAPTER 4

OVERVIEW OF THE TMS320F240 DSP

This chapter gives a brief summary of the various features of the TMS320F240

digital signal processor offered by Texas Instruments. The TMS320F240 is based on the

modified Harvard architecture, which supports separate bus structures for program space

and data space. This multiple bus structure allows simultaneous reading of data and

instructions thus enabling the execution of most instructions in a single machine cycle. A

third space, the input/output (I/O) space is also available and is accessed through the

external bus interface.

4.1 DSP Architecture

The basic block diagram of the DSP architecture is shown in Figure 4.1 below.

This chapter provides a comprehensive background on the features of the TMS320F240

as described in [3,30,31]. The chapter also introduces the principle of fixed-point

arithmetic, which has been employed throughout the DSP-based implementation of FOC

of permanent magnet machines.

50

Figure 4.1 TMS320F240 Block Diagram

The TMS320F240 is composed of three main functional units: the DSP

Core/CPU, the internal memory and the peripherals. In addition to these basic units, there

are a number of system features such as the memory map, device reset, interrupts, digital

I/O, clock generation and low-power operation.

51

4.2 Memory

The TMS320F240 has two kinds of on-chip memory-

4.2.1 Dual-access RAM (DARAM)

The DARAM allows writes to and reads from the RAM in the same cycle. It has

1056 words and is configured as three blocks - block B0, block B1 and block B2. Block

B0 is a 256-word block that can be configured as data or program memory. Block B1 is

256 words of data memory and block B2 is 32 words of data memory.

4.2.2 Flash EEPROM

The TMS320F240 includes 16K words of Flash EEPROM. This memory acts as

a non-volatile storage for programs. It allows one access per cycle in read mode. In write

mode (programming), it requires a 5-V supply that is generated by the chip itself.

The memory is organized into four selectable spaces-

1. Program Memory

This is the space where the application program code resides. The program space

can address up to 64K 16-bit words of external and on-chip memory. The memory map

is as shown in Figure 4.2. The chip has two modes of operation:

Microprocessor Mode (pin MP/MC=1): In this case, when a reset occurs, the

device fetches the reset vector from external memory.

Microcomputer Mode (pin MP/MC=0): In this mode, device fetches reset vector

from on-chip flash memory.

52

Figure 4.2 Program Memory Map of TMS320F240

2. Local Data Memory

This memory can address up to 64K 16-bit words and includes the on-chip

DARAM blocks B1, B2 and external memory. Block B0 is included if CNF bit is set to

zero. The memory map is shown in Figure 4.3 below.

53

Figure 4.3 Local Data Memory map for TMS320F240

3. Global Data Memory

Addresses in the upper 32K words of local data memory i.e. 8000h-FFFFh can be

configured as global data memory. This is mainly used for multi-processor systems. The

global memory allocation register (GREG) decides the size of the global data memory

that is between 256 to 32K words. The different possible memory configurations with the

allowable values of the GREG are listed in the Table 4.1.

54

Note: X = Don't care

Table 4.1 Global Data Memory Map for TMS320F240

4. I/O Space

The I/O space memory addresses up to 64K 16-bit words. The memory map is

shown in Figure 4.4.

Figure 4.4 I/O Memory Map for the TMS320F240

GREG Value Local memory Global memory High Byte Low Byte Range Words Range Words

XXXXXXXX 0000 0000 0000h-FFFFh 65536 - 0 XXXX XXXX 1000 0000 0000h-7FFFh 32768 8000h-FFFFh 32768 XXXX XXXX 1100 0000 0000h-BFFFh 49152 C000h-FFFFh 16384 XXXX XXXX 1110 0000 0000h-DFFFh 57344 E000h-FFFFh 8192 XXXX XXXX 1111 0000 0000h-EFFFh 61440 F000h-FFFFh 4096 XXXX XXXX 1111 1000 0000h-F7FFh 63488 F800h-FFFFh 2048 XXXX XXXX 1111 1100 0000h-FBFFh 64512 FC00h-FFFFh 1024 XXXX XXXX 1111 1110 0000h-FDFFh 65024 FE00h-FFFFh 512 XXXX XXXX 1111 1111 0000h-FEFFh 65280 FF00h-FFFFh 256

55

4.3 CPU (Central Processing Unit)

This CPU of the TMS320F240 can be divided into five main sections:

a. Input Scaling Section

b. Multiplication Section

c. Central Arithmetic Logical Section (CALU)

d. Auxiliary Register Arithmetic Unit (ARAU)

e. Status Registers

Figure 4.5 Block Diagram of the TMS320F240 Central Processing Unit (CPU)

56

4.3.1 Input Scaling Shifter

This unit forms the interface between the 16-bit data bus and the 32-bit central

arithmetic logical unit (CALU). Its main function is to align the 16-bit data coming from

the program and data space to the 32-bit CALU as required by the data scaling arithmetic

as well as aligning masks for logical operations. The shifter shifts the value left by 0 to

16 bits. The unused LSBs are filled with zeros and the unused MSBs are either filled

with zeros, or sign extended, depending on the value of the sign extension mode (SXM)

bit in the ST1 register. The shift count is decided either by a constant embedded in the

instruction word or by the four LSBs of the TREG register.

4.3.2 Multiplier

This is a 16×16-bit hardware multiplier capable of signed and unsigned

multiplication in a single machine cycle. The 16-bit multiplicand is picked up from the

TREG, which is loaded from the data memory. The multiplier is a 16-bit value that can

be either from the data memory or from program memory. The 32-bit product is stored in

the product register PREG. This 32-bit product is then passed through the product shifter,

which passes a 32-bit value to the CALU or a 16-bit value to the data memory. The

shifter decides the shift count based on the status of the product shift mode PM bits of the

status register. Figure 4.5 summarizes the function of the multiplier.

4.3.3 Central Arithmetic Logic Unit (CALU)

The CALU performs many arithmetic and logic functions most of which it

performs in a single clock cycle. These fall under the categories of: 16-bit addition, 16-

57

bit subtraction, Boolean logic operations and Bit testing, shifting, and rotating. The 32-

bit accumulator always provides one input to the CALU. Either the product-scaling

shifter or the input data-scaling shifter provides the second input. For some of the

instructions, the sign extension (SXM) bit of the ST1 register determines if the sign

extension is employed in the CALU calculations. The CALU transfers its output to the

32-bit accumulator.

The 32-bit accumulator accepts input from the output of the CALU and is capable

of performing bit shifts or rotations on its contents. The 32-bit contents can be split into

two 16-bit segments for storage in the data memory. The contents of the accumulator are

passed through the output data-scaling shifter before they are stored into the data

memory. The carry bit (C, the overflow mode bit (OVM), the overflow flag bit (OV) and

the test/control flag bit (TC) of the status registers are associated with the accumulator.

The output data-scaling shifter accepts a 32-bit input from the accumulator

performs a 0 to 7-bit shift on it and provides a 16-bit output to the data bus. The shift

count is based on the value specified in the corresponding instruction. The MSBs are lost

during the shift and the LSBs are loaded with zeros. It must be noted here that the

contents of the accumulator remain unchanged during this process.

4.3.4 Auxiliary Register Arithmetic Unit (ARAU)

The main function of the ARAU is to perform arithmetic operations on the eight

auxiliary registers (AR0-7) in parallel with the operations occurring in the CALU. The

auxiliary registers are primarily employed for indirect addressing. They are also

employed:

58

- For support of conditional branches, calls and returns.

- For temporary storage of data

- As software counters by incrementing and decrementing the registers as required.

A specific auxiliary register can be selected by specifying the 3-bit value of the

auxiliary register pointer (ARP) in the status register ST0. Figure 4.6 shows the ARAU

and related logic.

Figure 4.6 Block Diagram of the ARAU for the TMS320F240

59

4.4 Peripherals

The TMS320F240 has a number of on-chip peripherals. Some of the peripherals

are accessed through the data bus while the other are accessed via the peripheral bus

which is mapped to the data bus through the system interface module. The integrated

peripherals of the TMS320x240 can be divided into the following subsections:

a. External memory interface

b. Event manager (EV)

c. Dual analog-to-digital converter (ADC)

d. Serial peripheral interface (SPI)

e. Serial communications interface (SCI)

f. Watchdog timer (WD)

a. External Memory Interface

The TMS320x240 can address up to 64K words × 16 bits of memory or registers

in each of the program, data, and I/O spaces. The TMS320F240 supports a wide range of

system interfacing requirements. Program, data, and I/O address spaces provide interface

to memory and I/O, maximizing system throughput. The full 16-bit address and data bus,

along with some space-select signals allow addressing of 64K 16-bit words in program

and I/O space. Due to the on-chip peripherals, external data space is addressable to 32K

16-bit words. I/O design is simplified by having I/O treated the same way as memory.

I/O devices are mapped into the I/O address space using the processors external address

and data buses in the same manner as memory-mapped devices.

60

b. Event-Manager (EV) Module

The Event Manager (EV) module of the TMS320F240 that provides numerous

features applicable in motion control. The EV comprises the following functional blocks:

1. Three general-purpose timers (GPT).

2. Three full compare units

3. Three simple compare units

4. Pulse-width modulation (PWM) circuits

5. Four capture units

6. Quadrature encoder pulse (QEP) circuit

The block diagram is shown in Figure 4.7.

1. General-purpose (GP) Timers:

There are three GP timers on the TMS320F240. The GP timer x (for x = 1, 2, 3)

includes:

a. A 16-bit timer up/down-counter, TxCNT for reads or writes

b. A 16-bit timer-compare register (double-buffered with shadow register), TxCMPR for

reads or writes

c. A 16-bit timer-period register (double-buffered with shadow register), TxPR for reads

or writes

d. A 16-bit timer-control register, TxCON for reads or writes

e. Selectable internal or external input clocks

f. A programmable prescaler for internal or external clock inputs

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g. Control and interrupt logic for four maskable interrupts: underflow, overflow, timer

compare, and period interrupts

h. A timer-compare output pin with configurable active-low and active-high states, as

well as forced-low and forced-high states.

i. A selectable direction (TMRDIR) input pin (to count up or down when directional up/

down count mode is selected)

The GP timers can be operated independently or synchronized with each other. A

32-bit GP timer also can be configured using GP timer 2 and 3. The compare register

associated with each GP timer can be used for compare function and PWM-waveform

generation. There are two single and three continuous modes of operation for each GP

timer in up- or up/ down-counting operations. Internal or external input clocks with

programmable prescaler are used for each GP timer. The state of each GP timer/compare

output is configurable by the general-purpose timer-control register (GPTCON). GP

timers also provide the time base for the other event-manager sub-modules: GP timer 1

for all the compares and PWM circuits, GP timer 1 or 2 for the simple compares to

generate additional compare or PWMs, GP timer 2 or 3 for the capture units and the

quadrature-pulse counting operations. Double buffering of the period and compare

registers allows programmable change of the timer (PWM) period and the compare/PWM

pulse width as needed.

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Figure 4.7 Block Diagram of the Event Module for the TMS320F240

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2. Full Compare Units:

There are three full compare units on TMS320x240. These compare units use GP

timer1 as the time-base and generate six outputs for compare and PWM-waveform

generation using programmable dead band circuit. The state of each of the six outputs is

configured independently. The compare registers of the compare units are double-

buffered, allowing programmable change of the compare/PWM pulse widths as needed.

The dead band generator circuit includes three 8-bit counters and an 8-bit compare

register. Desired deadband value (from 0 to 102 sec) can be programmed into the

compare register for the outputs of the three compare units.

3. Simple Compare Units:

The TMS320F240 is equipped with three simple compares that can be used to

generate three additional independent compare or high-precision PWM waveforms. GP

timer1 or 2 can be selected as the time-base for the three simple compares. The states of

the outputs of the three simple compares are configurable as low-active, high-active,

forced-low, or forced-high independently. Simple compare registers are double-buffered,

allowing programmable change of the compare/PWM pulse widths as needed.

4. Compare/ PWM Waveform Generation:

Up to 12 compare and/or PWM waveforms (outputs) can be generated

simultaneously by TMS320x240: three independent pairs (six outputs) by the three full

compare units with programmable dead bands, three independent compares or PWMs

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(three outputs) by the simple compares, and three independent compare and PWMs (three

outputs) by the GP-timer compares.

5. Capture Unit:

The capture unit provides a logging function for different events or transitions.

The values of the GP timer 2 counter and/or GP timer 3 counter are captured and stored

in the two-level first-in first-out (FIFO) stacks when selected transitions are detected on

capture input pins, CAPx for x = 1, 2, 3, or 4. The capture unit of the TMS320x240

consists of four capture circuits.

6. Quadrature-Encoder Pulse (QEP) Circuit:

Two capture inputs (CAP1 and CAP2) can be used to interface the on-chip QEP

circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed

on-chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2 or 3

is incremented or decremented by the rising and falling edges of the two input signals

(four times the frequency of either input pulse).

c. Dual Analog-to-Digital Converter (ADC)

A simplified functional block diagram of the ADC module is shown in Figure 4.8.

The ADC module consists of two 10-bit ADCs with two built-in sample-and-hold (S/ H)

circuits. The TMS320F240 has 16 analog input channels is available on. Eight analog

inputs are provided for each ADC unit by way of an 8-to-1 analog multiplexer. Minimum

total conversion time for each ADC unit is 6.1 µs. Total accuracy for each converter is

±1.5 LSB. Reference voltage for the ADC module needs to be supplied externally

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through the two reference pins, V REFHI and V REFLO. The digital result is expressed

as:

VREFLOVREFHIgeInputVolta1023ultDigitalRes

−×=

Figure 4.8: Analog to Digital Converter Module Block Diagram

Functions of the ADC module include:

1. Two input channels (one for each ADC unit) that can be sampled and converted

simultaneously

2. Each ADC unit can perform single or continuous S/H and conversion operations.

3. Two 2-level-deep FIFO result registers for ADC units 1 and 2

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4. ADC module (both A/D converters) can start operation by software instruction,

external signal transition on a device pin, or by event-manager events on each of the GP

timer/compare output and the capture 4 pins.

5. The ADC control register is double-buffered (with shadow register) and can be written

to at any time.

6. A new conversion of ADC can start immediately or when the previous conversion

process is completed according to the control register bits.

7. At the end of each conversion, an interrupt flag is set and an interrupt is generated if it

is unmasked/enabled.

d. Serial Peripheral Interface (SPI) Module

The TMS320F240 devices include the four-pin serial peripheral interface (SPI) module.

The SPI is a high-speed synchronous serial-I/O port that allows a serial bit stream of

programmed length (one to eight bits) to be shifted into and out of the device at a

programmable bit-transfer rate. Normally, the SPI is used for communications between

the DSP controller and external peripherals or another processor. Typical applications

include external I/O or peripheral expansion through devices such as shift registers,

display drivers, and ADCs. Multi-device communications or party line configurations are

supported by the master/slave operation of the SPI.

Some of the important features of the SPI module include:

- Two operational modes: master and slave

- Baud rate: 125 different programmable rates / 2.5 Mbps at 10-MHz SYSCLK

- Data word format: one to eight data bits

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- Four clocking schemes controlled by clock polarity and clock-phase bits include:

Falling edge without phase delay, falling edge with phase delay, rising edge without

phase delay and rising edge with phase delay.

- Simultaneous receive and transmit

- Transmitter and receiver operations are accomplished through either interrupt-driven or

polled algorithms.

e. Serial Communications Interface (SCI) Module

The TMS320F240 includes a serial communications interface (SCI) module. The SCI

module supports digital communications between the CPU and other asynchronous

peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and

transmitter are double-buffered, and each has its own separate enable and interrupt bits.

Both can be operated independently or simultaneously in the full-duplex mode. To

ensure data integrity, the SCI checks received data for break detection, parity, overrun,

and framing errors. The bit rate (baud) is programmable to over 65000 different speeds

through a 16-bit baud-select register. Some of the important features of the SCI module

include:

- Two external pins

- SCITXD: SCI transmit-output pin or general-purpose bi-directional I/O pin

- SCIRXD: SCI receive-input pin or general-purpose bi-directional I/O pin

- Baud rate programmable to 64K different rates, up to 625 Kbps at 10-MHz SYSCLK

- Data word format: One start bit. Data word length programmable from one to eight

bits. Optional even/odd/no parity bit. One or two stop bits.

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- Four error-detection flags: parity, overrun, framing, and break detection

- Two wake-up multiprocessor modes: idle-line and address bit

- Half- or full-duplex operation

- Double-buffered receive and transmit functions

- Transmitter and receiver operations can be accomplished through interrupt-driven or

polled algorithms with status flags.

- Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another

character) and TX EMPTY flag (transmitter-shift register is empty)

- Receiver: RXRDY flag (receiver-buffer register is ready to receive another character),

BRKDT flag (break condition occurred), and RX ERROR (monitoring four interrupt

conditions)

- Separate enable bits for transmitter and receiver interrupts (except BRKDT)

- NRZ (non return-to-zero) format

f. Watchdog timer (WD)

The TMS320C240 device includes a watchdog (WD) timer and a real-time

interrupt (RTI) module. The WD function of this module monitors software and

hardware operation by generating a system reset if it is not periodically serviced by

software by having the correct key written. The RTI function provides interrupts at

programmable intervals.

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4.5 General purpose I/O ports

The processor has 28 pins sharing primary functions and I/O that can be divided

into 2 categories:

Group 1: Primary functions are shared with I/Os belonging to dedicated ports,

Port A, Port B and Port C.

Group 2: Primary functions belong to peripheral modules having built-in I/O

features as a secondary function (e.g. SCI, SPI, external interrupt and PLL clock

modules).

The control structure for Group1 type shared I/O pins is shown in Figure 4.9. The

only exception to this configuration is the CLKOUT/IOPC1 pin. Each pin has three bits

that define its operation:

i. Mux control bit this bit selects between the primary function (1) and I/O function

(0) of the pin.

ii. I/O direction bit if the I/O function is selected for the pin (mux control bit is set to

0), this bit determines whether the pin is an input (0) or an output (1).

iii. I/O data bit if the I/O function is selected for the pin (mux control bit is set to 0)

and the direction selected is an input, data is read from this bit; if the direction selected is

an output, data is written to this bit.

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Figure 4.9 Shared Pin Configuration

4.6 TMS320F240 Instruction Set

The TMS320F240 implements a comprehensive instruction set that supports both

numeric-intensive signal-processing operations and general-purpose applications, such as

multiprocessing and high-speed control. This processor has the ability to perform a

multiply-accumulate operation (often called a "MAC") in a single instruction cycle. The

multiply-accumulate operation is useful in DSP calculations such as the vector dot

product used for digital filtering, FFT. Almost every instruction can be completed in one

machine cycle. For maximum throughput, the next instruction is pre-fetched while the

current one is being executed. Because the same data lines are used to communicate to

external data, program, or I/O space, the number of cycles an instruction requires to

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execute varies, depending upon whether the next data operand fetch is from internal or

external memory. Highest throughput is achieved by maintaining data memory on chip

and using either internal or fast external program memory.

4.6.1 Addressing Modes

The TMS320x240 instruction set provides four basic memory-addressing modes:

Direct Addressing:

The instruction word contains the lower seven bits of the data memory address.

This field is concatenated with the nine bits of the data memory page pointer (DP) to

form the 16-bit data memory address. Therefore, in the direct-addressing mode, data

memory is paged effectively with 512 pages, each page containing 128 words.

Indirect Addressing

Indirect addressing accesses data memory through the auxiliary registers. In this

addressing mode, the address of the instruction operand is contained in the currently

selected auxiliary register. Eight auxiliary registers (AR0AR7) provide flexible and

powerful indirect addressing. To select a specific auxiliary register, the auxiliary register

pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.

There are seven types of indirect addressing: autoincrement or autodecrement,

postindexing by adding or subtracting the contents of AR0, single-indirect addressing

with no increment or decrement, and bit-reversed addressing [used in Fast Fourier

Transforms (FFTs)] with increment or decrement.

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Immediate Addressing

In this addressing, the actual operand data is provided in a portion of the

instruction word or words. There are two types of immediate addressing: long and short.

In short-immediate addressing, the data is contained in a portion of the bits in a single-

word instruction. In long-immediate addressing, the data is contained in the second word

of a two-word instruction. The immediate-addressing mode is useful for data that does

not need to be stored or used more than once during the course of program execution (for

example, initialization values or constants).

Register Addressing

The register-addressing mode uses operands in CPU registers either explicitly,

such as with a direct reference to a specific register, or implicitly, with instructions that

intrinsically reference certain registers. In either case, operand reference is simplified

because 16-bit values can be used without specifying a full 16-bit operand address or

immediate value.

4.7 Fixed Point Arithmetic

4.7.1 Fixed Point Representation

Since the TMS320F240 is a 16-bit fixed-point processor, this section gives a brief

background on the representation of fixed-point numbers.

The TMS320F240 uses the twos complement format for representation of binary

numbers. This type of representation can be understood from the example below:

+9 (decimal) is represented as 010012 (2s-comp) = 0*24 +1*23 +0*22 +0*21 +1*20

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-9 (decimal) is represented as 101112 (2s-comp) = -1*24 +0*23 +1*22 +1*21 +1*20

The above words are represented on 5 bits only. ForTMS320F240 the length of a

word is 16bit. To represent real numbers on this fixed-point architecture, a Qk format has

to be chosen by the user.

Qk numbers can be represented by the following general formula:

Z = - b15-k *215-k + b14-k *214-k +b0 +b-1 *2-1 + b-2 *2-2 ++ b-k *2-k

An implied dot separates the integer part from the fractional part of the Qk number

where k represents the quantity of fractional bit.

For example, the real number 2.14567 can be represented in Q13 with finite

precision as follows:

010.0 0100 1010 10012 = 0*22 + 1*21 + 0*20 + 0*2-1 + 0*2-2 + 1*2-3 + 0*2-4 + 0*2 -5 +

1*2 -6 + 0*2 -7 + 1*2 -8 + 0*2 -9 + 1*2 -10 + 0*2 -11 + 0*2 -12 + 1*2 -13

The number of bits in the fractional part affects the accuracy of the result while

the integer part affects the dynamic range of values that can be represented. The Q15

format offers the best precision but only real numbers comprised between 1 and +1 can

be represented. The Qk format offers a compromise between dynamic range and

precision.

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4.7.2 Arithmetic operations

Addition

The following example shows how two real numbers (X and Y) added in Q12

X = +5.71210 is represented as 0101. 1011 0110 01002 in Q12

Y = +3.45210 is represented as 0011. 0111 0011 10112 in Q12

SUM = X+Y

SUM is stored as 1001. 0010 1001 11112 in Q12 = 9.164 (decimal)

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Multiplication

The following example shows how two real numbers X coded in Q12 and Y coded

in Q10 are multiplied

X = 1.16810 is represented as 0001. 0010 1011 00002 in Q12

Y = 13.75110 is represented as 0011 01. 11 0000 00012 in Q10

000001001010110001 (1.168)

0001001010110000 (13.750)

000001001010110001 000000000000000000 000000000000000000 000000000000000000 000000000000000000 000001001010110001 000000000000000000 000001001010110001 000000000000000000 000001001010110000 0000000000000000 0000000000000000 000001001010110000 01000110000101000111101011 Thus, the result is PROD = 0100.0110000101000111101011 in Q22. Thus the

result of multiplication of a Qk number with a Qp number, has the format Qk+p.

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CHAPTER 5

EXPERIMENTAL SETUP

This chapter describes the development of the experimental setup for

implementation of the FOC control of permanent magnet machines. The system is based

on the TMS320F240 Digital Signal Processor (DSP) described in chapter 4.

The first section of this chapter explains the general features of the DSP board

hardware and software. The second section describ