Technical Note: Implementation of an Ultra Low-Power

FINAL DEGREE PROJECT

Electronics Engineering

Implementation of an Ultra Low-PowerReverse-Body-Bias Generator forLeakage Reduction in Digital Systems

NXP Semiconductors - Company Confidential

Author:Jaume Tornila Oliver

Supervisor:Gerard Villar Pique

August 6, 2013

NXP Semiconductors, Company Confidential - 2013

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Contents

1 Introduction 9

1.1 Leakage Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 Basic Theory of Switched-Capacitor Power Converters . . . . . . . . . . . . . . . . 10

1.2.1 Ideal Efficiency of the SCPC . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.2 Control Loop of the SCPC . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.3 General Considerations of the RBB Generator Design . . . . . . . . . . . . . . . . 15

1.3.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.4 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5 Structure of the Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Improvements on the Previous Design. Proposed Concept. 17

2.1 Previous Switched-Capacitor Power Converter. . . . . . . . . . . . . . . . . . . . . 19

2.2 Improved RBB Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Detailed Description of the Microelectronic Implementation. 25

3.1 Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.1 P-Well Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1.2 N-Well Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Reset Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2.1 Asynchronous Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3 Enable Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 Dual-Ramp Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4.1 Cross-Conduction Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5 Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.6 Non-overlapping Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.6.1 Phase-Detector Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.6.2 Schematic Alternatives for the Non-overlapping Block . . . . . . . . . . . . 41

3.7 Phase-Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.7.1 Potential Causes of Failure of the Phase-Control Block . . . . . . . . . . . . 45

3.8 Level-Shifter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.9 Switched-Capacitor Power Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.9.1 MOS-Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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3.9.2 Flying Capacitor Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.9.3 N-well Ripple Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.10 General Layout of the RBB Generator . . . . . . . . . . . . . . . . . . . . . . . . . 56

4 Simulation Results 59

4.1 Efficiency Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.2 Current Consumption of the RBB Generator . . . . . . . . . . . . . . . . . . . . . 60

4.2.1 Current Consumption of the Control Logic . . . . . . . . . . . . . . . . . . 60

4.2.2 Current Consumption of the Switched-Capacitor . . . . . . . . . . . . . . . 60

4.2.3 Improvement Proposals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3 PVT Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5 Conclusions 73

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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List of Figures

1.1 Voltage doubler schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2 Ideal model of the SCPC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Total output impedance approximation. Image reproduced from [1]. . . . . . . . . 12

1.4 Multi-ratio converter regulation schematic example. . . . . . . . . . . . . . . . . . 14

1.5 Hysteretic feedback loop scheme. Image reproduced from [1]. . . . . . . . . . . . . 14

1.6 Ideal N-well output voltage ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 Digital leakage current reduction versus RBB voltage in CMOS 90nm. Image repro-duced from [2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2 Expected well currents for different corners and temperatures. Image extracted from[2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3 Architectural modifications made to the RBB. . . . . . . . . . . . . . . . . . . . . . 19

2.4 SCPC diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.5 Improved SCPC diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.6 The dual-output SCPC. At the right side the equivalent circuit for each phase isdepicted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7 Example of the phase-control block output signals. From top to bottom the signalsare the output of phase A, phase N and phase P, respectively. . . . . . . . . . . . . 22

2.8 Detail of the RBB signals. From top to bottom the signals are the N-well and P-welloutputs, the outputs of the N and P-comparator, the reset signals for the N andP-comparators and the oscillator output. . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1 P-well comparator schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2 P-well comparator transfer function after adding an input capacitor. . . . . . . . . 26

3.3 P-well output voltage in case the P-comparator capacitor is discharged. . . . . . . 27

3.4 N-well comparator schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5 Schematic of the voltage divider of the N-comparator and simplified version of thelayout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.6 Layout of the voltage divider of the N-comparator. . . . . . . . . . . . . . . . . . . 32

3.7 Schematic alternatives for the N-comparator. . . . . . . . . . . . . . . . . . . . . . 32

3.8 Reset block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.9 Schematic of the asynchronous counters inside the Reset block. . . . . . . . . . . . 34

3.10 Enable block schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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3.11 Enable block input and output waveform signals. The charging process of the P-wellis finished even though the P-comparator is not active. . . . . . . . . . . . . . . . . 37

3.12 Dual-ramp oscillator schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.13 Schematic view of the power gating. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.14 Simplified schematic of the non-overlapping circuit. . . . . . . . . . . . . . . . . . . 39

3.15 Output voltages of the two-phase non-overlapping circuit. . . . . . . . . . . . . . . 39

3.16 Simplified waveforms of the outputs of the level-shifters for phase A. . . . . . . . . 40

3.17 Phase-Detector schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.18 Alternative version of the non-overlapping block schematic. Fixed-delay non-overlappingcircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.19 Phase-Control block input/output waveforms. . . . . . . . . . . . . . . . . . . . . . 42

3.20 Phase-Control block simplified schematic. . . . . . . . . . . . . . . . . . . . . . . . 42

3.21 Phase-Control block schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.22 Signals ’x’ and ’cpwn’ from the phase-control block for the input signals θ1, θ2, ’sp’and ’sn’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.23 Level-shifters schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.24 Op-phase level-shifters inputs and outputs. . . . . . . . . . . . . . . . . . . . . . . 47

3.25 On-phase level-shifters inputs and outputs. . . . . . . . . . . . . . . . . . . . . . . 47

3.26 Simplified schematic of the SCPC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.27 Schematic of the SCPC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.28 Cross section of a NMOS transistor placed in an isolated P-well. . . . . . . . . . . 49

3.29 Layout view of the RBB switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.30 N-well and P-well output waveforms of the RBB generator. . . . . . . . . . . . . . 51

3.31 RBB generator efficiency for different capacitor types. . . . . . . . . . . . . . . . . 51

3.32 Gate-leakage current for a PMOS and NMOS capacitors as function of the voltageacross them. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.33 RESR versus W/L ratio for a thin-oxide PMOS capacitor. . . . . . . . . . . . . . . 54

3.34 Detailed view of the fringe capacitor layout. a) Layout view with the Metal3 layerdisabled. b) Layout view with the Metal3 layer enabled. c) Cross-sectional view ofthe fringe capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.35 Capacitive coupling between the channel of the PMOS capacitor and Vnw. . . . . . 56

3.36 N-well ripple noise voltage waveforms. From top to bottom the signals are a detailof the N-well and P-well outputs, and the phase-control outputs; phase A, phase Nand phase P respectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.37 Layout of the RBB generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.1 Control logic current consumption of the RBB generator. . . . . . . . . . . . . . . 61

4.2 Bottom plate capacitance for a PMOS capacitor with its body tied at 1.9 V. Vcpis the voltage of the positive plate and Vcm the voltage at the negative plate of thecapacitor. The capacitance (in Farads) is represented in the Z-axis. . . . . . . . . . 63

4.3 Simplified output waveforms of the SCPC. . . . . . . . . . . . . . . . . . . . . . . . 63

4.4 SCPC with a bottom plate parasitic capacitor for phases AP. . . . . . . . . . . . . 65

4.5 SCPC efficiency versus P-well voltage for different bottom plate parasitics. . . . . . 66

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4.6 SCPC with a bottom plate parasitic capacitor for phases AN. . . . . . . . . . . . . 66

4.7 SCPC efficiency versus N-well voltage for different bottom plate parasitics. . . . . 67

4.8 P-well output voltage for different corners, supply voltages and temperatures. Everygroup of symbols corresponds to the different process corners. . . . . . . . . . . . . 70

4.9 N-well output voltage for different corners, supply voltages and temperatures. . . . 70

4.10 Output currents of the RBB generator for the different corners and temperatures. . 71

4.11 Input currents for different corners, supply voltages and temperatures. . . . . . . . 71

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List of Tables

2.1 Power consumption of the previous RBB. . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 D-type flip-flop truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2 Counter output table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3 Phase-Detector truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4 Phase-Control block states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5 SCPC switch types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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Resum del Projecte

La polaritzacio inversa del substrat es una tecnica emprada per a reduir el corrent de fuges delscircuits digitals. Per tal d’emprar aquesta tecnica s’ha dissenyat un polaritzador de substrat. Elpolaritzador de substrat s’ha dissenyat amb tecnologia CMOS de 90 nm i s’ha implementat amb unconvertidor capacitiu commutat de dues sortides. L’objectiu principal del disseny es que l’area i elconsum de potencia siguin mınims. Les sortides del convertidor capacitiu s’empren per generar -1V per al pou P i 1.86 V per al pou N d’un circuit digital. Aquest treball esta basat en un dissenyprevi on el re-disseny del polaritzador de substrat empra un condensador per generar ambduessortides. El llac de control proporciona robustesa enfront de variacions de proces i temperatura ala vegada que es mante un consum mınim de potencia per a una carrega nominal.

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Resumen del Proyecto

La polarizacion inversa del sustrato es una tecnica utilizada para reducir la corriente de fugasde los circuitos digitales. Para utilizar esta tecnica se ha disenado un polarizador de sustrato. Elpolarizador de sustrato se ha disenado con tecnologıa CMOS de 90 nm y se ha implementadocon un convertidor capacitivo conmutado de dos salidas. El objetivo principal del diseno es que elarea y el consumo de potencia sean mınimos. Las salidas del convertidor capacitivo se utilizan paragenerar -1 V para el pozo P y 1.86 V para el pozo N de un circuito digital. Este trabajo esta basadoen un diseno previo donde el re-diseno del polarizador de sustrato emplea un condensador paragenerar ambas salidas. El lazo de control proporciona robustez frente a variaciones de proceso ytemperatura a la vez que se mantiene un consumo mınimo de potencia para una carga nominal.

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Abstract

Reverse-Body-Bias (RBB) is a well known silicon tuning technique for leakage reduction of digitalcircuits. As a key enabler of the technique, a RBB voltage generator is designed. The RBBgenerator is designed in a CMOS 90 nm technology and is implemented using a dual outputswitched-capacitor power converter (SCPC). Besides low area occupancy, the RBB generator aimsto an ultra-low power consumption as a crucial design feature. The outputs of the SCPC are usedto generate -1 V for the P-well and 1.86 V for the N-well of a digital circuit. The work builds onan already existing design. The improved RBB generator uses a single capacitor to generate bothoutputs. A control loop provides robustness in front of process and temperature variations whilstkeeping minimum power consumption at nominal specification.

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Chapter 1

Introduction

1.1 Leakage Reduction

Due to the shrinking process of CMOS technology and the consequent increase of functionalitythe leakage currents have been increased. There are different types of leakage in a CMOS circuitand different techniques to reduce it [3]. This project focuses on the reduction of the subthresholdleakage through the channel of a MOS transistor in its Off state. This leakage occurs between thedrain and source of a MOSFET device when Vgs has exceeded the weak inversion point but is stillbelow the threshold voltage. In this regime the transistor behaves similarly to a bipolar device andthe subthreshold current is strongly dependent on Vgs. The substhreshold current [4] is defined as:

Isubthreshold = keVgs−Vth

nVT [1− e−VdsVT ] (1.1)

(1.2)

where k is a function of technology, Vth is the threshold voltage, VT is the thermal voltage, Vds andVgs are the drain-to-source and gate-to-source voltages respectively. Observing the subthresholdcurrent formula it is clear that if the threshold voltage is increased the subthreshold current isdecreased exponentially. Therefore, one way of reducing the leakage is increasing the thresholdvoltage of the MOS transistors.

The threshold voltage can be modified because of the body effect. As mentioned in [5] the bodypotential has an influence over the channel. The same way the gate voltage is capacitively coupledto the channel through the gate-oxide capacitance, the body is capacitively coupled to the channelthrough the junction capacitance between the channel and the body. Therefore, the channel can bemodified changing the body voltage. This is called the body effect and is modelled as an increasein the threshold voltage given by:

Vth = Vth0 + γ(√Vsb + |2φF | −

√|2φF |) (1.3)

where Vth0 is the threshold voltage with zero source-to-body voltage, Vsb is the source-to-bodyvoltage, φF is the Fermi potential of the body and γ is the body-effect constant which has unitsof√V . The body-effect constant is given by:

γ =2qNAεsCox

(1.4)

where q is the electron charge, NA is the doping concentration, εs is the permittivity of the siliconand Cox is the oxide capacitance. Therefore, depending on the type of well and hence the doping

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Figure 1.1: Voltage doubler schematic.

concentration and the oxide capacitance, the body-effect might differ from one transistor to anotherbecause of process variations.

In conclusion, the leakage current can be reduced increasing the threshold voltage and hence,the threshold voltage can be increased reverse-biasing the body. The body voltage needs to behigher than the source voltage for a PMOS device and lower than the source voltage for an NMOStransistor in order to reverse-bias the body. A Reverse-Body-Bias (RBB) generator is a circuit usedto increase the threshold voltage and hence to reduce the leakage power consumption of CMOScircuits.

The RBB generator is a power converter that generates two voltages, one for the P-well and theother for the N-well. This voltages need to be higher than Vdd (for the N-well) and smaller than0 V (for the P-well) in order to reverse-bias the body of the MOS transistors in CMOS circuits.The RBB described in this report is an improvement of a previous design [2]. The improved RBBgenerator is based in a switched-capacitor power converter (SCPC) in order to generate the desiredoutput voltages for the reverse-body-biasing.

The SCPC is used as a substitute of an inductor based converter. On-chip inductors are bulky andnot suitable for low-power converters because of its parasitic losses. A switched-capacitor converteris used because it allows to boost and invert a voltage beyond the power supply at higher efficienciesthan inductor-based converters [1].

1.2 Basic Theory of Switched-Capacitor Power Converters

In order to understand how a switched-capacitor power converter (SCPC) works, a voltage doubler,depicted in figure 1.1, is explained as an example. This voltage doubler has two phases; A andN according to a clock signal. During phase A the flying capacitor is connected across the inputvoltage and hence it is charged at Vdd. The equivalent circuit is the same as the one showed atthe bottom left of the figure. Then, during phase N, the flying capacitor is connected between theinput and output voltage as shown in the bottom right part of figure 1.1. Since the flying capacitoris charged at Vdd the voltage at the output is the addition of the input voltage plus the voltageacross the capacitor. Therefore, the output voltage is 2Vdd and hence this circuit acts as a voltagedoubler.

In order to analyze and design switched-capacitor converters, an ideal model can be used to simplifythe analysis. The ideal SCPC can be seen as an ideal transformer with a certain conversion ratioand output resistance as depicted in figure 1.2. The conversion ratio of the ideal transformer alongwith the output impedance and output current determine the voltage at the output. Te equivalentoutput impedance Rout is consequence of charging and discharging the floating capacitors for finitetime slots via the resistances of the circuit. In this general case, the output voltage and inputcurrent given an specific load current (Iout) are:

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Figure 1.2: Ideal model of the SCPC.

Iin =n

mIout (1.5)

Vout =n

mVin − IoutRout (1.6)

From these expressions two issues arise. First, the conversion ratio determines the maximumefficiency of the ideal converter. Second, as opposite as in inductor-based converters, the rangeof possible output voltages depends on the conversion ratio of the transformer together with thevoltage drop across Rout due to the output current. Thus, to obtain a different output voltage thatis not possible to achieve through the conversion ratio of the transformer the output impedanceneeds to be adjusted. As seen in equation 1.6, if the output impedance is zero the output voltageis determined by the conversion ratio of the transformer, otherwise, if a different output voltageis requested it is possible to change the output impedance to obtain the desired output. In thelater case the voltage conversion is no longer 100 % efficient since the desired voltage is obtainedcreating a voltage drop at the output impedance. In that case the voltage conversion is equivalentto using and ideal SCPC cascaded to a linear voltage regulator.

The output impedance of an SCPC is related to the switching frequency of the converter and thesize of the capacitor and switches. The output impedance is also related to the output voltage andcurrent. Since the flying capacitor is the main component inside the converter, changing the ratioV over I of the flying capacitor is equivalent to changing the impedance of the flying capacitorand hence the output impedance of the converter. Modifying the equivalent output impedancecan be accomplished through the time constants of the circuit; i.e. On-resistance of the switches,capacitor size and switching frequency.

In reference [1] is possible to find the derivation of the output impedance of an ideal SCPC.Depending on the topology of the converter, the computation of the exact output impedance maybe difficult or impossible, therefore, it is common to use an approximation for design purposes.The results of this approximation are the following:

Rout ≈√R2SSL +R2

FSL (1.7)

RSSL =m

fsC(1.8)

RFSL = pRon (1.9)

Where RSSL is the slow-switching limit impedance, RFSL is the fast-switching limit impedance, fsis the switching frequency, C is the capacitance of the flying capacitor, Ron is the On-resistance ofthe switches and p and m are constants that depend on the topology of the converter. Figure 1.3shows the total output impedance for a particular converter. In this figure, the On-resistance andcapacitance are set to one but the results are representative for any switched-capacitor converter.

From the results of the approximation 1.7 it is concluded that the output impedance is relatedto the sum of the fast-switching limit and the slow-switching limit impedance. The fast-switchinglimit depends on the On-resistance of the switches. When the converter is working on this limit itmeans that the voltage across the flying capacitor does not change. As seen in figure 1.3, the output

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Figure 1.3: Total output impedance approximation.Image reproduced from [1].

impedance at the fast-switching limit is constant, therefore, the V over I ratio of the capacitor isalso constant and hence the voltage across the flying capacitor does not change. The reason for itis that the switching frequency is high enough so the flying capacitor does not have time enoughto get charged or discharged.

Since the flying capacitor voltage is constant, if the switching frequency is increased the outputimpedance remains the same as seen in figure 1.3. On the other hand, when the converter operatesin the slow-switching limit, the flying capacitor has enough time to get completely charged anddischarged. In that case, if the switching frequency is increased the output impedance is reduceduntil the impedance is dominated again by the fast-switching limit. In the slow-switching limit theoutput impedance is dominated by switching frequency and the flying capacitor size.

In principle, the desired operation point of the converter is obtained when RFSL = RSSL. That isbecause the output impedance is set to the minimum for the lowest possible switching frequency,which represents a good compromise between efficiency and output power capability. If the designis capacitor constrained, it might be better to choose RSSL > RFSL. In that case the capacitor andthe switching frequency can be made smaller but the switches need to be bigger in order to reducethe Ron resistance. On the other hand, if the design is switched constrained, it could be better tochoose RSSL < RFSL, that means that the switches would be smaller, with a higher On-resistance,but the capacitor and frequency should be higher to obtain the same output impedance.

1.2.1 Ideal Efficiency of the SCPC

The efficiency formula for a SCPC can be derived from the transformer model of the switched-capacitor seen in figure 1.2. The transformer ratio is m:n but for simplicity it is assumed thatm = 1. The output voltage and output current of a transformer is related to the input as:

Vout = nVin (1.10)

Iout =Iinn

(1.11)

Using equation 1.11 in the general formula for the efficiency results in:

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η =PoPin

=VoIoVinIin

=VoIin/n

VinIin(1.12)

η =VonVin

(1.13)

where n is the ideal conversion ratio of the converter. To summarize, the input current for aparticular output current and the efficiency of a SCPC is:

Iin = nIo (1.14)

η =VonVin

(1.15)

This efficiency formula is similar to the efficiency formula of a linear regulator or a low-dropoutregulator (LDO). If n = 1, the results are the same. Therefore, when the output is different thann · Vin the results are exactly the same as the ones obtained by an LDO. This is consistent withthe theory of the SCPC. As mentioned before, the output regulation of the SCPC is done by theadjustment of the output impedance, the same way a linear regulator adjusts its output voltage.

The current that flows through the capacitors can be calculated knowing the derivative of thevoltage or the charge transferred by the flying capacitors. Since the charge delivered in each cycleis constant if the load is constant, the current formula through the capacitors of the SCPC can besimplified from dQ(t)/dt transforming the derivative into a division of increments. Therefore, thecurrent through the capacitor becomes:

∆Q = C∆VC (1.16)

IC =dQ(t)

dt=

∆Q

Ts= fsC∆VC (1.17)

Switched-Capacitor Losses

The ideal model of the SCPC and its equations are useful as a first iteration for a switched-capacitor converter design. In order to get realistic numbers for the efficiency and output powercapability, losses should be added to the ideal model. The main losses in a conventional SCPC arethe bottom-plate losses and the switching losses.

The bottom-plate losses are related to the parasitic capacitors formed inside the silicon chip. Theparasitic capacitors are formed by the PN junctions at the bottom of the MOS structures. Thiscapacitors are charged and discharged but most of the time the energy stored in them cannot be re-used. In standard CMOS technologies the capacitance of the bottom-plate capacitors lies between1 to 30 % of the total capacitance, depending on the technology of the capacitor. Typically, thebottom-plate losses are the dominant losses in a conventional design. As an example, in the caseof the voltage inverter presented in this work, having a 1 % of bottom-plate losses implies a 20 %reduction of the ideal efficiency as shown in section 4.2.2.

The switching losses are caused by the energy used to drive the switches. Since the switches areimplemented by MOS transistors it is necessary to charge and discharge the gate-capacitance ofthe MOS transistors in order to drive them. The switching losses are approximated by Ps =fsCgs∆V g

2, where fs is the switching frequency, Cgs is the gate-capacitance, and ∆V g is thevoltage drop at the gate-capacitor. The switching losses are important when the output current ishigh because the switches tend to have a considerable size and the switching frequency is increasedin order to be able to provide the requested output power.

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Figure 1.4: Multi-ratio converter regulationschematic example.

Figure 1.5: Hysteretic feedback loop scheme. Imagereproduced from [1].

In ultra-low-power SCPC the switching losses are not important in comparison to other type oflosses. Since the currents in a ultra-low-power converter are small by definition, the On-resistanceof the switches tends to be high and hence the area and gate capacitance of the switches might beirrelevant for ultra-low-power designs. In this work the switching current losses are smaller than 1nA.

1.2.2 Control Loop of the SCPC

Switched-capacitor power converters use discrete conversion ratios to transform the output voltagesince these are determined by the topology of the circuit. Nonetheless, it is also possible to regulatethe output of the SCPC adjusting its output impedance. In conclusion, the control loop can bedesigned to adjust the ideal conversion ratio (that is the case of multi-ratio SCPC), and to adjustthe output impedance through, for example, the switching frequency.

Figure 1.4 shows an example of a multi-ratio SCPC. The topology of this converter is not optimizedin order to simplify the example. The output of this converter in particular can be set to 2Vinand 3/2Vin from the same input configuration, that would allow to make a coarse regulation of theoutput between this two voltages or to regulate the output for different input voltages and keepa high efficiency for a wider range of Vin. Using different topologies with more conversion ratioswould also help the converter to obtain a finer regulation. Another possibility would be to drive aload which requests different output voltages. In that case the regulation of the output is done bychanging the conversion ratio of the SCPC.

For a given output voltage different approaches can be taken. For example, assuming the requestedoutput voltage is 1.5Vin, the first possibility is using a 3/2 conversion ratio SCPC. However, thefinite value of Rout would prevent the converter of reaching 1.5Vin, in practice. Another possibilitywould be using a voltage doubler and change the output impedance to get the desired output.Area, output ripple and efficiency should be considered in order to choose between the differentalternatives.

A typical control loop used to modulate the output impedance is the hysteretic feedback. By this

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Figure 1.6: Ideal N-well output voltage ripple.

control loop the output voltage is fixed between a certain ∆V around a fixed voltage reference asdepicted in figure 1.5. The oscillator of this SCPC is enabled depending on the output voltage.

The control loop of the improved RBB generator uses a very similar approach. The control schemeuses a lower-bound hysteretic control-loop. The oscillator of the SCPC is activated when the outputvoltage is lower than the reference. Then, the oscillator is kept active for a fixed amount of timeinstead of deactivating the oscillator when it reaches the higher-bound. The fixed time that theoscillator is active defines the hysteresis of the control loop. During this time the output capacitoris charged and the output voltage reaches its maximum value. Using a lower-bound hystereticcontrol makes the circuit simpler and reduces the power consumption of the control logic.

The control loop used to regulate the output voltage affects the output ripple and the powerconsumption of the SCPC. The RBB generator control loop defines the minimum voltage level ofthe output waveform and the ripple (consequence of the fixed amount of time that the oscillatoris enabled) defines the maximum output voltage as seen in figure 1.6. Due to this operation, theaverage voltage of the well is slightly higher than the one defined in the comparator because of theripple. Therefore, the selection of the converter regulation method is important since it affects theefficiency, the area and the output ripple.

1.3 General Considerations of the RBB Generator Design

The RBB generator provides the N-well and the P-well of a digital circuit with voltages higherthan Vdd and lower than ground, respectively. The design will be implemented in a 90 nm CMOSprocess (1.8 V), that provides triple-well and 3.3 V thick-oxide devices. Some nodes inside the RBBwill have to withstand higher voltages than Vdd, therefore, thick-oxide transistors are requested.

The RBB generator needs to perform correctly across different process variations and temperatures.For this design, the range of temperatures goes from −40C to 125C. Moreover, the behavior ofthe RBB generator needs to be checked under extreme process variations; fastN-fastP, fastN-slowP,slowN-fastP and slowN-slowP.

1.3.1 Contributions

For the design of the improved RBB generator it is expected to re-use as many blocks as possiblefrom the previous design. Since some blocks are already designed and tested on silicon, it isan advantage to re-use them in order to simplify the design process and have their performanceguaranteed.

The blocks used in the improved RBB generator are depicted in figure 2.5. The oscillator, thelevel-shifters and the comparator of the P-well output are re-used without any modifications. TheN-comparator uses the same topology as the P-comparator except for the sampling of the outputvoltage and some additional logic for the reset signals. The structure of the reset block is alsore-used, some of its logic is replicated in order to generate a reset signal for the N-comparator.The enable block, the non-overlapping and the phase-control block are designed from scratch alongwith the switched-capacitor converter itself.

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1.4 State of the Art

Apart from the previous design [2] in which this project is based on, other RBB generators havebeen reported. An area effective forward/reverse body bias [6] which has a similar load current thanthis design is presented in the literature. This body-bias generator is smaller than this work butit has a very low efficiency. Other ultra-low power converters ([7],[8]) have a better efficiency butthey overcome the losses using MiM capacitors which have less bottom plate parasitics even-thoughthey occupy more area. In [7], an efficiency of 63 % at 100 nW is claimed.

In order to exemplify the importance of the bottom-plate losses for state of the art designs acalculation example of the efficiency is shown. This example assumes the bottom-plate losses arethe same as the flying capacitor losses of this work. According to the topology presented in [7] andassuming a certain amount of bottom plate losses the maximum efficiency would be:

Vin = 1 V (1.18)

Vo = 0.4 V (1.19)

η|α=0.07 =2(Vin/2− Vo)

(Vin/2− Vo) + αVin/2= 60% (1.20)

η|α=0.01 =2(Vin/2− Vo)

(Vin/2− Vo) + αVin/2= 76% (1.21)

It is clear that it is possible to obtain a 63 % efficiency converter only if the bottom plate losses arelow enough. Having a 7 % of bottom plate losses, like in this RBB generator design, would makeit impossible to have an efficiency of 63 % since the maximum efficiency for this SCPC having thislosses is 60 %. If 1 % of bottom plate capacitance is assumed the maximum efficiency raises to 76%; in that case is possible to obtain a final efficiency of 63 %. Therefore, the reduction of bottomplate losses is crucial to obtain good efficiency results. Most of the new SCPC designs tend to usebetter types of capacitors in order to reduce the bottom plate losses. For example, a SCPC witha 93 % efficiency is presented in [9], the possibility to achieve such a high efficiency is thanks tothe use of better capacitors. In this 93 % SCPC ferroelectric capacitors are used to circumvent thebottom plate losses.

1.5 Structure of the Report

This report is structured as follows. In chapter 2 the previous RBB design is explained to givean starting point for the re-design process. Then, the proposed new architecture is presented.Chapter 3 describes the microelectronic implementation of the improved RBB generator. Theblocks designed for the improved RBB are described in detail. Some comments are done aboutthe problems found designing the blocks and the proposed solutions. In chapter 4 the simulationresults are presented. The current consumption of the different blocks and an analysis with thequantification of the losses is discussed. Finally, a conclusion section with the main problems andresults encountered in the design and some proposals for improvements are presented.

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Chapter 2

Improvements on the PreviousDesign. Proposed Concept.

This work is a continuation of a previous RBB design [2]. The targeted RBB is intended to drivea digital circuit working at 0.7 V . The required reverse voltage lies between 0.9 and 1.2 Volts.It should be considered that the load current changes widely across temperature and processvariations up to three orders of magnitude, as seen in figure 2.2. However, the target specificationsfor this design focus on the nominal case. Therefore, the P-well requires a nominal voltage of-1 V and the N-well a voltage of 1.7 V as seen in figure 2.1. According to the wells currentcharacterization, given the size of the digital circuit, the load currents at 25C and nominal cornerare 100 nA and 10 nA for the P-well and N-well, respectively. The regulation or the RBB is quiterelaxed since it does not need to be accurate as long as the output voltage remains in the specifiedrange as seen in figure 2.1.

The previous RBB [2] implements a switched-capacitor power converter (SCPC) and a low-dropoutregulator (LDO) to get the desired voltages. The SCPC is used for the P-well to generate −1 Vand the LDO is used for the N-well to generate 1.7 V . The SCPC has an input voltage of 1.2 V andthe LDO has a 3.3 V input. Therefore, both converters use a step-down approach and the SCPCalso inverts the signal. The power consumption of the previous RBB at a nominal load is shownin table 2.1. From these results notice that the LDO is the most inefficient block and also needsa 3.3 V supply. The improved RBB does not use the LDO and instead uses a SCPC with dualoutput. Therefore the efficiency can be increased and the 3.3 V supply is not needed anymore.

Figure 2.3 illustrates the changes made to the RBB. As seen in the figure the LDO plus the SCPC isreplaced by a dual-output SCPC. The outputs of the new RBB are an inverting step-down outputto generate -1 V and a step-up output to generate 1.9 V. Notice that in comparison to the previousarchitecture, which only had step-down output voltages, this one has both step-up and step-down

LDO Vin 3.3 VLDO Iin 173 nALDO Vo 1.76 VLDO Io 10 nASCPC Vin 1.2 VSCPC Iin 162 nASCPC Vo −1.01 VSCPC Io 100 nAη 15.5%

Table 2.1: Power consumption of the previous RBB.

17


Figure 2.1: Digital leakage current reduction versusRBB voltage in CMOS 90nm. Image reproduced from[2].

Figure 2.2: Expected well currents for different cor-ners and temperatures. Image extracted from [2].

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Figure 2.3: Architectural modifications made to theRBB.

Figure 2.4: SCPC diagram.

outputs. Since the new SCPC is single-input and dual-output both output voltages are generatedfrom the same power supply, in this case 1.2 V.

This new approach has some advantages. As mentioned before it only needs one power supply, ituses approximately the same area and it has improved robustness and better efficiency. The areapreviously used for the LDO can now be used for the required control logic and hence there is norequirement for additional area. Regarding robustness, the hysteretic control loop of the SCPCprevent less sensitivity in front of parasitics and devices parameters changes than the linear controlloop of the LDO. Moreover, the SCPC is much more efficient than the LDO hence a better powerperformance is achieved. Assuming that both LDO and SCPC are ideal, the LDO needs a 1.6 Vdrop (Vin − Vo = 3.3 − 1.7) to obtain the desired output and the SCPC only needs a 0.7 V drop(2Vdd − Vo = 2 · 1.2− 1.7). Besides, the LDO needs a bias current higher than its nominal output(10 nA) to perform appropriately in all process and temperature corners which reduces the overallefficiency.

2.1 Previous Switched-Capacitor Power Converter.

The diagram of the previous switched-capacitor power converter used to generate -1 V is shownin figure 2.4. The behavior of the converter is based on the activation of the clock signal. TheSCPC is operating when the clock signal is active and remains idle otherwise. As a result, theconverter has a duty-cycled activity and hence the SCPC is activated depending on the power

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needs. Because of this duty-cycled activity the power consumption is proportional to the outputcurrent. Therefore, if the load current is low, the activity is reduced and if the load current ishigh the activity is increased for a wide range of output power. Consequently, the efficiency ismaintained for a wide range of output current. Otherwise, if the activity of the SCPC was notdependent on the output current it should have been designed for the worst case scenario havinga penalty for lower loads and reducing the efficiency for a wide range of output current includingthe nominal specification point. To summarize, in order to keep a constant efficiency for a widerange of output current, the activation of the SCPC is based on a clock signal to make the SCPCactivity proportional to the output current.

As mentioned before the activity of the SCPC is based on the clock signal. In turn, the activationof the clock signal depends on the output voltage. The output, in this case the P-well voltage,is compared to a reference. Depending on the result of this comparison the clock generator isactivated or not. When the comparator is triggered its output is used to enable the oscillator.This way, the consumption of the oscillator is also kept proportional to the amount of outputcurrent.

Finally, the oscillator drives a non-overlapping two-phase clock. The non-overlapping clock is usedto avoid the cross-conduction of the switches of the converter. The switches of the SCPC aredriven by the non-overlapping clock which goes through the level-shifters and finally the switchesplus the flying capacitor generate the desired voltage.

The comparator of the SCPC, shown in figure 2.4, is used to compare the output with a referencevoltage. Since the comparator needs to be low-power, the use of an internal reference voltageis not desirable because of its power consumption. The comparator used in the SCPC is aninverter-based comparator and uses the power supply as a voltage reference in order to reducethe current consumption as explained in section 3.1. The voltage reference of the comparatoris obtained subtracting the switching-point of the inverter used as a comparator from the powersupply voltage. This reference voltage is stored in a capacitor. In order to avoid the dischargeof this capacitor, otherwise the reference voltage would be corrupted, a reset signal is need it torefresh this capacitor periodically.

The reset block shown in figure 2.4 is used to refresh the capacitor of the comparator. The reset isactivated during four clock periods and it is triggered by two events. When the system is poweredup and after the comparator triggers. In continuous operation the load is very high and theSCPC cannot drive the output below −1 V hence the comparator is always active. Therefore, thecomparator needs to be refreshed periodically, otherwise, in continuous operation the comparatorwould get deactivated if the reference voltage gets discharged. For that reason, in continuousoperation the reset signal is generated every 32 clock periods. The reset signal is generated usinga supply detector circuit when the supply voltage raises and it is also generated using a binarycounter both after the comparator triggers and in continuous operation as explained in section 3.2.

It should be noticed that the activation of the SCPC depends on the result of a comparison. If thethreshold for the comparator is −1 V and there is no hysteresis, the comparator will be switchingOn and Off all the time around −1 V increasing the switching losses. Therefore, some amount ofhisteresys is need it for the comparator. In this case the hysteresis is inherent in the design. Thehysteresis is given by the delay of the comparator and the delay introduced by the reset signal.

The reset block generates a delay because it forces the comparator to stay active for at leastfour periods of the clock signal. Therefore, the output is overcharged a little creating an extra∆V at the output. This extra ∆V gives some time to the output to get discharged again to thereference. This extra time the output is discharged is more than enough to get some hysteresis.The comparator will not trigger again until the well has discharged to the reference and hence theoutput of the comparator will not switch continuously.

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Figure 2.5: Improved SCPC diagram.

Figure 2.6: The dual-output SCPC. At the right sidethe equivalent circuit for each phase is depicted.

2.2 Improved RBB Generator.

The improved version of the RBB generator is shown in figure 2.5. The improved RBB generatorworks in a very similar way to the previous one. In this case the converter also works basedon the comparator output. When one or both outputs are out of the specified operating pointthe comparator triggers. This activates the oscillator which drives the non-overlapping clock andfinally the switches.

The main difference in this case is that the converter has two outputs and one flying capacitor,avoiding the need for an LDO to supply the N-well. Thus, it needs to decide which output needsto be driven. Since there are two outputs there are also two comparators to monitor the outputvoltages. The outputs of the comparators are used to enable the oscillator. Since there are twocomparator signals, an ”enable” block is used to enable the oscillator no matter which comparatoris triggered. In order to decide which output needs to be charged the phase-control block is used.Depending on the comparator outputs the phase-control block generates the adequate set of signalsto sent power to one output or the other. In order to understand which signals need to be generated,a better understanding of the SCPC is need it.

Figure 2.6 shows the switched-capacitor power converter. When the switches of phase A, Oa1 andOa2, are activated the capacitor is charged to Vdd. Then, if the switches of phase P, Op1 and Op2,are activated the voltage at the P-well is ideally -Vdd since the flying capacitor was previouslycharged at Vdd. On the other hand, when the N-phase is active, switches On1 and On2, the

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Figure 2.7: Example of the phase-control block out-put signals. From top to bottom the signals are theoutput of phase A, phase N and phase P, respectively.

N-well is ideally at 2Vdd. Therefore, when both outputs need to be charged the phase sequenceis ANAPANAPA... which means that the capacitor is charged to Vdd, then its discharged to theP-well, then its charged again to Vdd and finally is discharged at the N-well. In case that only oneoutput needs to be charged the phase sequence would be APAPA... for the P-well and ANANA...for the N-well. Figure 2.7 shows the signals generated by the phase-control block for a particularcase as an example. In this particular case both comparators are active (signals sn and sp areactive high), which results in the sequence ANAPANAPA..., as mentioned above.

Some of the signals used in the RBB generator are shown in figure 2.8 as an example. The first andsecond waveforms from the top are the voltages at the N-well and the P-well, the third row showsthe outputs of the comparators, the fourth row shows the outputs of the reset blocks and finally thelast row shows the output of the oscillator. When the comparator output goes high the oscillatoris enabled. At the same time the reset signal is also set high in order to refresh the comparatorreference. When the oscillator becomes active the P-well is charged as seen in figure 2.8. Whenthe P-well is charged the comparator toggles to ground and the charging process of the P-well isstopped. In this particular example the N-well comparator is triggered while the P-comparator isstill active as seen in the figure. In the same way the output of the N-comparator activates theN-reset signal. As seen in figure 2.8 the reset goes high at the next raising edge of the clock afterthe N-comparator its triggered. At the same time the N-well is charged-up until the comparatoris deactivated. Once both comparators are deactivated the oscillator is turned-Off to save power.

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Figure 2.8: Detail of the RBB signals. From top tobottom the signals are the N-well and P-well outputs,the outputs of the N and P-comparator, the resetsignals for the N and P-comparators and the oscillatoroutput.

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Chapter 3

Detailed Description of theMicroelectronic Implementation.

In this chapter, the building blocks of the RBB generator are explained. The blocks are explainedin the same order as they appear in the control loop. The first block is the voltage comparator,then the reset, the enable block, the oscillator, the non-overlapping, the phase-control block, thelevel-shifters and finally the switched-capacitor. Since some of the blocks are re-used from theprevious design they will be only briefly explained. At the end, the layout of the RBB generatoris showed and described.

3.1 Voltage Comparator

Both voltage comparators are very similar, therefore, only the P-well comparator is explainedin detail to show what is common for both comparators. After that, the particularities of eachcomparator are discussed.

The P-well comparator is a continuous time comparator and it is active low, the schematic isdepicted in figure 3.1. This circuit is re-used from the previous design. At the initial state of thesystem it is assumed that all capacitances are at 0 V and the value of the reset signal is also 0 V.The reset signal is used to refresh the signal stored across the capacitor

Just after the raise on the 1.2 V supply a reset pulse is generated (reset = 1). Because of the resetsignal the output of the comparator is activated as we can see at the schematic. Therefore, everytime the reset is activated the comparator is also active to keep the power conversion during thereset phase. In addition, at the reset phase the input and output of the inverter are short-circuited,hence, the capacitor CA has a potential of VSP − VGND; where VSP is the switching-point of theinverter. This capacitor is used to store periodically the ground reference and the switching pointof the inverter so the result of the comparison is not affected by changes in temperature and process

Figure 3.1: P-well comparator schematic.

25


Figure 3.2: P-well comparator transfer function afteradding an input capacitor.

variations.

After the reset pulse, the capacitor is connected to the voltage divider VA. Now, because thecapacitor holds the switching-point potential and the ground reference, if VA is higher than theground reference the inverter will switch to ground since its input will be at VA + VSP − VGNDwhich is higher than VSP . Therefore, the output of the comparator will be:

VA > 0⇒ Vout = 0 (3.1)

VA < 0⇒ Vout = 1 (3.2)

In order to clarify how the comparator works figure 3.2 shows the difference between an inverter-based comparator without and with an input capacitor. The transfer function without inputcapacitor is at the left side while the transfer function with an input capacitor is shown at theright part of the figure. Adding an input capacitor shifts the switching-point of the inverter-basedcomparator. Since the capacitor is charged at VSP − VGND, the switching-point of the inverterbecomes 0 V, which is the reference of the P-well comparator.

Therefore, in normal operation the comparator is triggered when Vpw = −1 V (VA is 0 V), then,the reset is activated and the capacitor is refreshed. When the comparator switches back to VAafter the reset phase, Vin is slightly smaller than −1 V (for example -1.04 V) because it has beencharged during the reset phase (actually, this action is the main contribution to the hysteresis ofthe controller), therefore, VA is also slightly smaller than zero and hence the inverter input can beconsidered a zero and the output a one. As a consequence the comparator remains inactive. Thecomparator will trigger again when Vpw will be higher than −1 V .

3.1.1 P-Well Comparator

P-Well Comparator Voltage Divider

One of the differences between the comparators is the voltage divider. For the P-comparator atwo-resistor voltage divider between Vdd and Vpw is used as seen in figure 3.1. The resistors areimplemented as MOSFETs in diode configuration. The upper resistor is defined as R1 and thebottom resistor as R2. The desired ratio for the transistors is the one that makes VA = 0 whenVpw = −1 V. The ratio is calculated using the voltage divider equation, to simplify the calculationsall nodes are raised one volt in order to have a zero volts reference.

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Figure 3.3: P-well output voltage in case the P-comparator capacitor is discharged.

Vpwell = 0 V, VA = 1 V, Vdd = 2.2 V (3.3)

VA = (Vdd − Vpw)R2

R2 +R1(3.4)

R1

R2=Vdd − Vpw − VA

VA(3.5)

If VA = 1→ R1

R2= 1.2 (3.6)

Two P-MOS transistors in a diode configuration are used to make the voltage divider. Sincethe transistors will have to be rather large to reduce the current through the voltage divider, P-MOS transistors are used because of its high resistivity. Using the same width and applying thesaturation formulas for both transistors leads to:

Ids1 = Ids2 (3.7)

kPW (Vdd − VA − Vtp)2

2L1=kPW (VA − Vpw − Vtp)2

2L2(3.8)

L2

L1=

(VA − Vpw − Vtp)2

(Vdd − VA − Vtp)2(3.9)

VA = 0, Vtp = 0.53, Vdd = 1.2, Vpw = −1 (3.10)

L2

L1≈ 0.5 (3.11)

As seen in figure 3.1, this is the aspect ratio used in the previous design, W1/L1 = 0.5/400 andW2/L2 = 0.5/199. Since the aspect ratio is rather small, the reference voltage is slightly affectedby process variations. However, the application is tolerant to small variations in the wells voltages.

Potential Causes of Failure of the P-comparator

One potential problem of this comparator is the discharge of the input capacitor due to the leakagecurrent, CA, shown in figure 3.1. If the voltage across CA decreases, the input VA will have to behigher to switch the inverter. For example, if the voltage across the capacitor is decreased by Vdthe inverter will switch when the input is VA > Vd. At the end, if the capacitor is not refreshed

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Figure 3.4: N-well comparator schematic.

and gets fully discharged, the input will need to be VA > VSP to switch the inverter. ApplyingOhm’s law to the voltage divider of the P-comparator shows that the comparator will trigger whenthe voltage at the P-well is:

VA = VSP = Vdd − IrefP ·R1 (3.12)

IrefP =Vdd − VpwR1 +R2

(3.13)

Vpw ≈ 0.03 V (3.14)

this result is obtained isolating Vpw from equation 3.13, where IrefP is the current through thevoltage divider.

In this case, since the reference voltage is the switching-point of the inverter (VSP ), around 0.554V, the comparator will trigger for an input voltage of approximately 0.03 V, as seen in figure 3.3.As a consequence, even if the P-comparator capacitor is completely discharged, the RBB generatorwill reset itself refreshing the reference again. Furthermore, from the previous design it is knownthat this problem does not happen because the leakage of the capacitor is low enough and henceit never gets completely discharged. To summarize, the discharge of the P-comparator capacitordoes not imply any risk for the system and if it happens the RBB generator is reset again so itwill never get locked.

Figure 3.3 shows that the output of the converter has a positive increase when its discharged sinceit grows toward ground. The reference of the comparator also has a positive increase when theP-comparator capacitor is discharged since it grows from 0 V to VSP . If the reference grows fasterthan the voltage of the well it is possible that the well gets completely discharged since the outputnever reaches the reference. For the system to work properly it must be assured that the outputgets discharged faster than CA. To avoid the discharge of the capacitor and hence the degradationof the reference voltage the capacitor must be refreshed.

Because of the P-comparator capacitor this converter needs a minimum load to work properly.This minimum load is imposed by the discharge rate of CA. As long as the load gets dischargedfaster than the reference the comparator works fine. This is the case for the output current rangeof the P-well as it has been verified by the previous RBB generator measurements and tests. Fromthe previous RBB generator specifications, for this work the minimum output current is set to 10nA for the P-well output and to 5 nA for the N-well output.

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3.1.2 N-Well Comparator

The N-well comparator has the same topology than the P-well comparator. The schematic isshown in figure 3.4. The capacitor stores the difference between the switching point of the inverterand the supply voltage, VCA

= Vdd − VSP , having now Vdd as a reference voltage. Looking at theschematic, the output of the comparator will be:

Vininv= VA − VCA

= VA + VSP − Vdd (3.15)

VA > Vdd ⇒ Vininv> VSP ⇒ Voutinv

= 0⇒ Vout = 1 (3.16)

VA < Vdd ⇒ Vininv< VSP ⇒ Voutinv

= 1⇒ Vout = 0 (3.17)

where Vininvis the input voltage of the inverter (after CA) and Voutinv

is its output. The comparatoris active when VA < Vdd, therefore, the comparator is active low. Since the voltage divider takes2/3 of the input the comparator will trigger when Vnw < 1.8 V.

In this case the comparator uses two reset signals, resetP and resetN. This is because the N-wellload is ten times lower than the load of the P-well at the nominal case. As mentioned in section3.1.1, the input capacitor of the comparator may get discharged faster than the well due to leakageif the load current is too low. Therefore, since it is known from the previous design that the P-wellcurrent is high enough to refresh the capacitor at an adequate rate, the resetP signal is used torefresh the capacitor of the N-comparator as well. That way it is assured that the capacitor of theN-comparator never gets discharged for all the range of output currents.

The P-well reset signal is enough to refresh the capacitor but the resetN signal is still needed.Every time the inverter toggles, some current flows from the input to the output of the inverterbecause of the capacitive coupling, therefore, some charge flows out of the input capacitor. If theinput capacitor gets discharged the reference voltage is degraded and the comparator won’t switchagain until a new reset signal arrives from the P-comparator. In some cases that would lead to adischarge of the N-well below of the reference voltage. In order to avoid that the resetN signal isalso used.

Since the resetP signal is enough to refresh the capacitor the resetN signal has a duration of only twoclock periods in comparison with the four clocks periods of the resetP pulse signal. The duration ofthe resetN pulse is reduced to minimize the power consumption. In the reset phase the comparatortakes more current than when it is in its idle state, mainly because the comparison inverter hasits input and output shorted and both transistors of the inverter are conducting. Reducing theduration of the resetN pulse helps to reduce the power consumption. A shorter resetN signal alsoreduces the ripple of Vnw, since the effective hysteresis is narrower.

Both comparators are designed to remain active when they receive a reset signal. That is becausethe reset signal is active because the comparator has been triggered and hence, if the reset isactivated the comparator should remain active as well. Therefore, at the reset phase it needs to beassured that the comparator is active. In order to do that the buffer after the comparator-inverterneeds to be properly designed. That is because in the reset phase, when the comparator-inverterhas its input and output shorted, the output of this inverter is around half the power supply,therefore the buffer needs to be designed to be active when its input is 1/2Vdd.

It should be noticed that the N-comparator should remain active only when the resetN signal isactive. Otherwise, if the comparator gets triggered every time it receives a reset from the resetPsignal the N-well will get overcharged. For that reason, some extra logic has been added to thecomparator in order to deactivate its output when the resetP signal is active. The added logic isseen in figure 3.4.

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N-Well Comparator Voltage Divider

The reference of the N-well comparator is intended to be 2/3 of Vnw to get an N-well voltage of1.8 V. The main difference in comparison with the LDO output of the previous design is that theLDO does not have ripple. Therefore, if the N-well switched-capacitor is designed to trigger at 1.8V, its output average output will be slightly higher because of the ripple of the switched-capacitor.

In principle it is possible to tune the reference voltage of the comparator the compensate for theextra output voltage the ripple introduces. Assuming a two-resistor voltage divider and repeatingthe same calculations for the N-comparator the results are:

VA = VnwR2

R2 +R1(3.18)

R1

R2=Vnw − VA

VA(3.19)

If VA = 1.2→ R1

R2= 0.5 (3.20)

Ids1 = Ids2 (3.21)

kPW (Vnw − VA − Vtp)2

2L1=kPW (VA − Vtp)2

2L2(3.22)

L2

L1=

(VA − Vtp)2

(Vnw − VA − Vtp)2(3.23)

VA = 1.2, Vtp = 0.53, Vnw = 1.8 (3.24)

L2

L1≈ 92 (3.25)

However, in this case the aspect ratio of the required transistors is very different in comparisonwith the aspect ratio of the P-well voltage divider. Having a very different aspect ratio causes toolarge changes in the reference for different process and temperature variations. Therefore, is notpossible to use two transistors as a voltage divider and it is also not possible to tune the referencevoltage using two transistors.

To solve this problem three MOSFETs with the same aspect ratio are used. Using three transistorsa 2/3 voltage divider is obtained. Since the three transistors are identical the voltage divider ismore robust in front of process and temperature variations. With a 2/3 voltage divider the outputvoltage will be slightly higher than the one imposed by the reference of the comparator becauseof the ripple of the output voltage. Nonetheless, the output in this case is 1.86 V, which is still inthe specified range.

Potential Causes of Failure of the N-comparator

If CA is discharged the comparator will be triggered when VA < VSP . Then, if the output isdischarged until it reaches Vdd, it needs to be assured that VA < VSP . Otherwise the comparatorwill never switch again. In this case, assuming VSP = 1/2Vdd and Vnw = Vdd, the comparator willtrigger when VA = 2/3 · Vdd = 0.8 V which does not satisfy the condition to toggle the comparator(VA < VSP = 0.6 V).

If the situation described above happened, the N-well would get discharged at 0.7 V, which is theexpected power supply of the digital core. Therefore, in that state the comparator will not recoverby itself as the P-comparator does. In that case the comparator would only start working again ifthe power supply of the RBB generator is reset.

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Figure 3.5: Schematic of the voltage divider of theN-comparator and simplified version of the layout.

Another issue that does not affect the P-comparator but affects the N-comparator is the forwardbiasing of PN junctions at the well. This would happen only when the N-well gets dischargedbelow 1.2 V (Vdd), when Vnw > Vdd the highest voltage is obviously Vnw but when Vnw < Vdd1d2the highest voltage is 1.2 V. If the N-well is not the highest voltage some PN junctions may getforward biased and the circuit would stop working. If this case is simulated, at some point theleakage through the PN junctions is equal to the load, which also decreases with the output voltage,and finally the N-well voltage stops decreasing when it reaches 1 V approximately. In the P-wellcircuitry the lowest potential is always Vpw but in the N-well comparator the highest potential isnot always Vnw, therefore, this problem does not affect the P-well output.

For this reason among others, both reset signals are used to refresh the input capacitor of theN-comparator. That way it is assured that the input capacitor of the N-comparator will never getdischarged and hence the problems mentioned above will never happen.

N-Comparator Voltage Divider Layout

Although the application does not require high accuracy, the layout of the voltage divider was madefollowing a common-centroid approach to reduce its mismatch. Figure 3.5 shows the schematicof the voltage divider and figure 3.6 shows the final layout. Each transistor is divided in twoand placed in a way that gradient related variations in the silicon affect each transistor by thesame amount. For example, if in the simplified layout version of figure 3.5 the left part is moreconductive than the right part, each transistor is compensated since it has been placed in a waythat half transistor is in the conductive side and the other half on the resistive side. Also, with thechosen layout, the current through the transistors flows in the same direction. The use of dummiesM52, M53 further reduces the mismatch.

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Figure 3.6: Layout of the voltage divider of the N-comparator.

Figure 3.7: Schematic alternatives for the N-comparator.

N-well Comparator Schematic Alternatives

The comparators of the RBB generator have a resistive voltage divider which is used to sample theoutput voltages. This voltage divider draws current continuously and it is an important fractionof the power consumed by the comparators. Figure 3.7 shows some of the alternatives that havebeen tried to reduce the power consumption of this voltage dividers. The transistors are connectedin diode configuration in order to use them as a reference. The idea is to design a comparator thatuses the threshold voltage of the transistors as a reference for the comparison.

Regarding the P-MOS transistors, if the source is connected to Vnw and the drain to Vdd or a lowervoltage, the transistor is conducting current when Vnw > Vdd+Vt ≈ 1.8 V. This is not desired sincein steady state the N-well output is higher than 1.8 V most of the time and hence the transistorwould draw current almost continuously the same way the resistive voltage divider does. On topof this, the Vt of a transistor is highly dependent on temperature and process variations.

On the other hand, if the N-well is connected to the drain a higher voltage is needed for the source.If the 3.3 V power supply was available it would be possible to use it but that is not the case. Itis also possible to use a voltage doubler to generate 2Vdd, but that has other disadvantages. First,the generation of a 2Vdd reference takes some power and the capacitor used to store it needs to berather large in order to be unaffected by the leakage. Since the voltage across the transistor is veryclose to its Vt, the leakage current through the transistor discharges the capacitor. At the end, thelosses, extra area and the added complexity to generate 2Vdd makes this solution not worthy.

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Figure 3.8: Reset block diagram.

D CP SD QNX X L LL R H HH R H LX F H QNX L H QNX H H QN

Table 3.1: D-type flip-flop truth table.

3.2 Reset Block

The main functionality of the reset block is to generate the signals used to refresh the inputcapacitor of the comparators. A simplified version of the schematic is depicted in figure 3.8. Asshown in the figure the reset block has two asynchronous counters and one supply detector. Thesupply detector is used to activate the reset signal every time the RBB generator is enabled. Thecounters are used to generate a reset when the comparators are triggered.

Since the RBB has two comparators it needs two counters to be able to generate two independentreset signals. The counter needs to be active only when its corresponding comparator is active.For that reason an AND gate is added as a clock enable, therefore, the counter will be active whenits comparator and the oscillator are also active as seen in figure 3.9.

As mentioned before, the reset is activated when the supply voltage raises and when the compara-tors outputs are activated. When the comparators are triggered they enable the counters whichgenerate the reset signals. If the P-comparator triggers, a reset pulse is generated with a durationof four clock periods. As mentioned in section 3.1.2, if the N-comparator triggers the durationof the pulse is 2 clock periods. When the comparator remains active due to higher output powerdemands the reset signal is generated every 32 clock periods. This behavior is easily seen analyzingthe asynchronous counter.

3.2.1 Asynchronous Counter

A detail of the counters is shown in figure 3.9. This counter has 5 bits and hence in continuousoperation goes from 31 to 0. This is a descending asynchronous counter made of D-type flip-flopswith active low preset and an inverting output. The truth table of the flip-flop used is depicted intable 3.1, it should be noticed that it has an inverting output.

The behaviour of the counter is as follows; when the enable signal arrives all flip-flops are set to’0’ thus the output of the counter is 0. The first flip-flop toggles to ’1’ when a rising edge of the

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Q4 Q3 Q2 Q1 Q00 0 0 0 01 1 1 1 11 1 1 1 01 1 1 0 11 1 1 0 0

1 1 0 1 1... ... ... ... ...

Table 3.2: Counter output table.

snr

clk

spr

clk

spr

snrcomN

comP

resetP

resetN

Supply

Detector

signal

Figure 3.9: Schematic of the asynchronous countersinside the Reset block.

clock arrives. Then, because of the first flip-flop the second one gets a raising edge in its CP input.Since the second flip-flop was set to ’0’, now it toggles to ’1’ in the same way the first flip-flopdid. The same happens for the rest of the flip-flops and at the end all flip-flops outputs are setto ’1’. Now the output of the counter is 31. When the next raising edge of the clock arrives tothe first flip-flop its output will toggle to ’0’ since its D input was ’1’. The remaining flip-flopswill not receive a raising edge in its CP input and hence they will store its QN value. Now theoutput of the counter is 30. Following the same reasoning one can conclude that the counter willdescend until it arrives to 0. At that time it will go back to 31 to repeat the counting again. Asmall sample of the counter output is depicted in table 3.2.

The P-comparator uses a reset signal of 4 clock periods to refresh the capacitor. To obtain thissignal the three most significant bits of the counter are multiplied using an AND gate as seen inthe schematic. For the N-comparator the four most significant bits are used since in this case thereset signal needs to be two periods long. The bits used from the counters are marked in table 3.2.As shown in the table; Q4, Q3, and Q2 are used to obtain a 4-period reset signal and Q4, Q3, Q2and Q1 are used to obtain a 2-period signal.

Since the output of the counter is not synchronous glitches may appear at its output. The differentoutput bits of the counter may arrive at a different instants at the AND gate creating glitches atits output. From the simulation results it is seen that the glitches are very short in duration anddo not affect the following logic gates. Furthermore, from the previous RBB test chip it was alsoverified that the glitches were not a problem. Therefore, this counters have been reused for theimproved RBB generator because its low-power consumption.

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3.3 Enable Block

The enable block is used to enable the oscillator of the RBB generator, which is active low. Theschematic is depicted in figure 3.10. The inputs of the enable block are the clock signal and theoutputs of both comparators. The enable output is low if one or both comparator outputs is active.

In order to understand the circuitry of the enable block, the initial experiments performed at thedesign phase with the RBB generator should be considered. During the first design iterations,different phase sequences for the SCPC were tried aiming for a power consumption reduction. Forexample, one of the phase sequences that was tested was the sequence APNAPNAPN... whichcould be used when both outputs need to be charged (the phase sequence used in the final designof the RBB generator when both comparators are active is shown in section 2.2). In principle, thesequence APNA... would reduce the voltage drop at the flying capacitor improving the efficiencybecause the output impedance would also get reduced, as explained in section 1.2. Unfortunately,this only improves the efficiency of the system when both outputs need to be charged, whichonly occurs when the output power is much higher than the nominal specification. Therefore,this solution does not improve the efficiency at the nominal load current and hence it was notimplemented. Apart from the APNA... sequence other sequences were tried but because of theadded complexity to the control logic, the efficiency at the nominal specification was decreased dueto the increased current consumption of the digital circuitry. Thus, this solution was discardedbearing in mind that the design goal was increasing the efficiency for the nominal load current.

To summarize, the enable block needed to allow the experimentation with different phase sequences.Despite the fact that these phase sequences were not implemented in the final design, the changesmade to the enable block were kept because of the added robustness to the system as explainedlater in this section.

Therefore, in order to add robustness to the system and allow for the experimentation with differentphase sequences, the duration of each phase is made equal or slightly higher than one clock period.That way, the design of the combinational and sequential logic circuits is simplified since all phasesequences are synchronized with the clock signal and it also adds robustness to the system since itavoids glitches at the outputs of the digital circuits.

If different phase sequences want to be tried it is also necessary to avoid undesirable transitions.For example, is possible to charge the P-well and then charge the N-well without re-charging thecapacitor to Vdd. To charge the P-well the flying capacitor needs a voltage greater than 1 V (−Vpw)and to charge the N-well the minimum voltage needed is Vnw − Vdd = 0.7 V. Since after chargingthe P-well the voltage across the capacitor is 1 V, there is still enough energy to charge the N-well but not the other way around. If the N-well is charged first, the voltage across the floatingcapacitor will be 0.7 V which is not enough for the 1 V required by the P-well. If this happens thevoltage at the P-well would raise instead of decrease. In order to be able to avoid these situations,the fact that the phase duration is equal to the clock period can be used as an advantage. As aconsequence, the design of the digital control logic is significantly simplified.

In order to set the duration of each phase equal to one clock period, two D-type flip-flops are addedto the enable block circuit. These flip-flops add a delay between one and two clock periods to theenable block output signal. Adding, at least, a one-period clock delay to the enable signal forcesthe deactivation of the clock at the end of each phase as depicted in figure 3.11. That way, eachphase duration is approximately constant which adds robustness to the system.

Furthermore, and as shown in section 3.9.1, the gate-leakage current of the MOS capacitor issignificant for this design, in order to reduce it, the flying capacitor is left floating when the SCPCis deactivated. This is easily implemented knowing that the SCPC can only be deactivated aftera raising edge of the clock signal.

As a conclusion, the flip-flops were firstly added to allow for experimentation with different phasesequences and to simplify the way to set the phase at which the flying capacitor is connected whenthe SCPC is disabled. Even-though different phase sequences were not implemented in the finaldesign, the flip-flops are kept to simplify the connection of the flying capacitor when the SCPC

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sp

sn

clk

enclk

Figure 3.10: Enable block schematic.

is disabled and to add robustness to the system. If the flips-flops were not added to the circuit,the flying capacitor would remain connected to the phase were it was connected at the instantwhen the SCPC is disabled, increasing the leakage current consumption of the flying capacitor asshown in section 3.9.1. For example, assuming the flying capacitor is connected across Vdd whenthe enable signal is deactivated would imply that the capacitor remains connected across Vdd whenthe SCPC is disabled. That would increase the leakage losses significantly, for that reason, theflying capacitor is left floating when the SCPC is disabled.

Figure 3.11 shows the output of the enable block in a particular case. The waveform on the top isthe output of the P-comparator and the one below is the enable block output. In order to illustratethe functionality of the enable block the output waveform is shown for a P-well charging process.As seen in the figure, the P-comparator is disabled while the flying capacitor is charged to Vddbut the oscillator is disabled one period afterwards. As a consequence, the charging process of theP-well is finished even though the P-comparator is not active. Now the flying capacitor is in itsinitial state and hence it has a known starting point.

3.4 Dual-Ramp Oscillator

The oscillator used in the RBB generator is depicted in figure 3.12. This block is re-used fromthe previous design. The oscillator alternatively charges two capacitors through a current source.The capacitors are alternatively discharged using switches. This oscillator can be conceived as atwo finite state machine. The control signal is clk, when clk = 1 the bottom capacitor is chargedand the upper one is discharged. When the bottom capacitor voltage reaches the threshold of thebuffer, the buffer toggles its output high. Because of that, the SR-latch is reset and the outputof the oscillator becomes low. When clk = 0 the behavior is the opposite, the upper capacitorgets charged and the bottom one is discharged. Then the SR-latch is set to ’1’ making clk = 1and repeating the cycle again. To achieve low frequency and low power consumption the currentsource provides only 10 nA approximately.

3.4.1 Cross-Conduction Reduction

A positive feedback loop is used in the oscillator to reduce the cross-condcution power consumptionof the buffers. The idea is to reduce the time the PMOS and NMOS transistors of the buffer drawcurrent at the same time. The positive feedback loop is composed of three transistors and is

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Figure 3.11: Enable block input and output waveformsignals. The charging process of the P-well is finishedeven though the P-comparator is not active.

Figure 3.12: Dual-ramp oscillator schematic.

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level-shiftersphase-controloscillator non-overlappingΦ1

Φ2ΦN

ΦA

ΦP

enable

Figure 3.13: Schematic view of the power gating.

depicted in figure 3.12. Once the input of the buffer starts to approach the VT of the NMOS (M1or M4) the feedback-loop is triggered. Then, it starts injecting current to the input of the bufferuntil the buffer input raises to Vdd. The time used to raise the buffer input to Vdd is much shorterthan the charging-time of the capacitor as seen in the waveforms shown in figure 3.12. That way,the amount of time during which both PMOS and NMOS transistors conduct simultaneously isminimized and hence the power consumption is reduced.

3.5 Power Gating

In the previous design a power-switch was used for the oscillator to disconnect the supply andreduce its power consumption. Since the oscillator is deactivated most of the time, the leakageof the oscillator is higher than its dynamic power consumption if no power-gating techniques areapplied.

In order to reduce the power consumption, not only the oscillator but the non-overlapping andphase-control blocks are disconnected from the power supply. The remaining blocks are not suitableto get power-gating since they need to remain active like the comparators or they need to holdsome outputs high like the level-shifters block.

Obviously, if the comparator is disconnected from the power supply it would not be monitoringthe output voltages and the RBB generator would not work. In a similar way if power-gating isapplied to the level-shifter blocks the outputs supposed to be tied to Vdd would discharge to groundcausing problems to the blocks connected after the level-shifter. Figure 3.13 shows the schematicused to implement the power gating.

When the enable block is active (active low), the PMOS switch is activated delivering power tothe oscillator, non-overlapping and phase-control blocks. When the enable block is not active theswitch is turned-off and all those blocks are disconnected from the power supply.

3.6 Non-overlapping Block

In order to drive the power of the SCPC switches a non-overlapping clock is needed. That wayit is assured that switches of different phases will never conduct at the same time avoiding short-circuits between different power supply voltages. The non-overlapping circuit used is depicted infigure 3.14. This circuit is based in a standard non-overlapping circuit, the only difference is inthe delayed feedback. In this case the highest delay is caused by the level-shifters, therefore, thelevel-shifter signals are included in the feedback loop. As seen in figure 3.14 the outputs of thelevel-shifters are feed back to the input of the non-overlapping circuit.

The output voltage of the non-overlapping circuit is shown in figure 3.15. From the oscillatorsignal, two clock phases are generated as seen in figure 3.15. The two outputs are complementaryand have some amount of dead-time between them. That way it is assured that one phase is turnedOFF before another one is turned ON. The amount of dead-time is defined by the delay of thenon-overlapping circuit, and of course, it is made the minimum possible in order to maximize thepower efficiency of the SCPC.

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Phase

Control

LS-A

LS-P

LS-N

A-phase

detector

Figure 3.14: Simplified schematic of the non-overlapping circuit.

Figure 3.15: Output voltages of the two-phase non-overlapping circuit.

For the N and P-phases there is only one lever-shifter per phase, therefore, that level-shifter is usedas a delay. An OR gate can be used for the N and P level-shifters since they are never ON at thesame time. On the other hand, the A-phase has two level-shifters so the circuit needs to decidewhich one to use. After simulation, it is observed that the delay depends on the type of edge, ifits a falling or raising edge, therefore, the circuit needs to decide which is the slowest one in alltransitions. The block designed to make this decision is the phase-detector block.

3.6.1 Phase-Detector Block

Phase A has two switches and both switches need a level-shifter. The outputs of those level-shiftersare called 0a1r and 0a2r. Since the switches of the A-phase are implemented using a NMOS andPMOS transistors their gate signals have opposite polarity, when one signal is high the other is lowand vice versa. As seen in figure 3.16, the slowest signal is 0a2r when 0a1r rises and the oppositewhen 0a2r rises.

The non-overlapping block has an input that should come from the A-phase level-shifters outputas seen in figure 3.14. But the phase-A has two level-shifters and hence two output signals. Thesesignals should be combined into one to be feed back to the non-overlapping circuit. Ideally, thesetwo signals are equal with different polarity. In reality, because of the asymmetric delays of digitalcircuits, each level-shifter output has a different delay depending on the type of edge (raising orfalling edge) and the capacitive load to which is connected.

In order to perform correctly, the non-overlapping circuit needs a signal with the same polarity asthe Oa1r signal in one of its inputs. Connecting the Oa1r signal directly to the non-overlappingblock is not possible because it would cause a short-circuit at the switches of the SCPC. The short-circuit would be caused because the delays of the level-shifters for the phase A are different. Forexample, assuming that the signal Oa1r is connected directly to the non-overlapping block, whenthe signal Oa1r raises the switch Oa1 of the SCPC is opened while the switch Oa2 is still closedbecause its driving signal (Oa2r) is slower. At the same time, the non-overlapping circuit detectsthe edge of the Oa1r signal and toggles its output activating the phase P or N (depending on theoutput current). Therefore, the switches of the phase P or N are closed while the switch Oa2 isstill closed creating a short-circuit. The same would have happened if the Oa2r signal would havebeen connected to the non-overlapping block, because as shown in figure 3.16, at both edges there

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Oa1r

Oa2r

01 11 10 11 01

Figure 3.16: Simplified waveforms of the outputs ofthe level-shifters for phase A.

r

r

r

r

Figure 3.17: Phase-Detector schematic.

is always one signal that is slower than the other.

Therefore, a circuit is needed to detect the slowest signal, which is the same as combining thetwo outputs of the phase-A level-shifters into one signal. Combining these two signals using onlycombinational logic is not possible, because as seen in figure 3.16, for the same inputs the outputneeds to be different depending on the previous state of the level-shifters. For example, for thisdesign, the signal connected to the non-overlapping circuit should be low when there is a raisingedge of the Oa1r signal and the opposite when there is a falling of the Oa1r signal. If the Oa1rsignal is considered as the state of a sequential circuit, when both signals are high (Oa1r and Oa2r),the circuit needs to store its previous state. That way, the phase-detector output will have theadequate polarity and delay to drive the non-overlapping circuit and hence to avoid short-circuitsat the SCPC.

The circuit designed to detect which signal is the slowest one is shown in figure 3.17. This circuitis based in a standard arbiter circuit, an arbiter circuit detects which is the fastest signal, onthe contrary, the phase-detector circuit detects the slowest signal. The phase-detector block usescombinational logic and an SR-latch to determine which signal arrives the last. When both signalsare high the latch stores the previous value and the output does not change again until both signalsare different. The truth table of this circuit is depicted in table 3.3. In conclusion, when the inputsignals (Oa1r and Oa2r) are equal means there is a transition, therefore, the output (Q) shouldnot change and retain its previous value until both signals reach a steady value in order to avoidshort-circuits at the SCPC.

0a1r 0a2r S R Q0 0 1 1 q0 1 0 1 01 0 1 0 11 1 1 1 q

Table 3.3: Phase-Detector truth table.

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Figure 3.18: Alternative version of the non-overlapping block schematic. Fixed-delay non-overlapping circuit.

Sp Sn A-phase P-phase N-phase State Description0 0 gnd gnd gnd Idle The wells are charged and

nothing needs to be done. Thecapacitor is kept floating.

0 1 θ1 gnd θ2 N-active The N-well needs to be charged.1 0 θ1 θ2 gnd P-active The P-well needs to be charged.1 1 θ1 θ2 / gnd gnd / θ2 N/P-active Continuous operation. Both the

N-well and P-well need to becharged.

Table 3.4: Phase-Control block states.

3.6.2 Schematic Alternatives for the Non-overlapping Block

In order to simplify the schematic for the non-overlapping block other alternatives were considered.A fixed delay block was used to implement the non-overlapping circuit. The fixed delay wasimplemented using transmission gates as seen in figure 3.18. This version of the schematic hada slightly better power performance for a nominal output but for other process corners the delaywould have need to be increased. Since the current consumption is almost the same betweenthe two alternatives, at the end, feedback loops via the level-shifters are used because they addrobustness to the system. Using the level-shifters it is assured that the delay is always sufficientfor the application and hence a worst case design is not necessary.

3.7 Phase-Control Block

The Phase-Control block decides which well needs to be charged depending on the outputs of thecomparators. This circuit uses the outputs of the non-overlapping clock, θ1 and θ2, to drive thepower switches via the level-shifters as depicted in figure 3.20. Depending on the value of thecomparators the multiplexer selection signals are generated, ’msOa’, ’msOp’ and ’msOn’. Signal’msOa’ drives the multiplexer which generates phase A and signals ’msOp’ and ’msOn’ drive themultiplexers to generate phase P and phase N, respectively. Signals ’msOp’ and ’msOn’ must notbe active at the same time since in that case the switches of the converter would be short-circuited.

In order to generate the selection signals the circuit has been divided in four states as depictedin table 3.4. From the results of table 3.4 its possible to start designing the logic to drive themultiplexers of figure 3.20. In the idle state, the output of the three multiplexers is ’gnd’ in orderthe maintain all switches OFF and hence leave the capacitor floating. As mentioned before, whenthe converter is in the idle state the output of phase A should be at ground. Otherwise, when the

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Figure 3.19: Phase-Control block input/output wave-forms.

MUX

MUX

MUX

ΦNΦA ΦP

Φ1 Φ2 Φ2

gnd gnd gnd

ms0Oa msOp msOn

Figure 3.20: Phase-Control block simplifiedschematic.

converter is in one of the active states the output of phase A should be the phase 1 output (θ1) ofthe non-overlapping clock as shown in table 3.4. Therefore, the output of phase-A is always ’gnd’or θ1.

Phase N and P are more complex. When just one comparator is active one phase is connected toθ2 and the other one to ’gnd’, this is true for states N-active and P-active as depicted in table 3.4.When both comparators are active, N/P-active state, the output of the N-phase and the P-phaseneed to toggle between the N-active and P-active state continuously. Therefore, when the P-phasehas its output connected to θ2 the output of the N-phase must be connected to ’gnd’ and viceversa. The phase-control block is what implements the capacitor steering operation requested bythe dual output SCPC.

Figure 3.19 shows the input and output waveforms of the phase-control block for all the possiblecases, when both comparators are active, when only one comparator is active and when bothcomparators are not active. In this example the comparator outputs are active high. From top tobottom the waveforms are: the output of the P-comparator, the output of the N-comparator andthe output of phase A, phase P and phase N.

When both comparators are active, the signal θ2 from the non-overlapping clock is toggled betweenphase P and N. When just one comparator is active, θ2 is connected to phase P or phase N. In allthree cases θ1 is always connected to phase A. When both comparators are deactivated the outputsof the phase-control block are switched to ’gnd’ to keep the flying capacitor floating.

The generation of the selection signals for the multiplexers is done using digital logic. The logicused is shown in the complete schematic of the phase-control block depicted in figure 3.21. Theoutputs of the P-comparator and N-comparator are ’sp’ and ’sn’, respectively. Signal ’phase1’

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Oa Op

On

phase1

phase2

phase2

gnd

gnd

gnd

spa

sna

sp

sn

Figure 3.21: Phase-Control block schematic.

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Figure 3.22: Signals ’x’ and ’cpwn’ from the phase-control block for the input signals θ1, θ2, ’sp’ and’sn’.

stands for θ1 and signal ’phase2’ stands for θ2.

The A-phase is very simple to implement as shown in table 3.4. Since phase A needs to be activatedwhen the P-comparator or the N-comparator is active, an OR-gate between the comparator outputsis used to drive the ’msOa’ signal. Generating the signals for phase P and phase N is more complexsince more situations need to be considered. First, some secondary signals will be explained inorder to simplify the explanation of the generation of signals ’msOp’ and ’msOn’. One of thissecondary signals is ’x’ which is active when both comparators are active. The ’cpnw’ signal is aclock signal with a period equal to 2 ·Tclk. This signal is used to toggle θ2 between phase N and Pwhen both comparators are active. The ’cpnw’ signal is generated from the non-overlapping clockusing a T-type flip-flop. The flip-flop is implemented using a D-type flip-flop with enable and ituses an inverter to feed back its output to its input. Both signals, ’x’ and ’cpnw’, are depicted infigure 3.22. As seen in the figure, signal ’x’ is active when both comparators are active. Signal’cpnw’ is active when ’x’ is also active and it has period of 2 · Tclk.

Knowing what signals ’x’ and ’cpnw’ do, it is easier to understand how signals ’msOp’ and ’msOn’are generated. The ’msOp’ signal is active in two different situations. The first one is when theP-comparator is active and the N-comparator is deactivated. The second situation occurs whenboth comparators are active and the signal ’cpnw’ is high. For the ’msOn’ signal it is the opposite,’msOn’ is active if the N-comparator is active and the P-comparator is deactivated or when bothcomparators are active and ’cpnw’ is low. Therefore, the logic functions used to drive the inputsof the multiplexers are:

msOa = sn · sp (3.26)

msOp = x · cpnw + sp · sn (3.27)

msOn = cpnw · x+ sp · sn (3.28)

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3.7.1 Potential Causes of Failure of the Phase-Control Block

Output Glitches at the Phase-Control Block

One charge cycle consist in charging the flying capacitor to Vdd and then discharging it to the Por N-well. This cycle starts with the raising edge of θ1 and finishes with the falling edge of θ2.Signals ’sn’ and ’sp’ are asynchronous so that they can change at any time and hence can causeglitches. If the inputs, ’sn’ and ’sp’, are synchronized with the falling edge of θ2, it is forced thatat the beginning of a new charge cycle the inputs have an steady value. In order to avoid glitches,signals ’sn’ and ’sp’ are captured with a flip-flop to force that they change at a known instant.That way it is forced that the comparator outputs have an steady value at the beginning of a newcharge cycle.

If the signal ’cpnw’ is synchronous with the falling edge of θ1, and the outputs of the comparatorsare synchronous with the falling edge of θ2, means that the signal ’cpnw’ will be steady whenthe signals ’sna’ or ’spa’ change because both the output of the comparators and ’cpnw’ aresynchronized with different phases. Therefore, glitches are avoided. To conclude, if the T-typeflip-flop is driven with θ1, the outputs of the comparator should be synchronous with θ2 and viceversa (and always with the same type of edge as seen in the schematic).

If the glitches of the phase-control block were not addressed, the converter could have an unexpectedbehaviour. Assuming that two or more inputs change at the same time or very close to each other,the outputs of the phase-control block could have glitches and hence the converter would notoperate properly. The switches of the SCPC would be opened and closed very fast when is notnecessary increasing the losses of the system.

Meta-Stability at the Input Signals of the Phase-Control Block

The comparator outputs are synchronized with just one flip-flop. This is not adequate if meta-stability needs to be avoided but that is not the case. Therefore, only one flip-flop for each inputis used in order to reduce area and power consumption. In principle, if ’sn’ or ’sp’ change at thesame time that the falling edge of θ2 does, it could cause a meta-stable voltage level at the outputof the flip-flop causing the rest of the logic to misbehave. This meta-stable state would be veryshort in comparison with the dead-time of the non-overlapping clock and hence it is not a problem.

The highest recovery time, for a load of 10 gates, is less than 500 ps (results obtained fromsimulation) and the fastest clock has a period much higher than 500 ns (three orders of magnitudehigher). Also, the clock is very slow and so are its edges. Since the clock is very slow and theactivation frequency of the comparator is also very small, the probability of meta-stability issuesis also reduced.

Furthermore, even if meta-stability happens, it is not a problem. If a meta-stable state is given,the synchronized comparator outputs will be wrong for one clock period but for the next clockedge, the comparator output will be stable and the output of the flip-flops will be correct. In figure3.21, the comparator outputs are ’spa’ and ’sna’ and the synchronized comparator outputs are ’sn’and ’sp’. Therefore, if a meta-stable state is given, the worst case will be that the switches of theSCPC will have a delay of one clock period which is not a problem at all.

3.8 Level-Shifter Block

The SCPC has different switches connected to different voltage domains. In order to properly openand close the switches, adequate gate voltage values need to be generated. The level-shifter blockhas different level-shifters to drive the gate signals of the MOSFET switches. The schematic ofthe level-shifter block is depicted in figure 3.23.

Single buffers or inverters are used for the switches that do not need level-shifting since the switches

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Figure 3.23: Level-shifters schematic.

are small enough and do not need extra buffering. For the remaining switches two types of level-shifters are used, the first one, called ’Level-Shifter’ is used to convert between the domain [0 : Vdd]to [Vpw : Vdd] and the second one, called TLSX5, is used to convert voltages from [0 : Vdd] to[0 : Vnw]. The voltages used to drive the switches are depicted in table 3.5. The output voltages ofthe level-shifters for the P-well charging process are shown in figure 3.24 and the output voltagesfor the N-well level-shifters are depicted in figure 3.25.

3.9 Switched-Capacitor Power Converter

The switched-capacitor converter has been designed in order to keep more or less the same areaof the previous design and to reduce its power consumption. In order to increase the powerperformance of the RBB generator the output impedance concept can be applied to it. In thiscase, due to the control loop, the activity of the switched-capacitor for the RBB generator isduty-cycled. That means that the switching frequency is fixed but the time the RBB is workingis variable and depends on the output load. The idea is to maximize the energy delivered to theload for a given switching period and that implies reducing the output impedance. Therefore, theswitches and hence the on-resistance has been designed to have RFSL = RSSL, which represents agood trade-off between conduction losses and switching losses. Once the switches have being sized,their On-resistance becomes 2 KΩ approximately.

In this case the size of the capacitor needs to be big enough in order to provide the desiredoutput current for all corners and temperatures. If the average current through a capacitor isIc = fsCf∆Vcf , the bigger the capacitor the better. On the other hand, the area of the capacitorremains the same in order to use the same area as in the previous design. Therefore, it is desired

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Figure 3.24: Op-phase level-shifters inputs and out-puts.

Figure 3.25: On-phase level-shifters inputs and out-puts.

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Figure 3.26: Simplified schematic of the SCPC.

to have the highest capacitance for the given area. Obviously, the capacitance is much higher thanthe requested for the nominal load but that is because the converter needs to deliver the requiredoutput current for higher loads also.

Regarding the reduction of the output impedance, the main points are the following. The area ofthe capacitor is given and the capacitor needs to be big enough to deliver the requested outputcurrent and hence, the objective is to maximize the capacitance for the given area. Because of that,it is not possible to change the output impedance through the capacitance value. The switchingfrequency is fixed because of the control scheme used in the RBB generator, therefore, changes inthe switching frequency are not possible. The only remaining design variable is the switch size andit is designed to minimize the output impedance as explained in section 1.2.

A simplified schematic of the SCPC is shown in figure 3.26. It has 3 phases and 6 switches.Switches Oa1 and Oa2 are on during phase A, Op1 and Op2 are on during phase P and finallyOn1 and On2 are on during phase N. The positive plate of the floating capacitor is called Cp andthe negative plate is called Cm as depicted in figure 3.26. The Cp node will be at 1.9, 1.2 or 0V and the Cm node will be at 1.2, 0 or -1 V depending on the switching phase of the converter.With this information its possible to decide which type of switches will be used and how they willbe driven. The decision of which kind of switch needs to be used is based in which voltages willhave to withstand when it is OFF and how easy it will be to generate these voltages. The selectedtype of switch is depicted in table 3.5 along with its ON and OFF gate voltages. All the switchesare implemented using thick-oxide transistors since they have to withstand voltages higher thanVdd.

The complete schematic is depicted in figure 3.27. All transistors have their bulks connected tothe lowest potential if they are NMOS transistors or to the highest potential if they are PMOStransistors. For some of the NMOS-type switches an isolated P-well is used to make the appropriateconnections since their bulk is connected to a voltage below ground. Switches Oa2 and Op2 use anisolated P-well which is tied at -1 V. The isolated P-well is placed inside a deep N-well as depictedin figure 3.28. As seen in the figure all PN junctions are reversed-bias. Thanks to the deep N-wellthe isolated P-well can be tied to other voltages different than ground. The drain and source ofswitch Op1 is always at 0 V or higher and hence its bulk is tied to ground. The PMOS switchesare placed inside an N-well. Switches Oa1 and On1 have its bulk tied to 1.9 V and On2 is tied toVdd. The layout view of the switches is depicted in figure 3.29. The output voltages of the SCPCare depicted in figure 3.30.

3.9.1 MOS-Capacitor

As it will be mentioned in the simulation results section, the capacitor is the main source oflosses in the RBB generator. Different implementation types for the capacitor have been tried

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Switch Type On-voltage Off-voltage Type selection justificationOa1 PMOS 0 V 1.9 V If the gate is 1.9 V the switch is

always closed regarding thevoltages at its drain/source.

Oa2 NMOS 1.2 V -1 V If the gate is -1 V the switch isalways closed regarding thevoltages at its drain/source.

Op1 NMOS 1.2 V 0 V The lowest voltage is 0 V and itis always at the same node.

Op2 NMOS 1.2 V -1 V The lowest voltage is -1 V andit is always at the same node.

On1 PMOS 0 V 1.9 V The highest voltage is 1.9 V andit is always at the same node.

On2 PMOS 0 V 1.2 V The highest voltage is 1.2 V andit is always at the same node.

Table 3.5: SCPC switch types.

Figure 3.27: Schematic of the SCPC.

Figure 3.28: Cross section of a NMOS transistorplaced in an isolated P-well.

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Figure 3.29: Layout view of the RBB switches.

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Figure 3.30: N-well and P-well output waveforms ofthe RBB generator.

Figure 3.31: RBB generator efficiency for differentcapacitor types.

as seen in figure 3.31. G01 transistors have a thin gate-oxide and G02 transistors have a thickgate-oxide. The most efficient one is the thin-gate PMOS type capacitor. Between thin and thickgate capacitors the thin-oxide ones are preferable because they have a higher capacitance densitysince the dielectric of the equivalent capacitor is thinner. However, the leakage of the thin-oxidetransistors is orders of magnitude higher than the thicker ones; from nano to pico-amperes.

In order to reduce the leakage losses of the capacitor, the capacitor itself is left floating when theRBB generator is not active. When the oscillator of the RBB is deactivated the flying capacitoris left floating. As a consequence, the only charge that can be lost is the charge remaining in thecapacitor from the previous charging process, at the most, ∆Q = Cf ·∆Vdd. The capacitor getsdischarged because of its own leakage current and hence the voltage across it decreases. Since thevoltage across the capacitor decreases the leakage current also decreases. As depicted in figure3.32, the leakage increases exponentially depending on the voltage across the capacitor. Thus, ifthe capacitor is left floating when the RBB generator is not active, the voltage across the capacitoris reduced and hence the leakage losses are also reduced. If the flying capacitor is not floating whenthe RBB generator is deactivated, the use of a thin-oxide capacitor would not be feasible becauseits high leakage current.

The PMOS capacitor has a much smaller leakage current in comparison with the NMOS capacitor.The reason for that is because in inversion, the main tunnelling component in a PMOS capacitoris the hole tunnelling from the valence band as opposed to electron tunnelling from the conductionband in NMOS capacitors [10]. Observing the models for the gate-leakage [11] it is concluded thatthe PMOS has less leakage mainly because its tunnelling barrier height is larger. On the other hand,the implementation of the NMOS capacitor is likely to have (mainly because technology parameters

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Figure 3.32: Gate-leakage current for a PMOS andNMOS capacitors as function of the voltage acrossthem.

such as doping concentration [12]) less parasitic bottom-plate capacitance than a PMOS capacitorsince the N-well typically has a higher doping concentration than the isolated P-well. For thisdesign, the difference between bottom-plate losses of the PMOS and NMOS transistors is notsignificant. Since the leakage losses of the NMOS capacitor are higher than the leakage losses ofthe PMOS capacitor, the use of a PMOS capacitor is more convenient for this design.

Different voltage connections at the wells of the MOS capacitors, for both NMOS and PMOS, havebeen tried aiming for a reduction in the bottom plate losses. Nonetheless, the high leakage of theNMOS capacitor makes it not suitable for this application. Therefore, a PMOS capacitor is usedas a flying capacitor as mentioned at the beginning of this section.

Well Connections Alternatives for Bottom Plate Losses Reduction

The idea behind the bottom plate losses reduction is to decrease the capacitance of the parasiticcapacitors. These parasitics are given by the capacitance of the reversed biased PN junctions. Thecapacitance per unit of area of the reversed PN junction can be approximated by the depletioncapacitance as [12]:

Cd =ε

WD(3.29)

where ε is the permittivity of the dielectric and WD is the width of the depletion region. Therefore,the P+N junction capacitance per unit of area is affected by the voltage across it:

Cd =

√eεND

2(VD − V )(3.30)

where VD is the built-in voltage, V is the voltage applied to the junction and ND is the dopingconcentration. As noticed from the previous equations the voltage across the junction affects itscapacitance. Therefore, it is possible to modify the bottom plate capacitance modifying the voltageof the wells.

For the PMOS capacitor there are not so many alternatives. If the 3.3 V power supply wereavailable it could be connected to the N-well in order to make create a stronger reversed-biasjunction but in this case the available voltages for the N-well are Vdd (1.2 V) and Vnw (1.9 V). If

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the N-well of the PMOS capacitor is connected to Vdd, when the P-channel is at 1.9 V, the PNjunction between the P-channel and the N-well is forward biased and some current flows from the1.9 V output to Vdd. This current taken from the 1.9 V output decreases the efficiency of theRBB generator; from 33 % to 26 %. As a consequence, the N-well must be connected to the 1.9V output so the PN junction between the channel of the capacitor and the well is always reversedbiased. Furthermore, the N-well to substrate parasitic capacitance of the PMOS flying capacitoradds an extra capacitance to the output capacitor of the 1.9 V output.

Regarding the NMOS capacitor more solutions are available since this capacitor has a deep N-well and an isolated P-well to be biased. Therefore, more combinations are available. However,decreasing the bottom plate losses of the NMOS capacitor is not worthy since its leakage lossesare too high for this application.

Ideal Maximum Output Current

The maximum output current that the RBB generator can deliver is mainly defined by the flyingcapacitor and the switching frequency; assuming the flying capacitor has enough time to getcompletely charged. Considering that both output comparators are active, the SCPC deliverscharge to each output at a rate of 2 · Tclk. Therefore, the maximum output current available foreach well is:

IpwMAX=fclk2Cf (Vdd − |Vpw|) = 6.7µA (3.31)

InwMAX=fclk2Cf (2Vdd − Vnw) = 16.7µA (3.32)

(3.33)

As shown in section 4.3, the output current is around this values when the output voltage startsto decrease.

3.9.2 Flying Capacitor Layout

As explained in the previous section, the most efficient capacitor for this design is the thin-oxidePMOS capacitor. The capacitor is placed inside an N-well tied at Vnw. Since the size of thiscapacitor is around 8100 µm2, it needs to be divided into smaller ones in order to pass the Design-Rule-Check (DRC) since it is not allowed to draw such a big poly-silicon area. Furthermore,dividing the capacitor into smaller ones and choosing an adequate ratio will help reducing theEquivalent Series Resistance (ESR) of the capacitor.

The total ESR of a MOS-capacitor is defined as [13]:

RESR = Rch +Rgate (3.34)

Rgate = Rpoly(αW

L+ β) (3.35)

Rch =L

γWµNCox(ηVT + Vgs − Vth)(3.36)

where Rch is the channel resistance and Rgate is the gate resistance. α is 1/3 when the gate isconnected from one side or 1/12 if the gate is connected from both sides. Rpoly is the squareresistance of the poly-silicon, β models the external resistance of the gate, which in this case isassumed to be zero, and η is a technological parameter which in this case is 1. γ is a parameteraccounting for the distributed nature of the channel. µN is the mobility of the electrons and Cox

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Figure 3.33: RESR versus W/L ratio for a thin-oxidePMOS capacitor.

is the gate oxide capacitance. Sweeping different values of the aspect ratio into the RESR equationleads to the minimum ESR value. As seen in figure 3.33, the ratio that minimizes the ESR isW/L = 10.

As mentioned before, the flying capacitor will be divided into smaller ones to pass the DRC.Therefore, the flying capacitor will be implemented by various capacitors connected in parallel.Each of this smaller capacitors will have its optimum aspect ratio, W/L = 10, in order to reduce theESR. Assuming there are n capacitors connected in parallel, the ESR will be also further reducedby an n factor. To summarize, the ESR is reduced by two techniques, first, the optimization of theaspect ratio for the ESR reduction, and second, the parallel connection of the smaller capacitors.

The schematic of the flying capacitor consists of nine MOS-capacitor instances connected in parallelas depicted in figure 3.37. These nine capacitors are connected in parallel using a metal layer inorder to pass the DRC for the poly-silicon layer. The decision of having nine capacitor instancesand not another number of capacitors was made because its a good trade-off between layoutsimplicity and area overhead (due to the metal connections). Each of this nine capacitors has adimension of W = 300 and L = 3 with 10 foldings, implying a parallel connection of 90 individualcapacitors (n = 90). With these parameters each individual capacitor has its optimum aspect ratio(W/L = 10) and the total capacitor area is the same as in the previous design (8100µm2).

The capacitance of the PMOS capacitor is increased by placing a fringe capacitor on top of it.The fringe capacitor layout is depicted in figure 3.34. Horizontal Metal1 strips are used at thebottom instead of vertical strips because of the layout of the PMOS capacitor. This Metal1 stripsare connected to Metal2 using vias. From the Metal2 layer until the Metal5 layer the strips arevertical. Views a) and b) are the same except that view a) has the Metal3 layer disabled in orderto show how the metal layers are connected. From Metal2 to Metal5 the layout is the same asseen in figure 3.34 c). Each color represents one plate of the capacitor, therefore, the vertical andhorizontal electrical field between each metal is used.

After the layout has been finished a parasitic extraction is performed and the capacitor is simulatedagain. The total capacitance and the ESR of the capacitor are computed through an AC simulation.The total ESR of the capacitor, after layout extraction, is RESR = 2.1 Ω and the total capacitanceis approximately Cf = 100 pF; 17 pF are obtained from the fringe capacitor and 83 pF from thePMOS capacitor.

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Figure 3.34: Detailed view of the fringe capacitor lay-out. a) Layout view with the Metal3 layer disabled.b) Layout view with the Metal3 layer enabled. c)Cross-sectional view of the fringe capacitor.

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Figure 3.35: Capacitive coupling between the channelof the PMOS capacitor and Vnw.

3.9.3 N-well Ripple Noise

The bulk of the PMOS capacitor is connected to Vnw, therefore, some capacitance coupling existsbetween the channel of the PMOS capacitor and Vnw. This capacitance coupling exists throughthe PN junction between the N-well and the P+ of the flying capacitor as depicted in figure 3.35.Hence, the parasitic capacitor has one plate at Vnw and the other plate at the channel of the PMOScapacitor, from now on VCp. The channel of the PMOS capacitor is switching between differentvoltages and transferring current between this two nodes. Thus, creating a voltage ripple at theN-well. This ripple has a peak-to-peak voltage of 10 mV which is much smaller than the ripple ofthe SCPC (124 mV) and hence it does not affect the performance of the SCPC.

When the flying capacitor of the SCPC is at the P-phase VCp is at ground, then, when it switchesto the A-phase VCp becomes Vdd and the current flows into the parasitic capacitor charging theN-well. When the parasitic capacitor switches back from Vdd to ground the current flows out ofthe capacitor and the N-well is discharged. This is shown in figure 3.36, when the flying capacitoris at phase A, the parasitic capacitor is charged and Vnw increases, when the flying capacitor isconnected to phase P the parasitic capacitor is discharged and Vnw decreases as observed in thefigure. Because of that, some of the current from the parasitic capacitor flows into the P-wellincreasing its voltage and producing small voltage spikes as seen in the detail of the Vpw output.

3.10 General Layout of the RBB Generator

The complete layout of the RBB generator is depicted in figure 3.37. The total area of the designis the same as in the previous RBB generator [2]; that is 0.02 mm2. The different parts of theRBB design are outlined in the figure, more than half the size of the RBB generator is occupiedby the flying capacitor and the rest by the control loop circuitry and the test structure. The teststructure contains the switches used to select the voltages to where the wells of the digital circuitare connected as seen in figure 2.3. The control loop contains all the blocks used to drive theswitched-capacitor; that is the oscillator, the comparators, the level-shifters, etc.

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Figure 3.36: N-well ripple noise voltage waveforms.From top to bottom the signals are a detail of the N-well and P-well outputs, and the phase-control out-puts; phase A, phase N and phase P respectively

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Figure 3.37: Layout of the RBB generator.

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Chapter 4

Simulation Results

4.1 Efficiency Results

The design has been simulated in Spectre using Cadence design environment. From the simulationresults the efficiency of the RBB for a nominal output load is:

Vpw = −1.04 V (4.1)

Ipw = 100 nA (4.2)

Vnw = 1.86 V (4.3)

Inw = 10 nA (4.4)

Vdd = 1.2 V (4.5)

Ivdd = 294.6 nA (4.6)

Ilogicvnw = 5.7 nA (4.7)

Ilogicvpw = 9 nA (4.8)

η =|Vpw|Ipw + VnwInw

VddIvdd + VpwIlogicvpw+ VnwIlogicvnw

= 33% (4.9)

The efficiency results of the previous design [2] are:

Vpw = −1.01 V (4.10)

Ipw = 100 nA (4.11)

Vnw = 1.76 V (4.12)

Inw = 10 nA (4.13)

VddSCC= 1.2 V (4.14)

IvddSCC= 162 nA (4.15)

VddLDO= 3.3 V (4.16)

IvddLDO= 173 nA (4.17)

η =|Vpw|Ipw + VnwInw

VddSCCIvddSCC

+ VddLDOIvddLDO

= 15.5% (4.18)

In comparison to the previous design the efficiency has been doubled while keeping the same area(0.02 mm2). The main reason for the efficiency improvement is the change in the architecture. TheLDO was the most inefficient block and its replacement by a switched-capacitor power converterimproves the efficiency of the RBB generator.

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4.2 Current Consumption of the RBB Generator

The total current consumption of the RBB generator is 309 nA. The main current consumption, 247nA, comes from the switches and the flying capacitor; from now on switched-capacitor. Obviously,this current is the highest one since the switches and flying capacitor are the ones that transferthe current from the input to the output. The remaining current, which is 62 nA, is consumed bythe control circuitry.

Assuming that the switched-capacitor converter is ideal and that the logic consumes zero current,the ideal current of the RBB is 120 nA as explained in section 4.2.2. Since the simulated current ofthe flying capacitor and switches is 247 nA, there is an extra 127 nA because of the losses on topof the ideal 120 nA. Therefore, the main losses of the whole system are because of the switched-capacitor (127 nA) and the control logic (62 nA). In the next sections, the current consumption ofthe control logic and the switched-capacitor are explained in more detail in order to understandthe current consumption of the RBB generator.

4.2.1 Current Consumption of the Control Logic

The current consumption of the control logic is broken down in figure 4.1. All these average currentvalues are obtained when the converter operates under nominal specification (i.e. duty-cycledactivity). From left to right the currents represented in the graph are the current of comparatorsP and N, the level-shifters current, the oscillator, the reset block, the non-overlapping and thephase-control block. As seen in the figure the comparators take the most current (IcompP andIcompN). This is expected since the comparators are continuous-time and hence they always drawsome current. The N-comparator has a voltage divider that takes 4.7 nA of current and the voltagedivider of the P-comparator takes 6.9 nA. Both comparators charge a capacitor every time theyreceive a reset signal, moreover, the comparators have an inverter with its input and output short-circuited at the reset phase increasing the power consumption. The other parts of the circuit areclock-based, therefore, they only take current when the oscillator is active.

Another interesting point here is that the switches of the converter take very little current. Thelow-power consumption of the switches can be demonstrated from the graph since the current takenfrom the level-shifters is rather small (Ils). This current includes the current used to supply thelevel-shifters and the current delivered from the level-shifters to the switches. Therefore, the currentdelivered to the switches is negligible (less than 1 nA from the simulation results) in comparisonto other blocks of the RBB as, for example, the comparators.

These results are coherent with the operation the converter. The current consumption of the controllogic is mainly proportional to the switching frequency. With a clock frequency of 600 KHz and aduty cycle of approximately 1 %, the effective switching frequency is around 6 KHz which explainsthe low current consumption of the control logic in comparison to the total current consumption.

In conclusion, there are two points to remember regarding the current consumption of the controllogic. First, the main current consumption is caused by the comparators because they are contin-uously taking current to behave as continuous-time comparators. And second, the remaining logicblocks take very little current because their current consumption is proportional to the switchingfrequency and the duty-cycle of the operation of the RBB generator is very low.

4.2.2 Current Consumption of the Switched-Capacitor

The current consumption of the flying capacitor and switches is 247 nA. In order to understandthe current consumption of the SCPC, the ideal current consumption is analyzed and then thecurrent losses are added.

Knowing the ideal ratio between input and output current of a SC converter it is possible tocalculate the input-output current ratio of the RBB generator. For the nominal output load the

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Figure 4.1: Control logic current consumption of theRBB generator.

RBB generator can be seen as two separate converters working independently. This holds true ifthe output current is small enough so the converter never needs to deliver charge at both outputsat the same time, ideally, this is the same as having two separate converters for each output.Therefore, the input current given a determined load for the RBB generator is the sum of theinput current of a voltage doubler and a voltage inverter:

Iin = npwIpw + nnwInw (4.19)

(4.20)

Where nnw and npw are the ideal conversion ratios for each output; 2 for a voltage doubler and -1for an inverter. Hence, the expected input current of the RBB generator is:

Iinideal= −1 · Ipw + 2 · Inw = −1 · −100 nA + 2 · 10 nA = 120 nA (4.21)

(4.22)

This is the expected ideal current in case of having a 100 % efficient SCPC. To have an idea ofthe current consumption of the RBB generator the current losses should be added. The mainlosses of the capacitor are the gate leakage and bottom plate losses. The gate leakage currentlosses of the capacitor are a non-linear function of the voltage across the capacitor. The higher thevoltage across the capacitor the higher the leakage current through the dielectric. The estimationof the gate leakage current is not simple since the leakage current can not be computed from thesimulations when the capacitor is left floating. Therefore, if the leakage current is plotted from thesimulation results it will show 0 Amperes of leakage current. What is observed from the simulationsis that the voltage across the capacitor diminishes but apparently no current is flowing through it.The problem is that this current is flowing internally, inside the capacitor model, and hence is notpossible to measure it in the simulations when the capacitor is floating. Therefore the gate leakagecurrent needs to be estimated by other means.

In order to estimate the gate leakage current losses, a function of the gate current depending on thevoltage across the capacitor is needed. This function can be obtained through a DC simulation.

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Ideally, if a DC voltage is applied to the capacitor the current should be zero. In this case thatis not true since the gate leakage is included in the model of the capacitor. If a DC simulation isperformed the current through the capacitor will be the gate leakage current. Once voltage andcurrent measurements are obtained an analytical function can be derived; Igateleakage

= f(Vcap). Inorder to obtain the analytical function the current and voltage, data collected from the simulationcan be approximated to a polynomial function. Once a function which relates current and voltageis obtained, the average gate leakage current can be computed since from the simulation resultsthe voltage across the capacitor is known. If that is done the simulation results show that the gateleakage current is:

Igateleak≈ 20.9 nA (4.23)

The power losses because of the bottom plate parasitic capacitance of the converter can be com-puted as the average current through the parasitic capacitor. The average current through acapacitor when it is charged and discharged with a constant ∆V is IC = fs · C ·∆VC . Therefore,the current through the parasitic capacitor is:

ICbp = fs(DpwCbppw∆VCbppw +DnwCbpnw∆VCbpnw) (4.24)

where fs is the clock switching frequency, ∆VCbppw is the voltage variation in the parasitic capacitorwhen the P-well is charged and ∆VCbpnw the same but for the N-well. Cbppw and Cbpnw are theparasitic capacitors for the P-well and N-well outputs respectively and Dnw and Dpw are the dutycycle of the N-well and P-well outputs.

The bottom plate parasitic capacitance is different for both outputs. This is because this parasiticcapacitance is caused by a PN junction and this PN junction has a capacitance that depends onthe voltage applied to it. Therefore, the capacitance of this PN junction depends on its biasingvoltage as seen in figure 4.2. Depending on which well is charged the parasitic PN junction hasdifferent voltages across it. For example, when the P-well is charged, the parasitic capacitor hasone plate tied to Vnw and the other plate toggles between 0 V and Vdd. On the other hand, whenthe N-well is charged, one plate is tied to Vnw also and the other one toggles between Vdd andVnw. As an approximation, the parasitic capacitance values are obtained from the results of anAC simulation.

The values obtained from the simulation results to calculate the bottom plate losses are the fol-lowing:

Dnw =TONnw

Tseff

= 0.0015 (4.25)

Dpw =TONpw

Tseff

= 0.02 (4.26)

fs = 600 kHz (4.27)

∆VCbppw = 1.2 V (4.28)

∆VCbpnw= 0.7 V (4.29)

Cbppw = 7.2 pF (4.30)

Cbpnw= 9.7 pF (4.31)

where Tseffis the effective switching time; in this case the time between two charging process of

the N-well as depicted in figure 4.3. TONnwis the time the N-comparator is active during Tseff

and TONpwis the same but for the P-comparator. Therefore, the estimated bottom plate losses

are:

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Figure 4.2: Bottom plate capacitance for a PMOScapacitor with its body tied at 1.9 V. Vcp is the volt-age of the positive plate and Vcm the voltage at thenegative plate of the capacitor. The capacitance (inFarads) is represented in the Z-axis.

Figure 4.3: Simplified output waveforms of the SCPC.

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ICbp = fs(DpwCbppw∆VCbppw +DnwCbpnw∆VCbpnw) ≈ 109.8 nA (4.32)

These results are very similar from the ones obtained by simulation. From the simulation, theinput current of the switched-capacitor is 247 nA, and from the analytical results:

IinSCPC= Iinideal

+ Igateleak+ ICbp = 250.7 nA (4.33)

Another experiment to verify that the losses of the switched-cap are mainly because of the MOS-capacitor is simulating the RBB generator with an ideal capacitor. If that is done the input currentof the SCPC is approximately the ideal input current:

Ipw = 112 nA (4.34)

Inw = 19 nA (4.35)

Iinideal= npwIpw + nnwInw = 150 nA (4.36)

Iinsimulation≈ 149 nA (4.37)

In this case the output currents (Ipw and Inw) are higher than in the nominal case. That is becausethe load the switched-capacitor sees includes the output load current and the logic current takenfrom the output to drive some parts of the control logic as the level-shifters or the comparators.In this case, the output current flowing out of the P-well output is Ipw = 100 + 12 nA and for theN-well is Inw = 10 + 9 nA. It should be considered that this is not the calculation of the RBBgenerator efficiency. It is the efficiency calculation of the switched-capacitor block, and hence, theoutput current of the switched-capacitor is composed by the load current and the logic currenttaken from the output as mentioned before.

Therefore, the main losses of the SCPC are because of the flying capacitor. The flying capacitorlosses include the bottom plate (109.8 nA) and the gate leakage losses (20.9 nA). Assuming theflying capacitor was ideal, the RBB generator would have an efficiency only dependent on thecontrol logic power consumption. If it is assumed that the SCPC is ideal, its efficiency would be:

Vpw = −1.04 V (4.38)

Vnw = 1.86 V (4.39)

Inw = 10 nA (4.40)

Ipw = −100 nA (4.41)

npw = −1 (4.42)

nnw = 2 (4.43)

η =VpwIpw + VnwInw

Vdd(npwIpw + nnwInw)= 85% (4.44)

This is the maximum possible efficiency (ideal SCPC) assuming an output voltage of -1.04 Vfor the P-well and 1.86 V for the N-well. As explained in section 1.2, the ideal efficiency is not100 % because the regulated output voltages are obtained from a voltage drop across the outputimpedance of the converter. Moreover, the losses should be added to the ideal efficiency to get anidea of a realistic value for the efficiency of the SCPC.

Ideal Efficiency of the SCPC Assuming a Certain Amount of Bottom Plate Losses

As mentioned before, the bottom plate losses are different depending on which well is charged.Figure 4.4 shows the equivalent circuit for the phase A and phase P when the P-well demands

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Figure 4.4: SCPC with a bottom plate parasitic ca-pacitor for phases AP.

power. Assuming that the capacitors get completely charged and discharged. The current throughthese capacitors are:

Icf = fsDpwCf∆Vcf (4.45)

Icbp = fsDpwαpwCf∆Vcbp (4.46)

Being ∆Vcf and ∆Vcbp the voltage drops at the floating and the parasitic capacitor, respectively.If the input current is divided by the output current the results are:

∆Vcf = Vdd − |Vpw| (4.47)

∆Vcbp = Vdd (4.48)

Iin = Icf + Icbp (4.49)

Ipw = Icf (4.50)

IinIpw

=fsDpwCf∆Vcf + fsDpwαpwCf∆Vcbp

fsDpwCf∆Vcf=Vdd(1 + αpw)− |Vpw|

Vdd − |Vpw|(4.51)

From these results, it is observed in figure 4.5 that the maximum efficiency is drastically reducedbecause of the bottom plate losses. For example, if the bottom-plate parasitic capacitor has acapacitance 40 % the capacitance of the flying capacitor, it is not possible to obtain an outputvoltage below -0.85 V as shown in figure 4.5. This is because the parasitic capacitor is too largeand too much energy is wasted, thus, there is no enough energy at the flying capacitor to chargethe output. In the RBB generator the ratio of the input over output current when the P-well isbeing charged is:

αpw =7.2 pF

97.3 pF= 0.074 (4.52)

Vdd = 1.2 V (4.53)

Vpw = −1.04 V (4.54)

IinIpw

= 1.56 (4.55)

ideally, without any kind of losses, for a switched-capacitor inverter this ratio should be 1 asexplained in the section 1.2. Having a ratio of the input over output current of 1.56 implies that

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Figure 4.5: SCPC efficiency versus P-well voltage fordifferent bottom plate parasitics.

Figure 4.6: SCPC with a bottom plate parasitic ca-pacitor for phases AN.

if the P-well current is 100 nA, the input current will be 156 nA. If there were no bottom-platelosses the input current would be 100 nA (Ideally, Iin/Ipw = 1, as explained in section 4.2.2).

For the N-well the bottom plate losses can be analyzed in the same way. During phase N theparasitic capacitor is charged to Vnw and it is discharged in phase A to Vdd as depicted in figure4.6. Therefore, the ratio of input and output current is:

∆Vcf = 2Vdd − Vnw (4.56)

∆Vcbp = Vnw − Vdd (4.57)

Iin = 2Icf − Icbp (4.58)

Inw = Icf − Icbp (4.59)

IinInw

=2fsDnwCf∆Vcf − fsDnwαnwCf∆VcbpfsDnwCf∆Vcf − fsDnwαnwCf∆Vcbp

=Vdd(4 + αnw)− Vnw(2 + αnw)

Vdd(2 + αnw)− Vnw(1 + αnw)(4.60)

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Figure 4.7: SCPC efficiency versus N-well voltage fordifferent bottom plate parasitics.

As depicted in figure 4.7, the efficiency is also drastically reduced in case of the bottom plate lossesaffect the charging process of the N-well. In this case the input current over the output current is:

αnw =9.7 pF

98.9 pF= 0.098 (4.61)

Vdd = 1.2 V (4.62)

Vnw = 1.86 V (4.63)

IinInw

= 2.14 (4.64)

Therefore, the ideal efficiency for the RBB generator assuming a 7.4 % bottom plate losses whenthe P-well is charged and a 9.8 % losses when the N-well is charged is:

η =VpwIpw + VnwInw

Vdd(1.56 · Ipw + 2.14 · Inw)= 58% (4.65)

As depicted in figure 4.5 and 4.7 the bottom plate parasitics determine the maximum efficiency andalso the maximum output voltage of the converter. From this analysis it is concluded that becausebottom plate parasitics obtaining ideal conversion ratios is impossible. It should be noticed thatthis formula does not take into account the control logic current losses and the gate leakage losses.If all the losses are added the results are the same as the ones obtained by simulation.

The actual losses because of the bottom plate capacitor are actually higher than the analyticalresults show. This is because in the analysis it is assumed a constant ∆V across the flying capacitorbut in reality that is not true. After every charge process the ∆V becomes smaller because thebuffer capacitor is getting charged, therefore, the difference between the output and input alsobecomes smaller. As a consequence, less charge is transferred to the output but the parasiticcapacitor is charged at the same ∆V ; Vdd for the P-well and Vnw − Vdd for the N-well. Theparasitic losses remain the same but the transferred energy is reduced. Hence, the ratio Iin/Ipw(Iin/Inw) gets increased as well as the losses.

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As an example, from the simulation results, when charging the P-well the average ∆V of the flyingcapacitor is 135 mV (ideally it should be Vdd − Vpw) and at the parasitic capacitor the ∆V is1.2 V. When charging the N-well the the ∆V of the flying capacitor is 442 mV (ideally shouldbe 2Vdd − Vnw) and at the parasitic capacitor the difference is 0.83 V. With this data the ratioof current for the P-well and the N-well are Iin/Ipw = 1.66; Iin/Inw = 2.23). Then, the gate-leakage current needs to be added. From the simulation results, during 14 charge cycles the P-wellis charged 13 times and the N-well is charged just one time. Therefore, it is assumed that thetotal gate-leakage current is divided in 13/14 for the P-well and in 1/14 for the N-well, that is,IleakP = 19.4 nA for the P-well and IleakN = 1.5 nA for the N-well. With this information theefficiency of the RBB generator would be:

η =VpwIpw + VnwInw

Vdd(1.66 · Ipwtotal + 2.23 · Inwtotal)(4.66)

η =VpwIpw + VnwInw

Vdd(1.66 · (Ipw + Ilogicpw + IleakP ) + 2.23 · (Inw + Ilogicnw + IleakN ) + Ilogicdd)= 34% (4.67)

which is very close to the results obtained by the simulation. Ipw and Inw are the output currentsdefined by the load. Ipwtotal

and Inwtotalare the currents taken from the output of the SCPC

including the output currents. Ilogicpw (12 nA) and Ilogicnw (9 nA) are the currents taken from theoutput of the SCPC to supply the level-shifters and the comparators. Ilogicdd is the current takenfrom the 1.2 V to supply the control logic.

4.2.3 Improvement Proposals

If the SCPC has bottom plate parasitic losses, as seen in figures 4.5 and 4.7, the efficiency getsreduced once the output voltage reaches the ideal conversion ratio voltage. As seen in figure 4.5,which corresponds to the inverter output of the SCPC for the P-well, the efficiency gets reducedwhen the output approaches the ideal output voltage, in this case -1.2 V. That is because whenthe output voltage reaches the ideal, the ∆V at the flying capacitor is reduced but the ∆V at theparasitic capacitance remains the same. This can be observed at figure 4.4 and in the equations4.47 and 4.48.

The control loop of the improved RBB generator charges the wells during five clock periods, oneperiod after the other. Regarding only the P-well output for simplicity, that means the P-wellvoltage decreases after every charge cycle, hence, after a new charge cycle the ∆V of the flyingcapacitor is reduced and the output voltage gets closer to its ideal value (-1.2 V). Thus, theefficiency is reduced as depicted in figure 4.5.

In principle, it would be possible to increase the efficiency if the ∆V of the flying capacitor is keptat its optimum value while the same average output voltage is maintained. That would implya higher switching frequency but a lower duty-cycle, therefore, the effective switching frequencywould be the same, as well as the average output voltage. For example, in the case of the P-welloutput, that would mean to charge the P-well more frequently but with a duration of a chargecycle of one clock period instead of five as in the current design. Because of that, the ∆V of theflying capacitor would be kept approximately constant and the efficiency would be increased.

This concept is the same as the one explained at the end of the previous section. As explainedbefore, the analytical calculation of the efficiency gives better results than the simulated efficiencydue to the assumption of a constant ∆V at the flying capacitor, but in practice that is not true.The ∆V of the flying capacitor varies after every charge cycle as well as the ∆V of the outputvoltage, approaching the ideal output voltage and hence reducing the efficiency, as shown in figure4.5.

This problem can be analyzed using a mathematical analogy in order to make it more clear. Forexample, an average value of 1 (using two numbers) can be obtained from multiple ways, (0.5 +

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1.5)/2 = 1, (0.9 + 1.1)/2 = 1, etc. Assuming that having values closer to 1 is more efficient, itwould be better to obtain an average value of 1 using (0.9 + 1.1)/2 = 1 rather than (0.5 + 1.5)/2= 1 since 0.9 and 1.1 are closer to 1. This is equivalent for the output voltages of the SCPC, itmight be more efficient to obtain a certain average output voltage value having the ∆V of theflying capacitor closer to its optimum value.

To summarize, in principle it would be possible to improve the efficiency having a flying capacitorwith its ∆V closer to its optimum value, as explained before. The optimum value for the ∆V of theflying capacitor depends on the required average output voltage and the amount of bottom-platelosses. Therefore, depending on the application this solution might be not feasible or not worthyimplementing.

The implementation of this solution is not considered for two reasons. First, the power savingsusing this solution are not significant since the ∆V of the flying capacitor is already close to itsoptimum value and second, the implementation of this solution implies the re-design of the controlloop. The re-design of the control loop is not considered since the comparators would need to bedesigned from scratch in order set the required ∆V for the flying capacitor. Since this projectis focused in the re-design of the previous RBB generator this option has been discarded for thisversion of the RBB but it may be considered for other versions.

Another option to reduce the bottom plate losses would be to change the technology of the flyingcapacitor, for example a metal-insulator-metal capacitor which has less bottom plate losses. Ofcourse, this option is only feasible if it is available on the CMOS technology to make the chip, andnormally requires more area, due to the low capacitance density of MiM capacitors.

4.3 PVT Characterization

A PVT characterization has been performed in order to ensure that the RBB generator worksfine and it is not a threat for other subsystems across process, voltage and temperature corners.The RBB generator has been simulated with five different process corners, Nominal, FastN-FastP,FastN-SlowP, SlowN-FastP and SlowN-SlowP; with three supply voltages, 1.08 V , 1.2 V and 1.32 V ;and with six different temperatures, −40 C, 0 C, 25 C, 85 C, 100 C and 125 C; giving atotal of 90 simulations.

The results of the PVT characterization are as follows. Figure 4.8 shows the P-well voltage fordifferent process, voltages and temperatures as mentioned above. For temperatures higher than85 C the regulation is quite poor because the converter is not able to deliver the required currentto the output. This application is not intended to work at such a high temperatures but the RBBgenerator needs to behave correctly in order to avoid causing failures to other possible sub-systemsinside the chip. Since the RBB generator is still functional at high temperatures these results aregood enough for the application.

The output voltage at the N-well is depicted in figure 4.9. As seen in the figure the outputregulation is better than in the P-well output mainly because in this case the floating capacitorstores a higher ∆V , and it can deliver more power to the output. It should be noticed that theenergy stored in a capacitor is 1/2 · C ·∆V 2.

Figures 4.10 and 4.11 show the output and input currents of the RBB generator, respectively. Theoutput current graph shows the output currents of the N-well and the P-well. In this case there arethree values for each well and temperature corresponding to the three possible corners; nominal,fast and slow. As seen in the figure the output current can change several orders of magnitudedepending on the corner and the temperature. These values have been obtained from calibratedmodels of the wells. As seen in figure 4.11, the input current will accordingly change several ordersof magnitude to supply the desired output current, which justifies the use of a varying control loopto keep efficiency as high as possible. From the PVT characterization it is concluded that the RBBgenerator performs correctly through the simulated process variations and that is not a thread toothers subsystems.

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Figure 4.8: P-well output voltage for different cor-ners, supply voltages and temperatures. Every groupof symbols corresponds to the different process cor-ners.

Figure 4.9: N-well output voltage for different cor-ners, supply voltages and temperatures.

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Figure 4.10: Output currents of the RBB generatorfor the different corners and temperatures.

Figure 4.11: Input currents for different corners, sup-ply voltages and temperatures.

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Chapter 5

Conclusions

An RBB generator in CMOS 90 nm technology is implemented using a dual output SCPC. Theoutputs of the SCPC are used to generate -1 V for the P-well and 1.86 V for the N-well. Theimproved RBB generator uses a single capacitor to generate both outputs. The control logicdecides which output needs to be charged depending on the output voltage. When both outputsrequest current at the same time the flying capacitor transfers charge at a rate of 50 % duty for eachoutput. The control loop of the RBB generator uses a single-bound hysteretic approach becauseof its simplicity, robustness and reduced power consumption since the output ripple is not critical.

The efficiency of the improved RBB generator has doubled the efficiency (from 15 % to 33 %) ofthe previous design mainly because the LDO has been removed. The main losses of the improvedRBB generator are caused by the bottom plate parasitics and the gate-leakage current of the MOS-capacitor. Regarding the control logic, the comparators are the most power-hungry blocks due totheir continuous time operation. In order to reduce the current consumption of the RBB generatorthis are the main issues to be addressed.

In comparison to traditional SCPC designs, the low-power SCPC do not suffer from the powerconsumption of the switches driver circuitry. Mainly, the losses come from the parasitics of theflying capacitor. The gate-leakage current has been reduced leaving the flying capacitor floatingwhen the converter is not working. Regarding the bottom plate losses not much can be done if it isnot possible to change the technology of the flying capacitor as the state of the art SCPC designsshow.

The implemented RBB generator builds on a previous design re-using many building blocks. Thenew generated blocks have been designed starting from ideal blocks, switches and capacitors andfinishing with components at transistor-level. The RBB generator has been taped-out but at themoment of the writing the chip has not returned from the factory, therefore, measurements of thechip are not available.

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[3] Kaushik Roy. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer cmos circuits. Proceedings of the IEEE, VOL. 91, NO. 2, February 2003.

[4] Robert W. Brodersen Anantha P. Chandrakasan. Minimizing power consumption in digitalcmos circuits. PROCEEDINGS OF THE IEE, VOL. 83, NO. 4, APRIL, 1995.

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[10] K.M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S.K.-H. Fung, J.X. An, B. Yu, and C. Hu. Bsim4gate leakage model including source-drain partition. In Electron Devices Meeting, 2000. IEDM’00. Technical Digest. International, pages 815–818, 2000.

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Technical Note: Implementation of an Ultra Low-Power