Teaching VLSI Design Considering Future Industrial Requirements

Matthias Hanke2010-05-10

Outline

1. Introduction2. Lecture3. Tutorial4. Lab5. Conclusion

2

Industrial Requirements

• Theoretical knowledge Semiconductor physics Wire lenght‘s signal influence Circuit design Synthesis mechanisms

• Practical experience Hardware description Electronic design automation (EDA) tools

TheoryTheory

PracticePractice

3

Course Concept

• Professorship sponsored by Intel Education Initiative

Lecture Tutorial Laboratory(2 s/w) (1 s/w) (3 s/w)

4

• Theory• Basic knowledge

• Practice• Calculations

• Practice• Tools

Lecture Overview

• Teaches the theoretical basics• 2 sessions per week• Manufacturing cost aspects• Semiconductor materials and devices• MOS Transistor physics and structure• Wire delays• Manufacturing process• CMOS inverter and gates• Design methodologies• Reconfigurable devices• Test and self-test methods

5

Tutorial Overview

• Offers exercises to theoretical topics from the lecture• Practical problems motivate participants• 1 session per week

6

Silicon

• Calculation of chip yield and cost• Construction of the transistor plot

7

IDS

VDSVGS-VT

VDS < VGS - VT VDS > VGS - VT

)2

)((2

DSDSTGSnD

VVVVkI 2)(

2 tGSn

D VVk

I

Logic

• Logic equations, transistor-level schematics and stick diagrams

• Modeling wires by Elmore Delay• Logical effort notation for path and gates

8

VDD

VSS

output

A

B

C

D

A B C D

1

2

3

nor4

VDD

VSS

A B C D

1 2 3

output

nmos

pmos

Laboratory Overview

• Teaches the handling of tools• 3 sessions a week• Goes through the complete design process from

RTL to GDSII

9

RTL SimulationRTL Simulation

Gate-Level SimulationGate-Level Simulation

Post-LayoutSimulation

Post-LayoutSimulation

VHDL codeVHDL code

SynthesisSynthesis

Place & RoutePlace & Route

VHDL Core

• VHDL introductory session• Identification of MIPS instructions in a given VHDL core

• Extend 16 Bit core to 32 Bit10

PCPC

MemoryData

Register

MemoryData

Register Sign-ExtendSign-

Extend

ALUOutALUOutAA

BB

MU

XM

UX

0

1

Instruction + Data

Memory

Instruction + Data

Memory

Write Data

Address

Mem Data

Instruction Register

Instruction Register

Instruction[20-16]

Instruction[15-0]

Instruction[25-21]

MU

XM

UX

0

1

MU

XM

UX

0

1

Shift Left 2Shift Left 2

MU

XM

UX

0

3

2

1

ALUALU

Zero

ALU Result

MU

XM

UX

0

1

Instruction[15-11]

Instruction[15-0]

16 Bit 32 Bit

4

Running Programs

11

• Verify extended processor‘s behaviour by wave forms created by given binary program

• Create additional instruction and write own binary program• Compile assembly code to create binary programs

Gate Level

• Gate Level Synthesis for 90nm• Compare 90nm design maximum frequency to 60 and 45nm

• Gate level delay sensitive simulation• Energy consumtion analysis• Scanchain insertion and automatic test pattern generation• Place and route

12

Library Frequency

90nm 450 MHz

60nm 700 MHz

45nm 1.000 MHz

Conclusion

• We meet industrial demands• Theory of lecture is consolidated by practice in tutorial and lab• High practice share motivates students• Course teaches the complete design process

13

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Questions