Embed Size (px)
Citation preview
Teaching Functional Verification
Design Automation Conference
Sunday, June 9, 2002
Workshop Goals Share experiences in teaching
functional verification Initiate collaborative efforts to
extend the teaching of functional verification
Expand Computer Engineering curriculums to include functional verification
Agenda Workshop Overview Textbook Overviews Course Organization and
Management Lab Exercise Overview Automated Testbench Concepts Formal Verification and Rulebase
Why is verification so important to the chip industry?
Verification is the single biggest lever to effect the triple constraints: Schedule, Cost, & Quality Fewer revs through the fabrication process
means lower costs and faster time-to-market Re-spinning a chip costs:
Hundreds of thousands of dollars 6-8 weeks
So if you can get it right in fewer "passes", you WIN!!!
What Industry Has Found The system and chip industry
depends on functional verification There’s a science and
methodology behind verification Verification has a separate career
path from logic and circuit design
Course Evolution IBM internal class
Initial 2 day class with 1 lab Current 2 week (80 hour) format
University Partnerships followed initial course
University Participation Penn State, Pittsburgh and North
Carolina State have completed full semester courses on functional verification
Active class at Ohio State (quarters)
There’s now a foundation of resources for other university professors to build upon
Notes: Web address:http://www.cse.psu.edu/~vijay/verify/instructors.html
Open to university professors doing verification classwork.Industry access granted for adding to body of knowledge.
Tool/Vendor specifics Universities should take advantage of any
current vendor agreements they have Materials are “vendor agnostic”
Simulation engines, Specman, VERA Recognition for all slides must be
maintained
Contacts Vijay Narayanan, PSU ([email protected]) (Web page
owner) Steve Levitan, Pitt ([email protected]) John Goss, NCSU ([email protected]) Bruce Wile, IBM ([email protected]) Matthew Morley, Verisity’s University partnerships (
[email protected] Yaron Wolfsthal, IBM’s Rulebase ([email protected]) Janick Bergeron, Qualis Corp, “Writing Testbenches”
textbook, & Verification Guild Newsletter ([email protected])
Faisal Haque, Cisco, “Art of Verification” textbook ([email protected])
Blank page for your notes
Blank page for your notes
