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TAU 2014 Contest and more … Igor Keller

TAU2014$ - International Symposium on Physical …9 CombinaJonal$Logic $ Clock$Path$(CP) Data$Path$(DP) IN $ Launching)FF 1 Capturing)FF 2 OUT D CK$ CLOCK $ Test$ SequenLal$Timing$Analysis$

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Page 1: TAU2014$ - International Symposium on Physical …9 CombinaJonal$Logic $ Clock$Path$(CP) Data$Path$(DP) IN $ Launching)FF 1 Capturing)FF 2 OUT D CK$ CLOCK $ Test$ SequenLal$Timing$Analysis$

TAU  2014  Contest  and  more  …  

Igor  Keller  

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TAU  2014:    Timing  Workshop  n  STA  and  related  areas  

¨ Analog  circuits  …  also  related  

n  Right  forum  for  top  STA  experts  n  Covers  both  mainstream  and  controversial  topics  n   Goals:  

¨   Re-­‐discover  STA  ¨   Bring  STA  science  to  design  houses  ¨   Bring  design  experience  to  academics  and  EDA  ¨ Exchange  ideas  and  build  networking  ¨ EnLce  students  to  stay  in  EDA  ¨ Have  fun  …  

2  

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Technical  Program  n   48  registered  aQendees  n  EDA,  design  houses,  foundries,  academia  

¨ Altera,  IBM,  Intel,  Cisco,  Qualcomm,  Broadcom,  ADI,  TI,  Oracle,  ARM,  Swatch  group,  Samsung,  TSMC,  NVIDIA,  Cadence,  Synopsys  

¨ 8  universiLes    ¨ Countries:  Switzerland,  Greece,  Ireland,    Netherlands,  Taiwan,  Japan,  Korea,  USA  

n  6  technical  sessions  squeezed  into  2  days  n  17  papers  (2  invited)  n  2  emoLonal  panel  discussions  n  Timing  Contest:    8  teams  

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4  TAU  2014  Workshop  –  March  6th-­‐7th,  2014  

The  TAU  2014  Contest  

Removing  Pessimism  during  Timing  Analysis  

Sponsors:  

Igor  Keller  Cadence  

Jin  Hu  IBM  Corp.  

[Speaker]  

Debjit  Sinha  IBM  Corp.  

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5  

Past  and  Present  Timing  Contests  

Previous  Contests  

Guided  awareness  of  challenging  projects  at  earlier  academic  stages  

Facilitate  infrastructure/benchmarks  for  future  research  Encourage  novel  parallelizaLon  techniques  (including  mulL-­‐threading)  

Goal  of  Coordinated  Academic-­‐Industry  Contests  

Develop  Clever  Methods  for  Solving  Difficult  Problems  

Allow  algorithm  development  through  focused  problem  statement  Gain  insight  from  other  perspecLves  and  approaches  

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6  

Focused  Problem  Statement  

Develop  an  algorithm  to  perform  

   

Common  Path  Pessimism  Removal    CPPR  

 

during  Lming  analysis  CPPR:  the  process  of  removing  inherent  but  arJficial  pessimism  from  Jming  tests  and  paths  

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7  

CPPR  Relevance  

Sinha  et  al.  [TAU  2013]  

Line-­‐edge  roughness  

Metal  thickness  (CMP)  Random  dopant  effects  (Vt)  

Manufacturing  VariaLons  

From  cycle  to  cycle  

Voltage  &  Temperature  VariaLons  Across  surface  of  chip  

Variability  causes  many  sources  of  Mming  uncertainty  

Difficult  to  accurately  and  quickly  model  for  all  variaJon  sources  

Create  lower  (early)  and  upper  (late)  delay  bounds  [lb,  ub]  

CPPR  prevents  over-­‐opLmizaLon  of  design  due  to  false  Mming  fails  

Electrical  Effects  

Simultaneous  signal  switching  PotenLal  coupling  noise  

*Global  chip-­‐to-­‐chip  variaJons  

Commonly  found  by  deraLng  original  delay,  e.g.,  ±5%  Any  unknown,  difficult-­‐to-­‐model  effect  can  be  accounted  for  

Bad        news:  addiLonal  pessimism  introduced  (unnecessary)  Good  news:  addiLonal  pessimism  introduced  (desirable  for  safe  chip  operaLon)  

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8  

CombinaJonal  Logic  

SequenLal  Timing  Analysis  

Clock  Path  (CP)  

Data  Path  (DP)  

OUT  Capturing  FF2  Launching  FF1  IN  

D  

CK  CLOCK  

Test  

Details  provided  in contest_education.pdf

Timing  tests  are  checked  against  data  pin  D  and  clock  pin  CK  of  FF  

slackHOLD = at (D) – at (CK) – tHOLD

Hold      Tests  (Same  Cycle)   [data  must  be  stable  tHOLD    Jme    a^er    clock  arrives]  

hold  Jme  pre-­‐CPPR  slack   arrival  Jme  at  D  

arrival  Jme  at  CK  

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9  

CombinaJonal  Logic  

Clock  Path  (CP)  

Data  Path  (DP)  

OUT  Capturing  FF2  Launching  FF1  IN  

D  

CK  CLOCK  

Test  

SequenLal  Timing  Analysis  

Clock  Path  (CP)  

Data  Path  (DP)  

Details  provided  in contest_education.pdf

Timing  tests  are  checked  against  data  pin  D  and  clock  pin  CK  of  FF  

Signal  cannot  be  both  early  and  late  in  common  porJon  à  This  is  inherent  but  arLficial  pessimism  

slackHOLD = at (D) – at (CK) – tHOLD

Hold      Tests  (Same  Cycle)   [data  must  be  stable  tHOLD    Jme    a^er    clock  arrives]  L E

hold  Jme  pre-­‐CPPR  slack   early  arrival  Jme  at  D  late  arrival  Jme  at  CK  

at  opposite  modes  

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10  

CombinaJonal  Logic  

Clock  Path  (CP)  

Data  Path  (DP)  

OUT  Capturing  FF2  Launching  FF1  IN  

D  

CK  CLOCK  

Test  

Common  Path  Pessimism  Removal   Details  provided  in contest_education.pdf

slackHOLD = at (D) – at (CK) – tHOLD + [at (cp) – at (cp)]

Hold      Tests  (Same  Cycle)   [data  must  be  stable  tHOLD    Jme    a^er    clock  arrives]  

Timing  tests  are  checked  against  data  pin  D  and  clock  pin  CK  of  FF  at  opposite  modes  

hold  Jme  post-­‐CPPR  slack  early  arrival  Jme  at  D  late  arrival  Jme  at  cp  

Signal  cannot  be  both  early  and  late  in  common  porJon  à  This  is  inherent  but  arLficial  pessimism  

L E

late  arrival  Jme  at  CK  

early  arrival  Jme  at  cp  

L E Apply  [Hold    CPPR  credit]  

common  point  (cp)  

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PotenLal  Impact  of  CPPR  CPPR  can  only  improve  test  slacks  (never  overly  opMmisMc)  

Pre-­‐CPPR  Test  Slack  

Post-­‐CPPR  Test  Slack  

no  post-­‐CPPR  slack  worse    than  its  pre-­‐CPPR  slack  

pre-­‐CPPR  slack  =  post-­‐CPPR  slack  

Pre-­‐CPPR      slack  ≈        -­‐55  Post-­‐CPPR  slack  ≈  +275  

*if  done  correctly  

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Why  is  CPPR  Important?  

12  

Slack   Slack  

Timing  opLmizaLon     Power  opLmizaLon  

Slack  

Done!  

CPPR  

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Why  is  CPPR  Difficult?  n  ExponenLal  complexity  n  Analysis  of  graph  for  re-­‐converging  paths  n High  runLme  and  memory  n Grows  fast  with  number  of  clock  nets  in  the  design  

n  Possible  but  not  easy  to  parallelize  n Devil  is  in  the  details  …  

13  

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14  

TAU  2014  Contest  MoLvaLon  

Analysis  is  path-­‐based:  can  have  exponenMal  runMme  à  CPPR  can  be  overly  opLmisLc  if  not  enough  paths  are  considered  ExisLng  literature  and  research  is  limited  

Provide  adequate  documentaLon  à  assumes  no  prior  knowledge  of  Lming  analysis  or  CPPR  

CPPR  Challenges  

*not  accounJng  for  holidays  Timeline  spans  roughly  2.5  months  

Simplify  input  /  output  processing  à  focus  on  algorithm  development  and  performance  opLmizaLons  

Limited  to  determinisJc  Jming  (no  staJsJcal)  

Contest  /  Topic  Scope  

Lessons  Learned  from  Previous  Contests  

Only  Hold  +  Setup  tests  considered  No  latches  (flush  segments)  considered  Limited  design  topologies,  e.g.,  clock  tree  reconvergence  

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15  

RunMme  (relaMve)  

From  TAU  2013  

TAU  2014  Contest  Guidelines  

EvaluaLon  Pre-­‐processing   Provided  to  Contestants  

*Industrial  tool  

Design  Library  

TAU  2013  Benchmarks  

Detailed  DocumentaMon  

Path-­‐based    CPPR  Output  

Golden  Result*  

Delay  File  

Delay  Converter  Phase  1  

Industrial  Tool  Phases  2  and  3  

Timing  File  

Topology,  tests,  etc.  

AsserJons,  etc.  

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16  

FF3  

FF2  

FF1  

CLOCK  

IN2  

OUT  

IN1  

B1  

B2  

B4  B3  

OR2  

FF  

QD

CK  

Setup  Hold  

B  OR2  

B  

AY A   Y

Primary  Output  

Timing  Arc  

Timing  Test  

Primary  Input  

Inputs:  Delay  File  

output OUT input IN1 input IN2 input CLOCK

Specifies  primary  inputs  and  outputs  

Provides  setup  and  hold  Lmes  for  every  data-­‐to-­‐clock  Lming  test  Provides  early  and  late  propagaLon  delay  for  every  source-­‐to-­‐sink  Lming  arc  

OR2:A OR2:Y 5e-11 5e-11

late    delay  

source  

early    delay  

sink  

setup FF3:D FF3:CK 3e-11

test  type   test  Jme  

clock  pin  data  pin  

Setup  

Details  provided  in contest_file_formats.pdf

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17  

FF3  

FF2  

FF1  

CLOCK  

IN2  

OUT  

IN1  

B1  

B2  

B4  B3  

OR2  

FF  

QD

CK  

Setup  Hold  

B  OR2  

B  

AY A   Y

Primary  Output  

Timing  Arc  

Timing  Test  

Primary  Input  

Inputs:  Timing  File  Provides  early  and  late  arrival  Lmes  for  each  primary  input  Provides  clock  period  for  the  clock  source  

at IN1 0e+0 1e-11

late  at  early  at  

Primary  Input  

clock CLOCK 1.2e-10

clock    period  

clock    pin  

Details  provided  in contest_file_formats.pdf

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18  

Benchmarks  Added  more  complex  (randomized)  clock  tree  

BRANCH(CLOCK,  iniJal  FF)  

BRANCH(src,sink):  create  buffer  chain                                                                                  from  src  to  sink

Select  random  locaLon  L  in  current  tree  For  each  remaining  FF  

BRANCH(L,FF)  

Phase  3  (EvaluaLon)  

[8.2K  to  109.6K  Tests]  

Phase  1  [6-­‐42  Tests]  

Phase  2  [380-­‐50.1K  Tests]  

Based  on  TAU  2013  v2.0    benchmarks  (openCore)  

Based  on  TAU  2013  v1.0    benchmarks  (sequenJal  circuits)  

Phase  2  Benchmark  

Phase  2  Benchmark  

Phase  2  Benchmark  

FF  

CLOCK  

FF   FF  

L1  

L2  

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19  

Setup  

FF3  

FF2  

FF1  

CLOCK  

IN2  

OUT  

IN1  

B1  

B2  

B4  B3  

OR2  

FF  

QD

CK  

Setup  Hold  

B  OR2  

B  

AY A   Y

Primary  Output  

Timing  Arc  

Timing  Test  

Primary  Input  

Output  File  Requires  pre-­‐CPPR  and  post-­‐CPPR  slacks  for  each  test  and  path  Controllable  opLons:  <testType> -numTests <int> -numPaths <int>

[number  of  paths  per  test]  [setup/hold/both]   [number  of  tests]  

[a^er  CPPR]  [Jming  analysis]  

setup -3e-11 -1e-11 1

-numPaths test  type  

post-­‐CPPR  test  slack  

pre-­‐CPPR  test  slack  

post-­‐CPPR  path  slack  

pre-­‐CPPR  path  slack  

path  length  

-1.5e-11 -1e-11 10

FF3:D OR2:Y OR2:A FF2:Q FF2:CK B3:Y B3:A B1:Y B1:A CLOCK

pin-­‐to-­‐pin  data  path  from:  data  pin  of  test  to:            primary  input  

Details  provided  in contest_file_formats.pdf

contest_rules.pdf

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20  

EvaluaLon  Metrics  

Test  t  Slack  Accuracy  A(t)  

Post-­‐CPPR  test  slack  Pre-­‐CPPR  test  slack  

Correctness  of  path  

Path  p  Slack  Accuracy  A(p)  Pre-­‐CPPR  path  slack  Post-­‐CPPR  path  slack  

Slack  Accuracy  (Difference)  

[0,1] ps 100 (1,3] ps 80 (3,5] ps 50 (5, ) ps 0

T:  set  of  all  tests  in  D  P:  set  of  all  paths  in  D  

Average  of  A(dp(t))  for  all  tests  t  in  T,  where  dp(t)  is  the  criLcal  path  of  t  

(Raw)  Testcase  D  Accuracy  A(D)  

Minimum  of  {A(t)}  for  all  tests  t  in  T  A(critT),  where  critT  is  the  most  criLcal  test  

Average  of  A(t)  for  all  tests  t  in  T  Average  of  A(p)  for  all  paths  p  in  P  

Overall  Contestant  Score  

Accuracy  (Compared  to  “Golden”  Results)  

RunMme  Factor  (RelaMve)  

Memory  usage  not  considered  

runLme(D)  Average  of  all  contestants  

RF(D)  =  

Composite  Testcase  Score  score(D)  =  A(D)      (0.5  +  0.5      RF(D))  

Average  of  score(D)  for  all  designs  

First  three  considers  overall  tool  quality;  Last  two  considers  worst  tool  quality  

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21  

TAU  2014  Contestants  University   Country   Team  Name  

NaLonal  Chiao  Tung  University   Taiwan   iTimerC  

University  of  Thessaly   Greece   The  TimeKeepers  

NaLonal  Tsing  Hua  University   Taiwan   TTT  

India  InsLtute  of  Technology,  Madras   India   ElecEnthus  

University  of  Illinois  at  Urbana-­‐Champaign   USA   UI-­‐Timer  

India  InsLtute  of  Technology,  Madras   India   LightSpeed  

Missouri  University  of  Science  and  Technology   USA   MST_CAD  

Peking  University   China   PKU-­‐HappyTimer  

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Contestant  Performance  

Normalized  Average  Performance  

0.5  

1  

0  

Overall  quality  of  submi\ed  binaries  was  superb  

For  each  Combo  benchmark,  used  4  seungs:  

Ex:  Combo7 -setup -numTests 35000 -numPaths 1

EvaluaJon  Machine:  8X  Intel(R)  Xeon  CPU  E7-­‐8837  @2.67GHz

One  testcase  comprised  of  <benchmark,testType,-numTests,-numPaths>  à  24  total

6  of  7  final  submissions  used  8  threads  [maximum  allowed];  1  of  7  final  submissions  used  2  threads  

-numTests N –numPaths 1 -numTests n –numPaths m

-setup -hold

n  <  N  <  50K,  m  <  20  

6  of  7  final  submissions  had  full  accuracy  on  12  designs  5  of  7  final  submissions  had  no  crashes;  1  of  7  crashed  on  only  5  testcases  

Team   C1   C2   C3   C4   C5   C6  

*Final  evaluaJon  is  design-­‐specific,  not  based  on  total  runJme  or  overall  averages  

RunLme  Factor  

Raw  Accuracy  

Total  RunLme  (hours)   6.27   4.27   1.44   7.8   4.96   2.42  

Worst  

Best  

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23  

Acknowledgments  

Special  Thanks  to  the  TAU  2014  Contestants  

Jobin  Kavalam,  NiLn  Chandrachoodan  [IITimer  from  TAU  2013]        Provided  Jmer  source  code,  helped  with  iniJal  input  file  conversions  

Jin  Hu  (IBM),  Debjit  Sinha  (IBM)  ,  Chirayu  Amin  (Intel)  

This  contest  would  not  have  been  successful  without  your  hard  work  and  dedicaJon  

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Winners

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TAU  2014  Timing  Contest    Removing  Common  Path  Pessimism  

Third  Place  Award  Presented  to  

Yu-­‐Ming  Yang,  Yu-­‐Wei  Chang  and  Iris  Hui-­‐Ru  Jiang  

NaLonal  Chiao  Tung  University,  Taiwan  

For  iTimerC  

Jin  Hu  Contest  Chair  

Chirayu  Amin  General  Chair  

Igor  Keller  Technical  Chair  

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TAU  2014  Timing  Contest    Removing  Common  Path  Pessimism  

Honorable  MenHon  Presented  to  

University  of  Thessaly,  Greece  

For  The  TimeKeepers  

Jin  Hu  Contest  Chair  

Chirayu  Amin  General  Chair  

Igor  Keller  Technical  Chair  

Christos  Kalonakis,  Charalampos  Antoniadis,  PanagioLs  Giannakou,    Dimos  Dioudis,  George  Pinitas  and  George  Stamoulis  

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TAU  2014  Timing  Contest    Removing  Common  Path  Pessimism  

Second  Place  Award  Presented  to  

M  S  Santosh  Kumar  and  Sireesh  N  

IIT  Madras,  India  

For  LightSpeed  

Jin  Hu  Contest  Chair  

Chirayu  Amin  General  Chair  

Igor  Keller  Technical  Chair  

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TAU  2014  Timing  Contest    Removing  Common  Path  Pessimism  

First  Place  Award  Presented  to  

Tsung-­‐Wei  Huang,  Pei-­‐Ci  Wu  and  MarLn  D.  F.  Wong  

University  of  Illinois  at  Urbana-­‐Champaign,  USA  

For  UI-­‐Timer  

Jin  Hu  Contest  Chair  

Chirayu  Amin  General  Chair  

Igor  Keller  Technical  Chair  

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Thank  you!  

29  

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Backup  

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Contest  Timeline  

Date   AcMvity  10/13/2013   Contest  release  date  

https://sites.google.com/site/taucontest2014

•   Timing  analysis  and  CPPR  tutorial  [contest_education.pdf]  •   Contest  overview  and  guidelines  [contest_rules.pdf]  •   Contest  input  and  output  specificaLons  [contest_file_formats.pdf]  •   Source  code  from  the  winners  of  TAU  2013  Contest  (IITimer)  

11/22/2013  –  12/02/2013  –  01/06/2014  

End  of  contest  registraLon  •   Phase  1  Benchmark  Set  [9  testcases]  •   Phase  2  Benchmark  Set  [6  testcases]  

01/15/2014   Alpha  binary  submission  

02/01/2014  [~2.5  months]  

Final  binary  +  short  report  submission  

03/07/2014   Winners  announced  (today!)  

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CombinaJonal  Logic  

Clock  Path  (CP)  

Data  Path  (DP)  

OUT  Capturing  FF2  Launching  FF1  IN  

D  

CK  CLOCK  

Test  

Common  Path  Pessimism  Removal   Details  provided  in contest_education.pdf

slackSETUP = at (CK) + P – at (D) – tSETUP + [delay (OL) – delay (OL)]

slackHOLD = at (D) – at (CK) – tHOLD + [at (cp) – at (cp)]

Setup  Tests  (Next  Cycle  with  clock  period  P)  

Hold      Tests  (Same  Cycle)  

[data  must  be  stable  tSETUP  Jme  before  clock  arrives]  

[data  must  be  stable  tHOLD    Jme    a^er    clock  arrives]  

L E L E

Timing  tests  are  checked  against  data  pin  D  and  clock  pin  CK  of  FF  at  opposite  modes  

setup  Jme  post-­‐CPPR  slack   clock    period  

hold  Jme  post-­‐CPPR  slack  early  arrival  Jme  at  D  late  arrival  Jme  at  cp  

early  arrival  Jme  at  CK  

Signal  cannot  be  both  early  and  late  in  common  porJon  à  This  is  inherent  but  arLficial  pessimism  

L E

late  arrival  Jme  at  CK  

early  arrival  Jme  at  cp  

Apply  [Setup  CPPR  credit]  

L E

late  arrival  Jme  at  D  

early  delays  of  CP  and  DP  overlap  

late  delays  of    CP  and  DP  overlap  

Apply  [Hold    CPPR  credit]  

common  point  (cp)  

OL = CP ∩ DP