Systems Architecture II - Drexel University

Lec 2 Systems Architecture II 1

Systems Architecture II

TopicsOverview of Pipelining*

Pipelined Datapath and Control*

Notes Courtesy of Jeremy R. Johnson

*This lecture was derived from material in the text (Chap. 6).

Notes Courtesy of Jeremy R. Johnson



Topic 1: Overview of Pipelining


Introduction• Objective: To understand pipelining and the enhanced

performance it provides

• Pipelining is an implementation technique in which multiple instructions are overlapped in execution. Instructions are broken down into stages and while one instruction is executing one stage another instruction can simultaneously execute another stage.

• Topics– Introduction to pipelining– Speedup– Designing instruction sets for pipelining– Pipelining hazards– Superscalar and dynamic pipelining


A Simple Example

• Stages in laundry example– wash clothes– dry clothes– fold clothes– put clothes away

• Same time to complete single load• Speedup requires multiple loads

– While drying the first load, one can begin washing the second load– When the first load is being folded the second load can be dried while

a third load begins– When the clothes from the first load are being put away four loads are

operating simultaneously– With sufficiently many loads the time is reduced by a factor of 4


Timing DiagramTime

76 PM 8 9 10 11 12 1 2 AM

A

B

C

D

Time76 PM 8 9 10 11 12 1 2 AM

A

B

C

D

Task�order

Task�order


Pipeline Stages for MIPS Instruction Execution

• There are five stages:

– Fetch instruction from memory– Read registers while decoding the instruction– Execute operation or calculate an address– Access an operand in data memory– Write result into a register

• Delays for functional units

– 2 ns for memory access– 2 ns for ALU operation– 1 ns for register file read/write


Pipelined Execution for Single-cycle MIPS Implementation

• Instructions: lw, sw, add, sub, and, or, slt, beq

Instruction Class Inst Fetch Reg. Read ALU op Data Acce Reg Write TotalLoad word (lw) 2 ns 1 ns 2 ns 2 ns 1 ns 8 nsStore word (sw) 2 ns 1 ns 2 ns 2 ns 7 nsR-format (add,sub, and, or, slt) 2 ns 1 ns 2 ns 1 ns 6 nsBranch (beq) 2 ns 1 ns 2 ns 5 ns


Timing Diagram

Instruction�fetch Reg ALU Data�

access Reg

8 ns Instruction�fetch Reg ALU Data�

access Reg

8 ns Instruction�fetch

8 ns

Time

lw $1, 100($0)

lw $2, 200($0)

lw $3, 300($0)

2 4 6 8 10 12 14 16 18

2 4 6 8 10 12 14

...

Program�execution�order�(in instructions)


access Reg

Time

lw $1, 100($0)

lw $2, 200($0)

lw $3, 300($0)


access Reg


access Reg

2 ns 2 ns 2 ns 2 ns 2 ns

�



Speedup

• Time = (Startup + Number of operations) X time/stage= (Number of stages + Number of operations - 1)

X time/stage

• Speedup = non-pipelined time/pipelined timeIf sequential time = time/stage X number of stages

Speedup = SNt/(S + N-1)t ≈ S,

where S = number of stagesN = number of operationst = time/stage


Designing Instruction Sets (MIPS) for Pipelining

• Want to break down instruction execution into a reasonable number of stages of roughly equal complexity

• All instructions the same length– easier to fetch and decode

• Few instruction formats (source register fields are located in the same place)

– can begin reading registers at the same time instruction is decoded• Memory operands appear only in loads and stores

– calculate address during execute stage and access memory following stage - otherwise expand to addr stage, mem stage and exec stage

• Operands must be aligned in memory– don’t have to worry about a single data transfer instruction requiring

two data memory accesses; hence, it requires a single pipeline stage


Pipeline Hazards

• Situations in pipelining when the next instruction cannot execute in the following clock cycle

• Structural hazards– hardware can not support the combination of instructions that we

want to execute in the same cycle• Control hazards

– need to make a decision based on the results of one instruction while others are executing

• Data hazards– an instruction depends on a the results of a previous instruction still

in the pipeline


Structural Hazards

• Problem: conflict in resources

• Example: Suppose that instruction and data memory was shared in single-cycle pipeline. Data access conflicts with instruction fetch

• Solution: remove conflicting stages, redesign resources to separate resources, or replicate resources


Control Hazards

• Problem: The next element to go into the pipe may depend on currently executing instruction or we may have to wait until a stage is completed to determine the next stage

• Example: branch instruction

• Solutions:– Stall - operate sequentially until decision can be made (wastes time)– Predict - guess what to do next. If guess correct, operate normally, if

guess is wrong clear the pipe and begin again


Timing Diagram (stall)


access Reg

Time

beq $1, $2, 40

add $4, $5, $6

lw $3, 300($0)4 ns


access Reg2ns


access Reg

2ns

2 4 6 8 10 12 14 16

�

�



Timing Diagram (predict)


access Reg

Time

beq $1, $2, 40

add $4, $5, $6

lw $3, 300($0)


access Reg2 ns


access Reg

�

2 ns



access Reg

Time

beq $1, $2, 40

add $4, $5 ,$6

or $7, $8, $9


access Reg

2 4 6 8 10 12 14

�2 4 6 8 10 12 14


access Reg

2 ns

4 ns

bubble bubble bubble bubble bubble



Delayed Branch

• Always execute the next sequential instruction with the branch taking place after that one instruction delay

• Compiler tries to put instruction in the “branch delay slot” that is always executed independent of branch outcome (compilers typically fill 50% of the branch delay slots)


access Reg

Time

beq $1, $2, 40

add $4, $5, $6

lw $3, 300($0)


access Reg2 ns


access Reg

2 ns

2 4 6 8 10 12 14

�

2 ns

(Delayed branch slot)



Data Hazards

• Problem: Instruction depends on the result of a previous instruction still in the pipeline

• Example:– add $s0, $t0, $t1– sub $t2, $s0, $t3

• Solutions:– forwarding or bypassing– instruction reordering to remove dependencies


Timing Diagram (forwarding)

add $s0, $t0, $t1

sub $t2, $s0, $t3


IF ID WBEX

IF ID MEMEX

Time2 4 6 8 10

MEM

WBMEM

Time2 4 6 8 10 12 14

lw $s0, 20($t1)

sub $t2, $s0, $t3


IF ID WBMEMEX

IF ID WBMEMEX

bubble bubble bubble bubble bubble


Summary• Pipelining increases the number of simultaneously

executing instructions and the rate at which instructions are started and completed.

• Pipelining does not reduce the time it takes to complete an individual instruction

– In the five-stage pipeline, it still takes 5 clock cycles for instructions to complete

• Pipelining improves instruction throughput rather than reducing individual instruction execution time

• Good pipeline design requires an appropriate number of stages of comparable complexity (speedup = number of stages)

• Must cope with structural, control, and data hazards• Techniques include: branch prediction, forwarding, and

stalls


Improving Pipeline Performance• Superpipelining - very long pipelines

• Superscalar - replicate resources so that multiple instructions can execute in the different stages of the pipeline

– issue multiple instructions in the same cycle

• Dynamic pipeline scheduling - dynamically reorder instructions to avoid hazards.

– usually combined with resource replication– lw $t0, 20($s2)– addu $t1, $t0, $t2– sub $s4, $s4, $t3– slti $t5, $s4, 20


Superscalar MIPS• Issue two instructions per cycle

– One ALU operation or branch and one load or store– requires fetching and decoding 64 bits– To simplify, require that the instruction be paired and aligned

PC Instruction�memory

4

RegistersM�u�x

M�u�x

ALU

M�u�x

Data�memory

M�u�x

40000040

Sign�extend Sign�

extend

ALU Address

Write�data


Superscalar Example• Loop: lw $t0, 0 ($s1) # $t0=array element

addu $t0, $t0, $s2 # add scalar in $s2sw $t0, 0($s1) # store resultaddi $s1, $s1, -4 # decrement pointerbne $s1, $zero, Loop # branch $s1 != 0

ALU or branch inst Data transfer inst Clock cycleLoop: lw $t0, 0($s1) 1

addi $s1,$s1,-4 2addu $t0, $t0, $s2 3bne $s1,$zero,Loop sw $t0, 4($s1) 4


Loop Unrolling• Unroll several iterations of the loop to provide additional

work• Introduce additional temporaries to remove artificial

dependencies• Previous example (speedup = 2)

ALU or branch inst Data transfer inst clockLoop: addi $s1,$s1,-16 lw $t0, 0($s1) 1

lw $t1,12($s1) 2addu $t0,$t0,$s2 lw $t2 8($s1) 3addu $t1,$t1,$s2 lw $t3, 4($s1) 4addu $t2,$t2,$s2 sw $t0, 0($s1) 5addu $t3,$t3,$s2 sw $t1, 12($s1) 6

sw $t2, 8($s1) 7bne $s1,$zero,Loop sw $t3, 4($s1) 8


Dynamic Pipeline Scheduling

• Go past stalls to find later instructions to execute while waiting for the stall to be resolved

• Out of order execution• In order completion• Speculative execution (dynamic scheduling + branch

prediction)• Register renaming• Can accomplish automatic loop unrolling


Design of a Dynamically Scheduled Pipeline

Commit�unit

Instruction fetch�and decode unit

…

In-order issue

In-order commit

�

Load/�Store

Floating�pointIntegerInteger …Functional�

unitsOut-of-order execute

Reservation�station






Topic 2: Pipelined Datapath and Control


Introduction• Objective: To understand the modifications to the datapath

and control used in the single cycle implementation of MIPS needed to support pipelining.

• Key idea: Separate datapath into 5 pieces, one for each stage of the pipeline. Add registers between pieces to hold the information specific to the currently executing instruction.

• Note: We will ignore the difficulties due to hazards in this lecture

• Topics– Review of the single cycle implementation of MIPS– Pipelined datapath– Graphical representation of pipelines (multiple and single clock-cycle

pipelining diagrams)– Adding control to the pipelined datapath


Pipeline Stages for MIPS Instruction Execution

• There are five stages:

– IF: Fetch instruction– ID: Instruction decode and register file – EX: Execution or address calculation– MEM: Data memory access– WB: Write back


Single-cycle Datapath

Instruction�memory

Address

4

32

0

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Shift�left 2

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M�u�x

0

1

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0Write�data

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1

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IF: Instruction fetch ID: Instruction decode/�register file read

EX: Execute/�address calculation

MEM: Memory access WB: Write back


Instruction Execution

IM Reg DM RegALU

IM Reg DM RegALU

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7

Time (in clock cycles)

lw $2, 200($0)

lw $3, 300($0)


lw $1, 100($0) IM Reg DM RegALU


Pipeline Registers


Address

4

32

0

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Shift�left 2

Inst

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ion

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ID/EX

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Datapath with Control Signals

PC


Address

Inst

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ion

Instruction�[20– 16]

MemtoReg

ALUOp

Branch

RegDst

ALUSrc

4

16 32Instruction�[15– 0]

0

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IF/ID ID/EX EX/MEM MEM/WB

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ALU Control

Instruction ALUOp Instruction funct ALU ALUopcode operation action controlLW 00 load word xxxxxx add 010SW 00 store word xxxxxx add 010BEQ 01 branch eq xxxxxx sub 110R-type 10 add 100000 add 010R-type 10 sub 100010 sub 110R-type 10 and 100100 and 000R-type 10 or 100101 or 001R-type 10 slt 101010 slt 111


Control Signals• RegDst - register destination number

– if deasserted then rt field (bits 20-16)– if asserted then rd field (bits 15-11)

• RegWrite - write to register file when asserted• ALUSrc - select second input to ALU

– if deasserted then second register file output– if asserted then sign-extended 16 bits of instruction

• PCSrc - select input to PC– if deasserted then PC+4– if asserted then branch target

• MemRead - read from memory if asserted• MemWrite - write to memory if asserted• MemtoReg - select register write data source

– if deasserted then ALU output– if asserted then data memory


Passing Control through the PipelineExecution/Address Calculation

stage control linesMemory access stage

control linesstage control

lines

InstructionReg Dst

ALU Op1

ALU Op0

ALU Src Branch

Mem Read

Mem Write

Reg write

Mem to Reg

R-format 1 1 0 0 0 0 0 1 0lw 0 0 0 1 0 1 0 1 1sw X 0 0 1 0 0 1 0 Xbeq X 0 1 0 1 0 0 0 X

Control

EX

M

WB

M

WB

WB

IF/ID ID/EX EX/MEM MEM/WB

Instruction


Datapath with Control Signals

PC


Inst

ruct

ion

Add


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toR

eg

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Branch

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ALUSrc

4

16 32Instruction�[15– 0]

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0

M�u�x

0

1

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Write�data

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1

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Zero

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1

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e

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6

EX

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M

WB

WBIF/ID

PCSrc

ID/EX

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M�u�x

0

1

Mem

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AddressData�

memory

Address


Example

• lw $10, 20($1)• sub $11, $2, $3• and $12, $4, $5• or $13, $6, $7• add $14, $8, $9




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toR

eg

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Branch

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ALUSrc

4


0

M�u�x

0

1

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EX

M

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M

WB

WB

Inst

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IF/ID EX/MEMID/EX

ID: before<1> EX: before<2> MEM: before<3> WB: before<4>

MEM/WB

IF: lw $10, 20($1)

000

00

0000

000

00

000

0

00

00

0

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0

1

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EX

M


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Inst

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ID: lw $10, 20($1) EX: before<1> MEM: before<2> WB: before<3>

MEM/WB

IF: sub $11, $2, $3

010

11

0001

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00

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00

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X

10

20

X

1


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WB

Inst

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IF/ID EX/MEMID/EX

ID: sub $11, $2, $3 EX: lw $10, . . . MEM: before<1> WB: before<2>

MEM/WB

IF: and $12, $4, $5

000

10

1100

010

11

000

1

00

00

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4

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WB

Inst

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IF/ID EX/MEMID/EX

ID: and $12, $2, $3 EX: sub $11, . . . MEM: lw $10, . . . WB: before<1>

MEM/WB

IF: or $13, $6, $7

000

10

1100

000

10

101

0

11

10

0

00

M�u�x

0

1

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andControl

Registers

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Read�data 2

Read�register 1

Read�register 2

12

X

X

5

4




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$4

X

12

MemRead

Mem

Writ

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$3

$2

11

M�u�x

M�u�x

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10

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Zero

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Clock 4



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4


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Inst

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ion

IF/ID EX/MEMID/EX

ID: or $13, $6, $7 EX: and $12, . . . MEM: sub $11, . . . WB: lw $10, . . .

MEM/WB

IF: add $14, $8, $9

000

10

1100

000

10

101

0

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M�u�x

0

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or

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7

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eg

11

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M


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4

0

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Writ

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WB

Inst

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IF/ID EX/MEMID/EX

ID: add $14, $8, $9 EX: or $13, . . . MEM: and $12, . . . WB: sub $11, . . .

MEM/WB

IF: after<1>

000

10

1100

000

10

101

0

10

00

0

10

M�u�x

0

1

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addControl

Registers

Read�data 1

Read�data 2

Read�register 1

Read�register 2

14

X

X

9

8




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$9

$8

X

14

MemRead

Mem

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$7

$6

13

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M�u�x

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11

11

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Clock 6



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0

1

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Shift�left 2

Reg

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e

MemRead

Control

ALU


Sign�extend

EX

M

WB

Inst

ruct

ion

IF/ID EX/MEMID/EX

ID: after<1> EX: add $14, . . . MEM: or $13, . . . WB: and $12, . . .

MEM/WB

IF: after<2>

000

00

0000

000

10

101

0

10

00

0

M�u�x

0

1

Add

PC

0Write�data

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1

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e

$8

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1

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M

WB

13 12

12$9

14

WB

Mem

toR

eg

10

Read�data 1

Read�data 2

Read�register 1

Read�register 2 Zero

Data�memory

Address

Clock 7


WB

EX

M


Address

Mem

toR

eg

ALUOp

Branch

RegDst

ALUSrc

4

0

0

1

Add Add�result

1

ALU�result

Zero

ALU�control

Shift�left 2

Reg

Writ

e

M

WB

Inst

ruct

ion

IF/ID EX/MEMID/EX

ID: after<2> EX: after<1> MEM: add $14, . . . WB: or $13, . . .

MEM/WB

IF: after<3>

000

00

0000

000

00

000

0

10

00

0

10

M�u�x

0

1

Add

PC

0Write�data

M�u�x

1

Control

Registers

Read�data 1

Read�data 2

Read�register 1

Read�register 2



extend


MemRead

Mem

Writ

e

M�u�x

M�u�x

ALURead�data

14

WB

13

13

Write�register

Write�data

Data�memory

Address

Clock 8


WB

EX

M


Address

Mem

toR

eg

ALUOp

Branch

RegDst

ALUSrc

4

0

0

1

Add Add�result

1

ALU�result

Zero

ALU�control

Shift�left 2

Reg

Writ

e

M

WB

Inst

ruct

ion

IF/ID EX/MEMID/EX

ID: after<3> EX: after<2> MEM: after<1> WB: add $14, . . .

MEM/WB

IF: after<4>

000

00

0000

000

00

000

0

00

00

0

10

M�u�x

0

1

Add

PC

0Write�data

M�u�x

1

Control

Registers

Read�data 1

Read�data 2

Read�register 1

Read�register 2



extend


MemRead

Mem

Writ

e

M�u�x

M�u�x

ALURead�data

WB

14

14

Write�register

Write�data

Data�memory

Address

Clock 9

Documents

Systems Architecture II - Drexel University