National Taiwan UniversityDepartment of Electrical Engineering& Graduate Institute of Electronics Engineering

Date : 2004.6.8

SystemC Study and Modeling of A CPU

魏君任謝宜政 R92943101林家慶 R92943085

2.

Outline

Introduction to SystemC( 林家慶 ) A Simple example with SystemC( 謝宜政 ) Modeling of a CPU( 魏君任 )

3.

Modules Ports

SC_MODULE(fifo) {sc_in<bool> load;sc_in<bool> read;sc_inout<int> data;sc_out<bool> full;sc_out<bool> empty;}

4.

Module Signals

•Signals can be local to a module, and are used to connect ports of lower level modules together.

•These signals represent the physical wires that interconnect devices on the physical implementation of the design.

• Signals carry data, while ports determinethe direction of data from one module to another.

•Signals aren’t declared with a mode such as in, out, or inout.

5.

Positional mapping

6.

Named mapping

7.

Internal Data Storage

8.

Process

Process are the modules that provide functionality and called whenever these signals the process are sensitive to change value.

Processes have sensitivity lists, i.e. a list of signals that cause the process to be

invoked, whenever the value of a signal in this list changes. To trigger a process a signal in the sensitivity list of the process must have an even

t occur. The event on the signal is the triggering mechanism to activate the process. Process

--Method process

--Thread process

--Cthread process

9.

Method process

10.

Thread&Cthread process

Thread Process can be suspended and reactivated. The Thread Process can contain wait() functions that suspend process execution

until an event occurs on one of the signals the process is sensitive to. An event will reactivate the thread process from the statement the process was last

suspended.

------------------------------------------------------------------------------------------------------------------- Clocked Thread Processes are only triggered on one edge of one clock, which

matches the way hardware is typically implemented with synthesis tools.

11.

Thread process example

12.

Constructor

The module constructor creates and initializes an instance of a module. The instance name of the module is passed to the constructor at instantiation

time.

13.

Part2:Transceiver Model

謝宜政

14

Simple SystemC example: Simplex Data Protocol

Timer

Transmit Channel Receive Display

Generates Timeout Events

Generated the packets by a function

Packets

acknowledge

Goal: mapping to expected CPU block

15

Timer

Display

start

Port connect

timeout

tpackin

clock

tpackout

start_timer

Transmit channel

tpackin

rpackintpackout

rpackout

rpackin

Receiver

rpackout

din

dout

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#Include *.h

…………..

Port connect & Data type

Constructor

For initializing

Simple SystemC construct

Implementation:

Method,process,case..

Some Block

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// packet.h file#ifndef PACKETINC#define PACKETINC#include "systemc.h“ struct packet_type {int seq; // identify the sequence number of the packets

int retry; // the number of times the packet has been sent

Define Packet structure

Transmit Channel

Packets

1 2 3 4 5 ………

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Ex: Transmit Module (1)

Portssc_in<packet_type> tpackin; // input portsc_in<bool> timeout; // input portsc_out<packet_type> tpackout; // output portsc_inout<bool> start_timer; // inout portsc_in<bool> clock; // input port

timeout

tpackin

clock

tpackout

start_timer

Transmit

// ConstructorSC_CTOR(transmit) {SC_METHOD(send_data); // Method Processsensitive << timeout;sensitive_pos << clock;framenum = 1; \\ initializes the variablesretry = 0;start = false;buffer = get_data_fromApp();}};

Verilog,VHDL

Reset for initializing

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Get_data_fromApp()

Rand() //random number to generate a new data value to send

Channel

Send_data()1.Check first if timeout is true

2.Check to see if the current value of tpackin is equivalent to the old value

To see if an acknowledgement

Packet was received

If the value differ tpackin ,copy it to local “packin”

else {packin = tpackin;if (!(packin == tpackold)) {if (packin.seq == framenum) {buffer = get_data_fromApp();framenum++;retry = 0;} tpackold = tpackin;

Timer

tpackin

tpackout

Transmit Module (2)

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Architecture

CPU

Instruction Cache

Data Cache

Memory

FPU

DSP

Fetch Decode

Execute

21

Modeling A CPU Using SystemC

魏君任

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Simulation

• Starts by calling sc_start() from sc_main().• sc_start(-1): A negative value to this function

makes the simulation to continue indefinitely.• Stop by calling sc_stop().• Calling sc_simulation_time() to determine the

current time during simulation.• Debuging: The value printed is the current val

ue, not a value just written to it.

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Asynchronous event

clock = 1;sc_cycle(5);reset = 1;sc_cycle(5);

:

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Asynchronous event

clock = 0;sc_cycle(5);clock = 1;sc_cycle(10);reset = 0;sc_cycle(5);

25

Tracing Waveforms

• File formats: VCD, WIF and ISDB.• VCD file:

sc_trace_file * my_trace_file;my_trace_file = sc_create_vcd_trace_file (“file_name”);

:sc_close_vcd_trace_file (my_trace_file);

• WIF file:sc_trace_file * my_trace_file;my_trace_file = sc_create_vcd_trace_file (“file_name”);

:sc_close_wif_trace_file (my_trace_file);

26

Tracing Variables and Signals of Aggregate Type

struct bus {unsigned address;bool read_write;unsigned data;

}

void sc_trace(sc_trace_file *tf, const bus& v, const sc_string& NAME){

sc_trace(tf, v.address, Name + “.address”);sc_trace(tf, v.read_write, Name + “.rw”);sc_trace(tf, v.data, Name + “.data”);

}

• Traces the data structure by tracing individual fields of the structure.

27

Tracing Variable and Signal Array

void sc_trace(sc_trace_file *tf, sc_signal<int> *v, const sc_string& NAME, int len)

{char stbuf[20];for (int i = 0; i< len; i++) {

sprintf(stbuf, “[%d]”, i);sc_trace(tf, v[i], NAME + stbuf);

}}

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Processes

Process causes other processes to excute by assigning new values to signals.

• Method: SC_METHOD(method_name)• Thread: SC_THREAD(thread_name)

can be suspended (wait()) until an event occurs.• Clocked Thread: SC_CTHREAD(thread_name)

are only triggered on one edge of one clock.

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Data structure

• bios = system bios data

• icache = initial instruction cache

• dcache = initial data cache

• register = initial register values

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Instruction set

• Arithmetic (x01~x08)

• Logical (x09~x0e)

• Transfer (x0f, x4d, x4e, x0f1)

• Branch (x10~x18)

• Floating point (x29~x2c)

• DSP (x31~x37)

• OS (x00, x0e0, x0f0, x0ff)

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Instruction format

048121620242831

OPcodedest

op1op2

immediate value

33

Partitioning

• Running the algorithm and measuring the cycles it takes.

• Determining the complexity (cost) of each part of the algorithm.

• Implementing some part of the algorithm (by modeling using SystemC).

34

Architecture

CPU

Instruction Cache

Data Cache

Memory

FPU

DSP

Fetch Decode

Execute

36

Classes

Instruction cache(Hex)

icache fetch decode

exec

FPU

Data cache(Hex)

dcache

DSP

CPU

37

Spiral-like model

• Design architecture

• Develop application

• Map application to architecture

• Analyze

Modify: mapping, architecture and application

• Continue refining to lower level unit

38

Design Methodology

SystemC Model

Simulation

Synthesis

Refinement

39

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• System spec.• Behavioral spec.

• Modeling• Validation

– Simulation– Verification

• Partition (Estimation)• Scheduling• Synthesis