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© Fraunhofer IIS/EAS

SYSTEMC AMS – ARCHITECTURE EXPLORATION FOR MIXED SIGNAL SYSTEMS

Stephan Schulz – Head of Heterogeneous System Specification

© Fraunhofer IIS/EAS | Stephan Schulz | 26. November 2015

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About FraunhoferFacts and figures

Founded 1992

Employees ~90

Budget ~$10.2M

Director Dr. Peter Schneider

Founded 1985

Employees ~880

Budget ~$144M

Director Dr. Albert Heuberger

Fraunhofer undertakes applied research of direct utility to private and public enterprise and of wide benefit to society.

Europe’s largest application-oriented research organization

Major innovations e.g. mp3 music format, white LEDs and a high-resolution thermal camera

Fraunhofer Association

Fraunhofer Institute for Integrated Circuits IIS Design Automation Division EAS


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Fraunhofer IIS, Design Automation DivisionOur business areas

System Level Design

Mixed-Signal IP and Design Services

Reliability and Lifetime Prediction

Condition Monitoring Systems

Wireless Automation

Energy Management

Design Application

Advanced System Integration

Optical Sensors

Integration

Requirements (technical, economical, legal)


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AGENDA

Motivation / Introduction of SystemC AMS

Architecture Exploration

Examples

Conclusion


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Sensors, actors, receiver, transmitter

Why consider analogue aspects?

Digital systems embedded in analogue components

System level design usually omits analogue effects

Re-designs and adaptations at later stages needed

Early analogue incorporation needed to avoid unnecessary iterations

Cost reduction

Shorter time to market

µC, ECU, DSP

Requirements

Concept

Detailed

Implementation

System-Test

Integration-Test

Unit-Test


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Why mixing analogue and digital?

Functionality moves from intelligent hardware design into software implementation

Easier bug-fixing

Cheaper hardware components

Re-use generic (verified!) digital components instead of custom solutions

Proven verification methods available such as UVM

Digital assisted analogue

Traditional architecture

DSP.

ADC

DAC

Receiver

Transmitter

Ant

enna

fron

t-en

d

Serial

InterfaceDSP

µCCalibration & Control

Receiver

ADC

DAC

Transmitter


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Modelling, Simulation, Verification: How?

Software is the key

ISS too slow in concept phase

Native compilation needed

SystemC & SystemC AMS provide key combination for integrating Software, Digital and Analogue Designs

Mixed-Signal Architecture Exploration

New: UVM-SystemC

SystemC modelling environment

UVM-SystemC -AMS

-AMS

C++

TLM SCVSystemC-AMS

SystemC


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SystemC AMS

Additional library to SystemC

Compatibility to vendor implementations

SystemC model

C++ compiler and linker

SystemC library

Executable code

(simulator)C++ debugger

Waveform viewer

SystemC AMSlibrary

-AMS

UVM-SystemClibrary


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SystemC AMS

Native integration in SystemC environments

Several modelling styles

Timed Data Flow (TDF)

Linear Signal Flow (LSF)

Electrical Linear Networks (ELN)

Several analysis types

Time domain

Frequency / Noise domain

SystemC Language Standard (IEEE Std 1666-2005)

Linear Signal Flow (LSF)

AMS methodology-specific elementselements for AMS design refinement, etc.

Synchronization layer

Scheduler

Timed Data Flow (TDF)

Electrical Linear Networks (ELN)

Linear DAE solver


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Model of Computations

Timed Data Flow

Discrete-time behaviour

Static scheduling

Support of static non-linear behaviour

Linear Signal Flow

Continuous-time behaviour

Differential and Algebraic Equations solved numerically at appropriate time steps

Electrical Linear Networks

Network primitives

Topology results in equation system which is solved numerically


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Analysis Types

Transient time domain driven by the SystemC kernel

AC-analysis

Calculates linear complex equation system stimulated by AC-sources

AC-noise-analysis

solves the linear complex equation system for each noise source contribution (other source contributions will be neglected)


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Use-Cases

functional

architecture

implementationSy

stem

C A

MS

data flow

signalflow

electricalnetworks

design abstraction

use cases

executablespecification

architectureexploration

integrationvalidation

modeling formalism

virtualprototyping

Syst

emC


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AGENDA



Examples

Conclusion


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Temp

Pressure

AD

ADµC

DA

DA

- +

DC

Firmware



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ELN

Temp

Pressure

AD

ADµC

DA

DA

- +

DC

Firmware

Domains

DIGITALLSF

SOFTWARE

TDF

TDF

TDF


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TIER2 TIER1 OEM

Re-usable reference models

Value/Supply Chain

Source: Wolfgang Scherr Infineon AIM


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Re-usable reference models

TIER2 TIER1 OEM

Value/Supply Chain

SystemC provides easy exchange of IP-protected models

Suppliers provide binary models

Easy provision of model libraries

Verification artefacts can be included to support verification during integration

SystemC model

C++ compiler and linker

SystemC library

Executable code

(simulator)C++ debugger

Waveform viewer

SystemC AMSlibrary

-AMS

UVM-SystemClibrary


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AGENDA



Examples

Conclusion


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SATA PHY including cable transmission

Serial ATA PHY chip set for 3 / 6 / 8 GBit serial data transmission

Concept engineering model of transceiver /receiver including phase locked loop (PLL)

Estimation of bit error rates, simulation of PLL locking behaviour


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Fiber optical Gyrosensor

This research project (Syena) is supported by the German Government, Federal Ministry of Education and Research under the grant number 01M3178


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Fiber optical Gyrosensor

Analogue ASIC (LiANA)

Digital ASIC (LiFOGA)Detector module

Sensor Electronic Module (SEM)

Digital MIOC (Multi Integrated Optic Chip)

Northrop Grumman LITEF GmbH


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ADSL / VDSL Systems

Transient settling behavior

Interaction Voice / Data transmission

Training algorithm

BER estimations

Numerous of use scenarios

Interaction of different lines

Multi level simulation environment essential

Hybrid

AGC Prefi ADC FilterDec. TDQ FFT FDQ

POFI DAC NSH FilterInt. IFFT

LECHybrid

AGCPrefiADCFilterDec.TDQFFTFDQ

POFIDACNSHFilterInt.IFFT

LEC

Linetwisted pair

Splitter Splitter SLIC Vinetic

Central OfficeCustomer Premises Equipement

CO0

CO1

CON

NEXT

FEXT

(Central Office) Cabinet

Cable Binder DropWire

NEXT

CPE N

CPE 1

CPE 0

Source: Gerhard Nössing, LANTIQ


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Motor speed and direction

Switches

Interrupt

OPAMP

Temperature

sensor

MON

inputs

LIN

transceiver

Power management unit

WDT

Measurement

interface

Microcontroller

subsystem/

ISS

Reset

Supply

Bias

Interrupt

Interrupt

Interrupts

Wake up

Wake up

Wake up

Mechanical subsystemAMS subsystem

to AMS parts

Motor speed and direction

Motor current

Window Lifter Model Overview

Source: Georg Pelz, Monica Rafaila, Infineon Technologies


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Window Lifter – Substantial Subset of Door ECU

SystemC(-AMS) simulations(functional and system MC) for substantial parts of ECU on

ECU architecture

Chip architecture in systemcontext

Chip design in system context

ECU design

Source: Georg Pelz, Infineon Technologies

This research project (AutoSUN) is supported by the German Government, Federal Ministry of Education and Research under the grant number 01M3178


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Simulation Performance – Window Lifter Model

Simulation time over simulated time

SystemC AMS Software on algorithm level 5 – 100

SystemC AMS Cycle-Accurate MCU model: 10³ – 5*10³

VHDL-AMS / VHDL: 105 – 106

FastMOS (Ultrasim): 109 – 1010 (start-up only)

Spice (Spectre): just no

Source: Monica Rafaila, Georg Pelz (Infineon Technologies)


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AGENDA

Motivation / Introduction


Examples

Conclusion


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Conclusion

SystemC in combination with SystemC AMS suitable for architecture exploration

Software, digital, analogue in one simulation

Verification method available covering all domains

License free simulation

Simulator available as PoC implementation

Tool integration available


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SystemC AMS – Architecture exploration for mixed signal systems

Questions


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THANK YOU FOR YOU ATTENTIONYOUR CONTACT

Stephan SchulzHead of Group

Heterogeneous System Specification

[email protected]

+49 351 4640-847

Fraunhofer Institute for Integrated Circuits IISDesign Automation Division EASZeunerstraße 3801069 Dresden, Germany

www.eas.iis.fraunhofer.de

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SystemC AMS – Architecture exploration for mixed signal ... · TIER2. TIER1. OEM. Value/Supply Chain SystemC provides easy exchange of IP -protected models Suppliers provide binary