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System Verilog Primer 1) Cover Properties - printf and property checking (ie, fifo full) 2) Queues 3) Assertions - Immediate and concurrent assertions - Sequence - Sequence match - Property 4) Dynamic array - Deletion of array 5) Clocking blocks - Multiple clocks 6) Interfaces 7) Program block - Sequence of events 8) Interposes sync and communication - Semaphores 9) Data types class Methodology a) Stimuli generation (Random generation) b) Checking (assertions, scoreboard) c) functional coverage (cover group, cover point)

System Verilog Primer

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Page 1: System Verilog Primer

System Verilog Primer

1) Cover Properties- printf and property checking (ie, fifo full)

2) Queues

3) Assertions- Immediate and concurrent assertions- Sequence - Sequence match- Property

4) Dynamic array - Deletion of array

5) Clocking blocks- Multiple clocks

6) Interfaces

7) Program block- Sequence of events

8) Interposes sync and communication- Semaphores

9) Data types class

Methodologya) Stimuli generation (Random generation)b) Checking (assertions, scoreboard)c) functional coverage (cover group, cover point)


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