System-level Exploration for Pareto- optimal Configurations in Parameterized Systems-on-a-chip Architectures Tony Givargis (Frank Vahid, Jörg Henkel) Center

System-level Exploration for Pareto-System-level Exploration for Pareto-optimal Configurations in Parameterized optimal Configurations in Parameterized

Systems-on-a-chip ArchitecturesSystems-on-a-chip Architectures

Tony Givargis (Frank Vahid, Jörg Henkel)Center for Embedded Computer Systems

University of California

Irvine, CA 92697

[email protected]

2

OverviewOverview

Given:– Parameterized SOC

architecture

Explore

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void main(){ while(1){ Receive(); Decode(); Display(); }} Application– Fixed application

Automatically explore the design space

Find optimal points w/respect to power and performance

SOCCPU Memory

JPEGCODEC

Math/FPU

UART

I$-D$BRIDGE

Size = {1K, 4K, 8K}Line = {4, 8, 16}Assoc = {1, 2, 4}

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MotivationMotivation

Design trends:– Growing demand for

portable devices– Growing demand for

low power design– Increased application

complexity– Shrinking time-to-

market windows

Technology trends:– Increased chip

capacity– Increased I/O pins– Improved on-chip

integration techniques (storage, digital, analog, digital, …)

– SOC era

Need for greater designer productivity!

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SOCCPU Memory

JPEGCODEC

Math/FPU

UART

MMXBRIDGE

?


One approach: reuse of existing IP

???

?

– IP selection ?

MIPS

RAM

JPEGCODEC1 Math/FPU

UART

ISABRIDGE

ARM

SRAM

DRAM

AMBABRIDGE

JPEGCODEC2

USB

– IP integration ?

– SOC verification ?– Multi-source IP

licensing– More…

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Alternate approach: reuse of SOC– Designed, integrated, tested– Domain specific– Parameterized

Designed by firms specializing in SOC

User: map application, then, “configure-and-execute”

(successors to microcontrollers!)

Parameterized SOC

CPU Memory

JPEGCODEC

Math/FPU

UART

MMXBRIDGE

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Composed of 100s of cores

Cores are “configurable”

Configurations impact power/performance

Large number of total configurations!

Architecture is otherwise fixed!

Parameterized SOC

CPU Memory

JPEGCODEC

Math/FPU

UART

MMXBRIDGE

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ATI Technologies – XILLEON™ 220 SOC for Digital Set-top Box Market

Tensilica – Xtensa™ 1040 configurable processor cores

Philips Semiconductors – Velocity RSP9™ SOC platforms

Adelante Technologies – offers complete SOC customizable platforms for DSP domains

More…

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OutlineOutline

Previous work Target architecture Power/performance estimation Parameter space exploration Experiments Conclusion

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OutlineOutline


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Previous WorkPrevious Work

Parameterized SOC design– [Malik00], [Veidenbaum99], [Vahid99], [Stan95]

Power/performance evaluation– [Barndolese00], [Simunic99], [Li98], [Tiwari94]

Design space exploration (manual)– [givargis99], [Lieverse99]

Design space exploration (automatic)– Focus of this work…

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Previous WorkPrevious Work

ArchitectureApplicationApplicationApplicationApplicationApplication

Mapping

Analysis

Numbers

Auto

Y-chart [Lieverse99]

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OutlineOutline


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Target ArchitectureTarget Architecture

UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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Voltage scale Size, line,

associativity Bus width,

encoding (gray, invert)

UART tx/rx buffer size

DCT resol. UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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DCT resol. UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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DCT resol. UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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DCT resol. UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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DCT resol. UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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26 parameters 1014

configurations What are the

optimal configuration (given a fixed application)?

UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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Problem SummaryProblem Summary

What are the possible power/performance tradeoffs? (100 trillion)

Need to efficiently evaluate power/performance (1/sec150,000 years)

Need to explore the configuration space

Parameterized SOC

CPU Memory

JPEGCODEC

Math/FPU

UART

MMXBRIDGE

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OutlineOutline


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Power EvaluationPower Evaluation

Exploration works with:– Chip instrumentation

(real-time)– System-level simulation– RTL simulation– Gate-level simulation– Circuit-level simulation

Relative accuracy required!

Digital camera application mapped on our SOC, capturing

1 image.

020000400006000080000

100000120000140000160000180000

1st Qtr

ChipSystemRTLGateCircuit

1 440

5400 28

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1800

00

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Power EvaluationPower Evaluation

Exploration works with:– Chip instrumentation

(real-time)– System-level simulation– RTL simulation– Gate-level simulation– Circuit-level simulation

Relative accuracy required!

Digital camera application mapped on our SOC, capturing

1 image.

020000400006000080000

100000120000140000160000180000

1st Qtr

ChipSystemRTLGateCircuit

1 440

5400 28

800

1800

00

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Power Evaluation - ProcessorPower Evaluation - Processor

[Tiwari94/00]’s instruction-level

Measure watt/inst

Account for stalls + dependency

Apply traces UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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Power Evaluation – Cache/Mem.Power Evaluation – Cache/Mem.

[Evans95] Capacitance

model of sub- components

Switching obtained via simulation (parameter dependent)

UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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Power Evaluation – BusesPower Evaluation – Buses

[Chern92] Model bus

capacitance Switching

derived from I/O traffic (parameter dependent)

UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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Power Evaluation – PeripheralsPower Evaluation – Peripherals

Observation: cores execute instructions!

Apply a technique similar to that used for processors! UART

MIPSI-Cache

D-Cache

Bridge

Peripheral Bus

DCT CODEC

Memory

DMA

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Power Evaluation – SummaryPower Evaluation – Summary

UART (5%)

MIPS (10%)I-Cache (8%)

D-Cache (8%)

Bridge (5%)

Peripheral Bus

DCT CODEC (5%)

Memory (8%)

DMA (5%)

~50-100K instruction/second! (Platune)

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OutlineOutline


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ExplorationExploration

Problem formulation P1, P2, … , Pn

A configuration (point) is an assignment of values to all parameters

How to efficiently generate all Pareto-optimal configurations?

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Exploration Exploration

* = 320 pointsAlgorithm Idea A (10)

B (32)

A and B interdependent+ = 42 points A and C are independent

A (10)

C (32)

C and B are independentC

(32)B

(32)+ = 64 points

138 points

With knowledge about dependency we prune 98.6%

* * = 10240 pointsB (32)

C (32)

A (10)

Directed graph

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A B : Pareto-optimal configurations of B calculated after Pareto-optimal configurations of nodes along the path A B

A B A, (cycle) : Pareto-optimal configurations of all the parameters on the cycle calculated simultaneously

A : Pareto-optimal configurations calculated in isolation

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Exploration Exploration

AB

C

D

J KE

F

G

H I

N O

L M

R S

P Q

V W

T U

X

YZ

Node Core Parameter

A MIPS

Voltage scale

B I$ Total size

C Line size

D Associativity

E D$ Total size

F Line size

G Associativity

H CPU I$

bus

Data bus width

I Data bus code

J Addr bus width

K Addr bus code

X UART

Tx buffer size

Y Rx buffer size

Node Core Parameter

L CPU D$ bus

Data bus width

M Data bus code

N Addr bus width

O Addr bus code

P I/D$ Mem bus

Data bus width

Q Data bus code

R Addr bus width

S Addr bus code

T Peripheral bus

Data bus width

U Data bus code

V Addr bus width

W Addr bus code

Z DCT CODE

C

Pixel resolution

Dependency Graph

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AB

C

D

J KE

F

G

H I

N O

L M

R S

P Q

V W

T U

X

YZ

Dependency graph Based on designer

knowledge Computed by

simulating all pairs of nodes (quadratic time complexity, approx.)

One time effort


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Exploration – Algorithm Exploration – Algorithm

Step 1: Clustering followed by simulation

A

B

C

D

J K

E

F

GH I

N O

L M

R S

P Q

V W

T UX

Y Z

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Exploration – Algorithm Exploration – Algorithm

A,H,I B,C,D,E,F,G

J,K,T,U

L,M,P,Q

N,O,V,W X,Y,R,S

Z

A,H,I,B,C,D,E,F,

G

J,K,T,U,Z

L,M,P,Q,N,O,V,W

X,Y,R,S

A,H,I,B,C,D,E,F,G,J,K,T,U,Z

L,M,P,Q,N,O,V,W,X,Y,R,S

A,H,I,B,C,D,E,F,G,J,K,T,U,Z,L,M,P,Q,N,O,V,W,X,Y,R,S

Step 2: Pair-wise merge followed by simulation

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Exhaustive solution Evaluate all points Sort by decreasing

execution time Walk through the

space, eliminate points with power > minimum seen so far!

Substitute heuristics 0

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(only works for 1-4 parameters!)

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Complexity: O((K + log(K)) * 2N/K) K is the number of clusters N is the number of parameters 2N/K bounds the exhaustive comp. (K + log(k)) bounds the number of iterations Worse case K=1, best case K=N 2N/K decrease rapidly as K increases (e.g.,

226/2+226/2 is much smaller than 226!)

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OutlineOutline


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Exploration – Results Exploration – Results

JPEG

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JPEG Exploration

time: 29.1 min Config. visited:

12352 (141) 5.10x exe. time 7.51x power 2.73x energy Pruning ratio >

0.99997

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Exploration – Results Exploration – Results

CKEY

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CKEY Exploration

time: 108 min Config. visited:


0.99993

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Exploration – ResultsExploration – Results

IMAGE

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IMAGE Exploration



0.99998

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MATRIX Exploration



0.99997

MATRIX

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JPEGJPEG

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JPEG JPEG

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ConclusionConclusion

Gave a system-level algorithm for exploring the solution space of an application mapped to a parameterized SOC architectures– Given a dependency graph we extensively prune the

solution space– Pruning ratio > 0.99997 in experiments

Future work:– Automatically compute the dependency model– Replace the exhaustive sub-algorithm with a heuristic

(e.g., gradient search, GA)

Documents

System-level Exploration for Pareto- optimal Configurations in Parameterized Systems-on-a-chip Architectures Tony Givargis (Frank Vahid, Jörg Henkel) Center