System Architecture of Detector Control and Safety for the ATLAS Inner Detector Upgrade Didier Ferrère, DPNC Université de Genève Susanne Kersten, Wuppertal

System Architecture of Detector Control and Safety for System Architecture of Detector Control and Safety for the ATLAS Inner Detector Upgradethe ATLAS Inner Detector Upgrade

Didier Ferrère, DPNC Université de Genève

Susanne Kersten, Wuppertal University

2D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima

New Inner Detector for ATLAS UpgradeNew Inner Detector for ATLAS Upgrade

Under consideration: • Current silicon tracker is expected to smoothly die with an integrated luminosity (< 600 fb-1) : Radiation damages and Inefficiencies at high rate. • A new ID is foreseen at phase 2 Upgrade of the machine and for data taking in ~2020• The electrical services between the counting rooms and the cavern remain a constraint for the new detector• All the hardware for the FE electronics, the DAQ, the power supply and the DCS will have to be renewed• The cooling is one of the critical challenges for the future silicon tracker with requested operational temperature down to -40°C• All the development has to fit in the framework of the existing ATLAS DAQ, DCS, Trigger with some restrictions under study

One ID layout under consideration

4 pixel layers3 Short-strip layers2 Long-strip layers


ATLAS Detector Control System to be UpdatedATLAS Detector Control System to be Updated

Pixel & Strip to be renewed

Cooling and ID environment to

be renewed

The new DCS structure has to fit in the ATLAS GCS


DCS MotivationsDCS Motivations

The DCS has to be defined as early as possible such it is integrated into the readout architecture together with the powering and the services.

Towards the specifications:• Define the needs Use cases (close to current tracker)• The detector safety and the interlock to be considered as the 1st requirement • Monitoring sources to be well evaluated• Minimize as much as possible the material and the services • Optimize the development effort • Limit access installation in the cavern DCS hardware in the counting room• Try to define a common Pixel and Strip DCS architecture if possible • Search for adequate sensors: Humidity, others?• Identify all the topics where early resources may be necessary• Define the prototypes for DCS investigations like power monitoring and control

Up to 180 kW to control and monitor during the operation in term of power, cooling, and environment across the all ID.


Comments:• SMC is located at the stave end and steer 24 hybrids. In total and per stave there are 2 SMCs: one per side. • SMC (Super Module Controller) is a hybrid board which integrates the opto, the GBT, the DCS and some power regulations • 1 or 2 MCC (Module Controller Chip) steer the data of the 20 chips on a hybrid• The service bus is running below the Si-wafers and the front and back detector bias are separated.•There are 2 SMCs par Stave/SM electrically separated from the top and bottom side

Short Strip Barrel Stave LayoutShort Strip Barrel Stave Layout

Service bus

TTC, Data & DCS fibers

PS cable

DCS env. IN

Cooling In

Opto

GBT

DCSinterlock

SMC Hybrid

Module #1 Module #2 Module #12

Cooling Out

IPBeam Axis* the GBT (Giga Bit Transmission) is a chip for data transmission developed by the CERN PH-ESE group

MCC MCC MCC MCC MCC MCC


Pixel Barrel Stave LayoutPixel Barrel Stave Layout

FE FEFE FE

GBT*DCS

FE FEFE FE

FE FEFE FE

FE FEFE FE

FE FEFE FE

FE FEFE FE

FE FEFE FE

FE FEFE FE

Module 0Module 7

End of Stave Card

half stave

Beam Axis

2 single sided staves sandwiched together back to back

GBT* DCS

Comments:• The construction of the staves varies between the different layers 24 - 32 modules/stave

There are 4 Front End chips/detector module• The DCS relevant building blocks are half stave/disk sector: up to 16 modules + 1 EoS card • For both Pixel and strip two options are considered for the powering:

- Serial powering- Parallel powering with 2 DC-DC stages

IP* the GBT (Giga Bit Transmission) is a chip for data transmission developed by the CERN PH-ESE group


ID Upgrade DCS ArchitectureID Upgrade DCS Architecture

ID DCS

Strip DCS Pixel DCS ID DCS Gen? Cool DCS

FE DCS DCS Chip

Elect. Opto at PS

Lines from staves to

counting room

DCS split at BOC/ROD

DCS Data with RO Data

DCS at PS

Not defined yet!Not defined yet!

‘Cooling Interlock’ ‘Strip Module Interlock’

‘SMC Interlock’@ « BBIM » @ « SMC »

@ PS card

@ « BBIM »

or

Pixel Stave

Elect.

‘Pixel Module Interlock’

@ « BBIM »

DCS Chip

Strip Stave Power SupplyEnv DCS

Elect.

Env DCS

SPI or I2C

FE DCS

DCS Data with RO Data

Opto

Lines from staves to

counting room


Strip Architecture OverviewStrip Architecture Overview

Stave

RH

SCTDAQ

PS Crate

Cooling Temp

FE DCS

Hybrid Temp

Hybrid Power

EoS Card

Ibox Elmb

CAN Bus

CAN BusGlobal Interlock

ROD

BOC

5 GB/s optical linkTTC - DCS

Channel Interlock

LAN

Type 2 Type4 cables

Env. Structure

DetectorPS Type 2 Type 4 cables

SCTDCS

Elmb

CAN Bus

SPI bus or LVDS lines daisy chain

Option 2 Option 1/3

BBIM

RH

NTC

Matrix


Pixel Architecture OverviewPixel Architecture Overview

Distance frominteraction point [m]

Control room

~100

DCS Master

Power SuppliesPixel DCSPixel DAQ

Readout Crate

diagnostics

InterlockCircuit

EoSController

Opto Board

symmetric to both sides

cable bundle from half stave

DCSDCS Environment

safetyControl –feedback

DCS

End of Stave Card

half staveshalf staves half staveshalf staves

~50

Detector volume


Safety Interlock and Monitoring Sources Safety Interlock and Monitoring Sources

Strip Pixel

Cooling Interlock

NTCs / Stave 2 -

JustificationProtection against cooling

failure-

ActionPower cut of the

corresponding LV & HV stave-

Module Interlock

NTCs / Stave 48 16 4 lines

JustificationProtection against any heat excess. Reasons: Runaway,

Cooling failure, contact problem

Protection against any heat excess. Reasons: Cooling failure, runaway, contact

problem

ActionEither Disable LV locally or at

power supply

Power cut of the corresponding LV & HV

stave

Stave Card Interlock

NTCs / Stave 2 1

JustificationProtection against excess

heating of EoS CardProtection against excess

heating of EoS Card

ActionDisable the LV power on all

the staveDisable the LV power on all

the stave

Monitoring sources: NTCs, RH sensors, power supplies, FE temp & power.


Interlock and Monitoring of Module NTCs forInterlock and Monitoring of Module NTCs forStripStrip

NTC NTC NTC

RESISTORS

ADC

REF

+V

+V

GND

GND

GND

NTC

REGISTERTRIPLE VOTE LOGIC

THRESHOLD from DAC with Triple vote logic

GND GND

Stave side – 24 hybrids

IC on SMC HYBRID

CLEAR

D F/F

+

-

OVER HEAT

OR

INTERLOCK

1 ADC 12bitsmultiplexed

1 interlock signal/ half stave

REF

Enable DAC with Triple vote logic

Asic either with GBT SCA or separated

GBTE-port?

1 2 3 23 or 24

Op

tion

3

Interlock steered on the stave card


LV Mod PS BotLV Mod PS Bot

HV PS Bot X 9-12HV PS Bot X 9-12

HV PS Top X 9-12HV PS Top X 9-12

LV Mod PS TopLV Mod PS Top

PS Crate

DCSDCSI-box

NTC-Cooling

NTC-SMC

I-Cooling/Mod

I-SMC-Top

I-SMC-Bot

I-Modue Top

I-Modue Bot

Top-side Stave Power-DCS cable

Bottom-side Stave Power-DCS cable

NTC-Mod (option3)

LV SMC PS BotLV SMC PS Bot

LV SMC PS TopLV SMC PS Top

Combining Interlocks at PS crate – Strip Serial PoweringCombining Interlocks at PS crate – Strip Serial Powering


Interlock and Monitoring of Module NTCs forInterlock and Monitoring of Module NTCs forPixelPixel

On detectorOff detector

DCS chip

NTC

A

Interlock

• Temp. measurement of detector modules: NTCs are supplied from outside

• In case of environmental temp. measurement, the NTCs will be supplied by the DCS chip

Interlock steered in the counting room


Towards a Common Radiation Hard DCS ChipTowards a Common Radiation Hard DCS Chip

Motivations:- Unification of some DCS hardware across the ATLAS ID- Optimize development effort and cost - Chip should be as flexible as possible in term of use in the all ID volume

Main features:

• Radiation hardness up to 1.3x1016 1 MeV neq/cm2 • Have to work with two protocols: I2C/SPI (low frequency), and GBT e-port (40 MHz)• Low power when running at low frequency with I2C or SPI: < 0.1W• About 32 analog input needed• Some DAC for power control and up 17 dig. Out (Bypass for pixel SP + reset)• Interlock function based on FSM with programmable temp limits (Strip)• SEU protection for all the relevant parts• Interlock decision need to be sure • Power supply reference for NTCs

AnalogMux32

I2C SPI GBT

a1

a32

Vref

SCK Din Dout

CE SDA SCL

FSM

VSupply VRef

Alarm flagDAC1 bit

dout

ADC10bit

E-link for Slow Control

NB: A DCS IC submitted by Wuppertal to study I2C and SPI


GBT-SCA – Slow Control in a Radiation Hard DCS ICGBT-SCA – Slow Control in a Radiation Hard DCS IC From A. Marchioro

On-DetectorCustom Electronics & Packaging

Radiation Hard Off-DetectorCommercial Off-The-Shelf (COTS)

Custom Protocol

I2C Master SCAController

SCLSDATA

D[0:7] A[0:15]

JTAGMaster

Clock Generation

E-Link

Monitoring ADC

Ch1Ch2

…Ch16

Monitoring ADC

16 x

I2C

Bus

es

MemoryInterface

PIA4 x PP[0:7]

Ext Reset*

I2C Master

e-LinkController

The “GBT Project” is part of the “Radiation Hard Optical Link Project” which aims at developing a radiation

hard bi-directional optical link for use in the LHC upgrade programs


ConclusionsConclusions

• The Inner Tracker Upgrade has to be renewed and is under development & prototyping construction based on silicon pixel and strip• The DCS has to be designed as a new system to fit with the detector requirements in term of safety and operation as well as with the ATLAS Global Control System• The key parameters of such a system are the control of the power and of the temperature of the complete tracker• Controllable power is needed at the detector parts using either serial powering or DC-DC conversion• New features are proposed for detector diagnostics like including DCS into FE chips• Strip and Pixel detectors have different requirements but need to unify system, effort and some hardware parts• A single radiation hard DCS IC is one of the illustration of it with some common specifications that are under investigation. GBT-SCA is a possible option now considered• Still a lot to investigate in term of steering DCS interlock and information at the counting room and linked to the Power Supply units


Back-up slidesBack-up slides


Back-up slidesBack-up slides Pixel - Disabling of serial powered modules Pixel - Disabling of serial powered modules

charge pump:

DCS chip produces pulses (between 0 and 3.3 V)

C1 is charged to U_GS (2.5 V due to inefficiency)

Bonn-Wuppertal Stave emulator system

DCS chip is simulated by COBOLT (DCS board with microprocessor)


DCS chips are running permanentlycheck that there is no temp. interlock check temp of opto board turn on cooling of opto boardsturn on power of opto board + monitor its power

check temp of modules and EOS turn on cooling of modulesturn on power of EOS controller and modules + monitor their power consumption

initialize opto board configure modulespower consumption → successful configurationstart tuning, calibration, etc … of data taking chain

Back-up slidesBack-up slides Pixel - Power Up SequencePixel - Power Up Sequence


Back-up slidesBack-up slides Strip – DCS Operational SequencesStrip – DCS Operational Sequences

Pre-operation SMC ramp & Opto com Module ramp Operation

Cooling Interlock Active, Env. data accessible, PS

Module Interlock Active, Module temp, local PS accessible

DCS Cooling Survey

FE DCS, Hybrid power accessible

High data volumePossible but not desired

Medium data volume> 4.3x105 data/day/stave

Low data volume> 5x104 data/day/stave @ 0.1-1Hz

@ 0.1-1Hz

On request

Detector ColdDetector Cold

From

DCS syste

m w

ith optio

n 2

From D

AQ with

optio

n 1&3

A) B) C) D)


Back-up slidesBack-up slides Strip – DCS Operational SequencesStrip – DCS Operational SequencesOperational phase Option 1 & 3 Option 2

Pre-operation

Cooling OFF

Access to Env DCS and monitor cooling Interlock NTCs (+ 1 Module side for option 3)

Access to Env DCS and monitor cooling interlock NTCs & module temps Module Interlock active

SMC ramp & Opto com

Cooling ONPower ramp-up on SMC for Opto settings and com. DCS ON – Monitor module temp + Env Module Interlock active

Power ramp-up on SMC for Opto settings and com. DCS ON – Monitor module temp + Env Module interlock still active

Module ramp

Cooling ON

Power ramp-up on FE hybrids.

Active protection + Bypass (SP) or Power En/Dis (DC-DC)

DCS diagnostics accessible

Power ramp-up on FE hybrids.



Operation

Cooling ONActive protection + Bypass (SP) or Power En/Dis (DC-DC)




E) Module temp failure

Cooling ON

SP: FE LV + HV inhibit (Case B)

DC-DC: Module power disable (Case C-D)

SP: FE LV + HV inhibit (Case B)

DC-DC: Module power dsiable (Case C-D)

F) Cooling failure

Cooling OFF

All power interlocked! (Case A) All power interlocked! (Case A)


Back-up slidesBack-up slides DCS Data & Interlock versus the Construction Phase & TestDCS Data & Interlock versus the Construction Phase & Test

Hybrid & Module QA

Stave QA Integration & Tests

Barrel commissioning

ID commissioning

Cooling type Water Water or evaporative

No cooling Evaporative Evaporative

Power type Local power SMC power

Module power

SMC power (quick tests)

Final PS crate SMC and Module power

Final PS crate SMC and Module power

Type of test FE Readout FE readout chain

GBT-Opt com

Conn. tests

Full readout Full readout

PS DCS Custom survey Custom survey NO Final system – PS Mon

Final system - PS Mon

Environmental survey

No No Connectivity test

Yes Yes

SMC DCS No Yes Yes for com test Yes Yes

Cooling interlock

No No No Yes (Warm cool) Yes (Possibly warm cool)

Module interlock

Home made Home made No Yes Yes

SMC interlock No Home made No Yes Yes

NB: Modules are never tested un-cooled either individually or on the stave

Documents

System Architecture of Detector Control and Safety for the ATLAS Inner Detector Upgrade Didier Ferrère, DPNC Université de Genève Susanne Kersten, Wuppertal