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Synthesizing and Simulating Verilog code Using Xilinx Software Neeraj Kulkarni

Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

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Page 1: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Synthesizing and Simulating Verilog code

Using Xilinx Software Neeraj Kulkarni

[email protected]

Page 2: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Xilinx ISE 14.6 • Download link- http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html • Choose the Full Installer for Windows • You need to register on their website.

• Install the software. When it prompts for licence choose

WebPack Licence which is available for free.

• Note: Preferable install it in Windows 7 environment. Xilinx 14.4 has some annoying bugs when run with Windows 8. I think they still do not support windows 8.

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html

Page 3: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Open the Xilinx ISE Software

Open New Project

Page 4: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Choose the location to create New Project

Page 5: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Choose settings as shown as FPGA chosen is available .

Click Next and then click Finish.

Page 6: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Create New Source as shown

Page 7: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Select Verilog module.

Click Next twice and then Finish.

Page 8: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

You can now write your module.

Page 9: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Code for mux written.

Double click on synthesize, on the left hand side.

Page 10: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

To see the circuit click on view RTL schematic option and then press ok.

Page 11: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Go on clicking in the black area to zoom in the circuit elements.

Page 12: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

To run simulation click on Simulation option at the top of left column

Page 13: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

To create a Test bench, create New Source.

Select Verilog Test Fixture

Page 14: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Template of Test bench will be created instantiating the mux module.

Page 15: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Add the testing code in the initial block below Add Stimulus here comment.

Page 16: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

Double click on Simulate Behavioral Model option.

Page 17: Synthesizing and Simulating Verilog code · Select Verilog Test Fixture . Template of Test bench will be created instantiating the mux module. Add the testing code in the initial

This is the simulation window. You can verify the working using waveforms or using printed statements at the bottom.

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