Synthesizable “Power” · DCR AHB Ar b i t e r AHB (32/64 /128 -bits) PLB Monitor AHB Master1 AHB Master3 AHB Slave1 AHB Slave2 AHB Slave3 DCR AHB Monitor DCR DCR Monitor These

Synthesizable “Power” –Using Process Portability to Embed PowerPC Cores in Your Chip

Lonn FianceDirector, Strategic AlliancesSynopsys

© 2005 Synopsys, Inc. Pg. 2;

Agenda

• Synopsys overview• PowerPC embedded core overview• Synopsys’ Synthesizable PowerPC

405/440 offering• Questions and answers


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FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04

Global leader in EDA and IP

• Strong global presence:~ 4,400 employees, 60+ offices

• Strong technical innovation: 1600+ R&D eng. (~26% of rev.)

• Strong customer support:1450+ applications engineers

• Strong global presence:~ 4,400 employees, 60+ offices

• Strong technical innovation: 1600+ R&D eng. (~26% of rev.)

• Strong customer support:1450+ applications engineers

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FY96 FY97 FY98 FY99 FY00 FY01 FY02 FY03 FY04

$1.1B revenue in FY04$1.1B revenue in FY04

$285M on R&D in FY04$285M on R&D in FY04


ShanghaiShanghai

BeijingBeijing

ShenzhenShenzhen

Hong KongHong Kong

Synopsys OfficesSynopsys Offices

XiXi’’anan

ChengduChengdu HangzhouHangzhou

WuxiWuxi

Synopsys in China Since 1995

National IC Design National IC Design Incubation CentersIncubation Centers

200+ R&D Engineers200+ R&D Engineers

University ProgramsUniversity Programs35 locations35 locations

Tsinghua UniversityTsinghua UniversityBeijing Beijing PolytechnicalPolytechnical UniversityUniversityNorthern Northern JiaoTongJiaoTong UniversityUniversityPeking UniversityPeking UniversityBeijing College of AeronauticsBeijing College of Aeronautics

HarrbinHarrbin UniversityUniversity

Shanghai Jiao Tong UniversityShanghai Jiao Tong UniversityTongjiTongji UniversityUniversityFudan UniversityFudan University

University of Electronics Science University of Electronics Science and Technology of Chinaand Technology of China

Xian Jiaotong Xian Jiaotong UniversityUniversity

Zhejiang UniversityZhejiang University

HKUST, HKUC, SCUSTHKUST, HKUC, SCUST

Chinese Chinese Academy Academy of Sciencesof Sciences

Datang Datang TelecomTelecom

SMICSMICPPP

PPP

PartnershipsPartnerships

PPP

PPP


Most Trusted in EDA Industry

61%59%

39%37%

36%

24%

Best afterBest after--sales support sales support

Technology leader todayTechnology leader todayTechnology leader in 3 yearsTechnology leader in 3 years

Clear vision of futureClear vision of futureMost ethical companyMost ethical company

Knowledgeable sales repsKnowledgeable sales reps

Best training servicesBest training servicesBest beforeBest before--sales system supportsales system support

Offers consulting design servicesOffers consulting design services

Best documentationBest documentation

WellWell--managed companymanaged company

Best Web siteBest Web site

28%

12%

Offers competitive pricesOffers competitive prices

7%

Best integration w/other toolsBest integration w/other tools

46%

33%35%Best integration with foundries & IP suppliersBest integration with foundries & IP suppliers

Best support of open standardsBest support of open standards

331111222211111111111111221122

11

32%

23%23%

7%

Attribute in selecting vendorAttribute in selecting vendor SNPS RankSNPS Rank ImportanceImportance

Source: 2004 EE Times Reader EDA Survey


Need Convergent Optimization Solution

Yiel

dYi

eld

Sign

al In

tegr

itySi

gnal

Inte

grity

Pow

erPo

wer

Test

Test

Are

aA

rea

TTRTTRQORQORQORQOR

COR

COR

TTRTTR


Complete, Correlated And Concurrent

& Services& ServicesFlows Flows

VerificationVerificationDesignDesign

IP ReuseIP Reuse

DFMDFM


Industry Leading AlliancesASIC VendorsFoundries PLD Vendors

IP Vendors Library VendorsSynopsys strategic Synopsys strategic partnerships assure our partnerships assure our customers meet their customers meet their performance, cost, and performance, cost, and schedule goals. schedule goals.

http://www.lsilogic.com/index.html


Power Architecture Application Areas

Digital Imaging

Games

Set-Top Box

GPS, In-cabin, & Telematics

Personal Communicator

PDA

In Auto In Hand In Home

Pervasive ComputingPervasive Computing

750

970

750Server

Networked Storage

IT/StorageIT/Storage

Workstations

970

750

970

NetworkingNetworking

3G Access / IP Gateway

Wireless LAN

WAN Switch/Router

405 405 405405

440 440440

440

440

750

970


IBM PowerPC® Licensable Cores

PowerPC 440

32K/32K0.18um

15.5mm2

32K/32K130nm9.8mm2

440 440 440-S32K/32K

FullySynthesizable

2.5mW/MHz 1.5mW/MHzKey Features•32-bit PowerPC Book E•Superscalar, 2 inst/cycle•MMU, 1KB-256MB pages•128-bit PLB, 64GB addr

Key Features•32-bit PowerPC Embedded•Scalar, 1 inst/cycle•MMU, 1KB-16MB pages•64-bit PLB, 4GB addr

16K/16K0.18um8.0mm2

16K/16K130nm3.8mm2

405 405 405-S16K/16K

FullySynthesizable

1.9mW/MHz 0.9mW/MHz

PowerPC 405


PowerPC 405 FeaturesArchitecture 32-bit PowerPC Embedded

Application code compatible with all PowerPC microprocessors

Special Features

Hardware multiply / divide24 DSP instructions (16x16+32)32-bit x 32 general purpose registers

MMU 64 entry UTLB – full associativity4 entry ITLB, 8 entry DTLB5 cycle miss penaltyVariable pages – 1KB to 16MB

Branch Pred.

Static

Physical Address

32-bit (4GB physical address)64- or 128-bit interface to Processor Local Bus (PLB)On-chip memory supported via PLB

Debug JTAG and Trace FIFO portsReal-time, non-invasive trace supported

CPU Pipeline

5 Stage PipelineSingle instruction per cycle

Caches 16KB, 2-way set associative, 32-byte line, no locking, parity

Instruction Unit

Instruction Unit Branch

Unit

Branch Unit

Execution Unit

MAC

Execution Unit

MAC

GPRsGPRs

I-cache control

I-cache control MMUMMU

TimersTimers

Debug / TraceDebug / TracePower ManagementPower Management

InterruptsInterrupts

16K I-cache

16K I-cache

64b Processor Local Bus64b Processor Local Bus

D-cache control

D-cache control

16KD-cache

16KD-cache


PowerPC 440 FeaturesArchitecture 32-bit PowerPC Book E

Application code compatible with all PowerPC microprocessors

CPU Pipeline Two-way superscalar7 Stages, out of order issue, execution and completion

L1 Caches 32KB, 64-way set associative, transient and locked cache region mechanism, software managed coherency, parity

MMU 64 entry UTLB – full associativity4 entry ITLB, 8 entry DTLB3 cycle ITLB/DTLB miss penalty

Branch Pred. Dynamic16-entry BTAC, 4K-entry BHT

Physical Addr 36-bit (64GB physical address)

Core Interfaces Three independent 128-bit PLB4 master ports (instruction read, data read, data write), each with separate address bus

Debug JTAG and Trace FIFO portsReal-time, non-invasive trace supported

Instruction UnitInstruction Unit Branch Unit

Branch Unit

D-cache control

D-cache controlI-cache

control

I-cache control MMUMMU

TimersTimers

Debug / TraceDebug / TracePower ManagementPower Management

InterruptsInterrupts

32KD-cache

32KD-cache32K

I-cache

32K I-cache

128b Processor Local Bus128b Processor Local Bus

Complex Integer

Pipe

MAC

Complex Integer

Pipe

MAC

Simple Integer

Pipe

Simple Integer

Pipe

Load / Store Pipe

Load / Store Pipe


The Power of Flexibility

• Each application has unique requirementsBusiness: cost, delivery time, existing supplier relationships, design services, etc.Technical: process technology, integration, packaging, performance, other IP, etc.Life cycle: process migration, multi-sourcing, cost reductions, strategic options

• Process portability provides flexibility to address these requirements

• Flexibility is key to proliferation


Flexibility Creates Value

• Design Value is a complicated function

Value = f(Area, Performance, Power, Yield, IP, Packaging, Process, Delivery Time, Reliability, Risk, Location)

• Complex interaction between the parameters

• Intelligent tradeoffs increase value

Design specific

Example Trade-Offs

Perf

orm

ance

Area orPower


PowerPC 405-S & 440-S Overview • Macro Objective:

Technology independent, reusable and fully synthesizable PowerPC cores

• Design ObjectivesStandard SRAM’s and Register Filesfor Caches and UTLB’sMaintain cycle compatibility with the existing PowerPC 4xxTarget performance of 300 MHz (440-S) and 250 MHz (405-S) for Artisan TSMC 13 LVFSGFault coverage goal of >98%Use a complete Synopsys tool flow

• Verification ObjectivesCreate a portable verification environmentCreate tests to verify the major architectural capabilities

• Easy delivery and use via Synopsys DesignWare®

440 440 440-S

405 405 405-S

32K/32K180nm

15.5mm2

32K/32K130nm9.8mm2

16K/16K180nm8.0mm2

16K/16K130nm3.8mm2

2.5mW/MHz 1.5mW/MHz

1.9mW/MHz 0.9mW/MHz

32K/32KFully

Synthesizable

16K/16KFully

Synthesizable


Synopsys Power Solution -Design Flexibility and Portability

• System C modelsSystem-level SystemC modelsInstrumented for System Studio

• SoC DesignDesign ViewImplementation ViewCPU, SoC testbenches with test suites

• DocumentationImplementation scripts with README’sUser Guide, Data Book, App Notes, etc.

• SupportAward-winning customer supportQualified design services and complimentary IP


SystemC Models

• C++ class library to model SoC hardware and processes

• Used for system-level designArchitectural analysis of processors, buses, custom logic, and IP

• Explore hardware/software tradeoffs• SystemC is an open industry standard

Tool and IP support from multiple companies• C++ basis allows concurrent development

of hardware and software


Synopsys SystemC Deliverables

• Original models, testing and validation from IBM

• Synopsys distributes and supports

• Instrumented for System Studio

SystemC Model List• PowerPC 405 Processor Core• PowerPC 440 Processor Core• PLB4 (Processor Local Bus v4.x)• DMA Controller (PLB4)• DCR (Device Control Register)• UIC (Universal Interrupt Controller)• UART (Universal Asynchronous

Receiver Transmitter)• MCMAL PLB4 (Multi-channel

Memory Access Layer)• Memory (DDR) Controller (PLB4)• EBC (External Bus Controller)• OPB (On Chip Peripheral Bus)• PLB4 to OPB Bridge• OPB to PLB4 Bridge• PCI-X to PLB4• PCI-Express


Design View coreKit Overview• “Black Box” Verilog Models for the

PowerPC 4xx-SFixed configuration to determine feasibilityCycle compatible VMC model of the 4xx-SVERA based CPU testbench Timing model for WC operating conditions for Artisan TSMC 13 LVFSGAll appropriate documentation (databook, datasheet, etc.)

• PLB-to-AHB Bridge Verilog ModelCycle compatible VMC model of the PLB2AHB Bridge VERA based SOC testbench for the PLB2AHB BridgeApplication note

• Available to DesignWare licensees at no additional charge

4 4 0 C o r e

C l o c k a n dR e s e t L o g i c

V e r i l o g T o p l e v e lT e s t b e n c h

D C RM o n it o r

In t e r r u p tC t r l M o d e l I n te r r u p t p in s

D C RM o d e l D C R B u s

J T A GM o d e l

J T A G I n t e r f a c e

P L BM o n i t o r

IC U R d D C U R d D C U W r

B a c k e n d In te r f a c e

V E R A M o d e ls

P L B S l a v e /B a c k e n dC o n t r o l

I B M P L BS l a v e M o d e l

( m e m o r y )

P r o c e s s o r L o c a l B u s ( P L B )P r o c e s s o r L o c a l B u s ( P L B )I B M

P L BA r b i t e r

D W A M B A V I P

D W A M B A V I P

I B M P L B M o d e l T o o l k i t

PLB

Arb

iter

P L B ( 1 2 8 - b i t s )

P L BM a s t e r

P L BS l a v e 1

P L BS l a v e 2

P L B M a s t e r( P P C 4 4 0 )

P L B 2 A H B B r i d g e( P L B S l a v e 3 )( A H B M a s t e r 2 )

D C R

AH

B

Arb

iter

A H B ( 3 2 / 6 4 / 1 2 8 - b i t s )

P L BM o n i t o r

A H BM a s t e r 1

A H BM a s t e r 3

A H BS l a v e 1

A H BS l a v e 2

A H BS l a v e 3

D C R

A H BM o n i t o r

D C R

D C RM o n i t o r

T h e s e I P 's a r e n o t d e l iv e r e d a s a p a r t o f t h e c o r e k i t , b u t h a s t o b e i n s t a l le ds e p a r a t e ly . H o w e v e r t h e t e s t b e n c h w i l l b e i n s t a n t i a t i n g t h e s e c o m p o n e n t s .

h c l kS Y S _ p l b C l k

d c r _ c l k D C RS l a v e

D C RS l a v e


Testbench - 440-S CPU

4 4 0 C o r e

C lo c k a n dR e s e t L o g ic

V e r i lo g T o p le v e lT e s t b e n c h

D C RM o n i t o r

I n t e r r u p tC t r l M o d e l I n te r r u p t p in s

D C RM o d e l D C R B u s

J T A GM o d e l

J T A G I n t e r f a c e

P L BM o n i t o r

IC U R d D C U R d D C U W r

B a c k e n d I n te r f a c e

V E R A M o d e ls

P L B S la v e /B a c k e n dC o n t r o l

I B M P L BS la v e M o d e l

( m e m o r y )

P r o c e s s o r L o c a l B u s ( P L B )P r o c e s s o r L o c a l B u s ( P L B )IB M

P L BA r b i t e r


Testbench - PLB/AHB SOC

D W A M B A V IP

D W A M B A V IP

IB M P L B M o d e l T o o lk it

PLB

Arb

iter

P L B (1 2 8 -b its )

P L BM a s te r

P L BS la v e 1

P L BS la v e 2

P L B M a s te r(P P C 4 4 0 )

P L B 2 A H B B r id g e(P L B S la v e 3 )(A H B M a s te r 2 )

D C R

AH

BA

rbite

r

A H B (3 2 /6 4 /1 2 8 -b its )

P L BM o n ito r

A H BM a s te r 1

A H BM a s te r 3

A H BS la v e 1

A H BS la v e 2

A H BS la v e 3

D C R

A H BM o n ito r

D C R

D C RM o n ito r

T h e s e IP 's a re n o t d e liv e re d a s a p a r t o f th e c o re k it , b u t h a s to b e in s ta lle ds e p a ra te ly . H o w e v e r th e te s tb e n c h w il l b e in s ta n t ia t in g th e s e c o m p o n e n ts .

h c lkS Y S _ p lb C lk

d c r_ c lk D C RS la v e

D C RS la v e


Implementation View coreKit Overview• RTL source for PowerPC core and PLB-to-AHB Bridge

Configurable via coreAssemblerPortable RTL validated by both IBM and Synopsys

• Implementation scripts with documentationRTL simulation in an automated verification environmentDefault floor plansIntegration of technology specific RAMsLogical and physical synthesis with clock tree synthesisScan insertion and ATPGFormal verificationPower optimization and analysis

Complete RTL-to-GDSII capability

• Documentation for SoC integrationUser Guide, Data BookApp Notes

• LicensingPowerPC license from IBMDesignWare license from Synopsys

InstructionUnit

Timers

Debug/Trace

128-bit Processor Local Bus

I-cacheControl

D-cacheControlMMU

Power Management

ComplexInteger

Pipe

SimpleInteger

Pipe

Load /StorePipe

MAC

BranchUnit

Interrupts

PowerPC 440 Core

32KB I-cachew/parity

32KB D-cachew/parity


Implementation View FlowDesign View FlowInstall Design View coreKit

Create coreConsultant workspace

Install VMC Model

Simulate VMC Modelin standalone verification environment

Simulate VMC Modelin application verification environment

Synthesize application logic using PowerPC 4xx Star IP CPU’s timing model to check approximate timing

Get Implementation View coreKit

Install Implementation View coreKit

Create coreConsultant workspace

Configure RTL

Simulate configured RTL in standalone verification

environment

Integrate technology specific RAMs

Synthesize (RTL-to-gates)

Insert scan

Create floorplan

Run physical synthesis

Create test vectors

Run STA

Formally verify gate-level netlist

Simulate gate-level netlist

Perform power analysis

Simulate configured RTL in application verification

environment


Synopsys Tool Support in coreKitProduct CapabilityVCS® RTL simulationVera Verification TestbenchDesign Compiler® Logic synthesisPhysical Compiler® Physical synthesisJupiterXT™ Design planningAstro™ CTS scripts for detailed placement and

routingDFT Compiler Design-for-test insertionTetraMAX® Test pattern generationDesignWare BIST Built-In-Self-Test capabilityPower Compiler™ Power optimizationPrimePower Full-chip power analysis


Default IBM PowerPC 440-S Floorplan

DCA top array

DCA bottom array

UTLB

ICA top array

ICA bottom array

BHT SRAM

InstructionUnit

Timers

Debug/Trace


I-cacheControl

D-cacheControlMMU

Power Management

ComplexInteger

Pipe

SimpleInteger

Pipe

Load /StorePipe

MAC

BranchUnit

Interrupts

PowerPC 440 Core

32KB I-cachew/parity

32KB D-cachew/parity


Default IBM PowerPC 405-S Floorplan

16KI-cache

16KD-cache

Timers Power Mgmt

InterruptsDebug/Trace


I-cachecontrol

D-cachecontrolMMU

InstructionUnit

BranchUnit

ExecutionUnit

MAC

GPRs

I CacheI Cache

D Cache D Cache


Synopsys DesignWare® IP portfolio

On-Chip Bus

Datapath, AMBA IP, Memory,Verification IP, Building

Block IP, 8051, 6811, etc.DesignWare Library

DesignWareVerification

LibraryDesignWareIBM PowerPC 440

DesignWare Star IP DesignWare Cores

AMBAPCI Express

PCIPCI-X

Serial I/OUSB 2.0

IEEE 1394EthernetMemory

etc.

PCI Express, PCI-X,USB 2.0, USB OTG,

IEEE 1394, etc.

DesignWare Star IP Microprocessor cores from leading Star IP providersDesignWare Library Infrastructure IP, including high-speed datapath generatorsDesignWare Cores Portfolio of digital and analog connectivity IPDesignWare Verification Library Simulation models of buses & I/O standards


Benefits for PowerPC in DesignWare

• Broad Availability25,000+ DesignWare users worldwide

• Availability of supporting IP components

Fully Integrated with AMBA™ peripherals• AMBA AHB/APB w/ automated subsystem assembly• All DesignWare peripherals supported

Native CoreConnect™ interface retained and supported

• Industry recognized first-tier customer supportExperienced technical support infrastructure

• Tested with complete design flow

On-Chip Bus


Block IP, 8051, 6811, etc.

DesignWareIBM PowerPC440/405

DesignWare Star IP

AMBAPCI Express

PCIPCI-X

Serial I/OUSB 2.0


etc.

PCI Express, PCI -X,USB 2.0, USB OTG,

IEEE 1394, etc.

On-Chip Bus


Block IP, 8051, 6811, etc.

DesignWare LibraryDesignWare Library


Library


LibraryDesignWareIBM PowerPC440/405

DesignWareIBM PowerPC440/405

DesignWare Star IPDesignWare Star IP DesignWare CoresDesignWare Cores

AMBAPCI Express

PCIPCI-X

Serial I/OUSB 2.0


etc.

PCI Express, PCI -X,USB 2.0, USB OTG,

IEEE 1394, etc.


Summary

• All program objectives achievedCycle compatibility with existing 440 and 405 coresSingle cycle cache accessTarget performance of 300 MHz (440-S) and 250 MHz (405-S) achievedPortable verification environment and critical test cases packaged in core delivery

• Synopsys is a “one-stop shop” for synthesizable PowerPC 440 and 405 cores

Complete tool flow from RTL to CTSKnowledge of CoreConnect and AMBA peripheralsSupported through DesignWareSynopsys Professional Services are experts in PowerPC core and system implementations


Synopsys and PowerA Complete and Flexible Solution

SystemSystem--Level Design CapabilityLevel Design CapabilityComplete Functional VerificationComplete Functional Verification

Complete PowerPC and SoC Implementation FlowComplete PowerPC and SoC Implementation FlowPost GDS Solution (OPC, PSM, fracturing)Post GDS Solution (OPC, PSM, fracturing)

PowerPC experiencePowerPC experienceLow power, SoC designLow power, SoC design

Complete Flow ExpertiseComplete Flow Expertise

Distribution & support (DesignWare)Distribution & support (DesignWare)Proven Reusability Methodology Proven Reusability Methodology

#1 Connectivity IP provider#1 Connectivity IP providerCore Connect and AMBA IPCore Connect and AMBA IP

IBMIBMPower.orgPower.orgFoundriesFoundries

Services

IP

Tools

Partners

Complete Synopsys Solution

Documents

Synthesizable “Power” · DCR AHB Ar b i t e r AHB (32/64 /128 -bits) PLB Monitor AHB Master1 AHB Master3 AHB Slave1 AHB Slave2 AHB Slave3 DCR AHB Monitor DCR DCR Monitor These