Synthesis and Optimization of Threshold Logic Networks-1

8/10/2019 Synthesis and Optimization of Threshold Logic Networks-1

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Synthesis and Optimization ofThreshold Logic Networks

with Application to Nanotechnologies


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Overview

Purpose of the Paper

Threshold Logic Overview

Multi-Level Threshold Network Synthesis Methodology

Experimental Results

Conclusion


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Purpose of the Paper

The main purpose of this Paper is to bridge the wide gap

that currently exists between research on the

development of nanoscale devices and research on the

development of synthesis methodologies to generate

optimized networks utilizing these devices.


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Threshold Logic Background:Threshold logic (TL) emerged in 1960s as a generalized

theory of switching logic and has long been considered as

an alternative way to compute Boolean functions.

Rapid development of synthesis and optimization toolsfor Boolean logic design led to a loss of interest in

developing similar infrastructure for designing TL circuits.

With the emergence of new devices and need for

transitioning to nonCMOS technologies because of the

scaling limitation of CMOS technology, things are now

changing in favor of threshold logic and synthesis that are

applicable to large multilevel threshold networks.


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Threshold Logic and Post-CMOS DevicesA large amount of research currently in progress in

the post-CMOS devices like:

Resonant Tunneling Diodes (RTDs),Single Electron Transistors (SETs),

Quantum Cellular Automata(QCA), and

Carbon Nano-tube FETs (CNT-FETs)

has revealed that all these devices can be used to

realize threshold logic very efficiently.


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What is Threshold Logic Gate?

A threshold logic gate has one or more binary inputs, x1, x2, . . ,xnand a single binary output. The gate is characterized by a set ofweights, W = W1, W2, . . . , Wn where Wiis the weight associatedwith inputxi, and a threshold T. The output of a threshold gate is

defined as follows:

Parameter s and represent defect tolerances that must beconsidered since variations (due to manufacturing defects,temperature changes, etc.) in the weights can lead to network

malfunction.


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Multi-Level Threshold Network

Synthesis Methodology

Theorems to describe properties of ThresholdLogic:


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Multi-Level Threshold Network

Synthesis Methodology Flow Diagram and Main steps in Multi-Level Threshold Network Synthesis Methodology

The input to the methodology is an algebraically-factored multi-output

combinational network, G, and its output is a

functionally equivalent threshold network, GT.

The synthesis algorithm begins by processing

each primary output of network G. First, the

node representing a primary output is collapsed.

If the node represents a binate function, it is splitinto multiple smaller nodes which are then

processed recursively.

If the unate node is a threshold function, it is

saved in the threshold network and the fanins of

the node are processed recursively. Otherwise,

the unate node is first split into two nodes.

If either of the split nodes is a threshold function,

Theorem 2 is used as a simplification step.

If neither of the split nodes is a threshold function,

the original node is split into multiple smaller nodes

which are then processed recursively.

The synthesis algorithm terminates when all the

nodes in network G are mapped into threshold nodes.


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The proposed methodology was implemented in a toolcalled ThrEshold Logic Synthesizer (TELS) which is

considered the first multi-output multi-level threshold

network synthesis tool.

The experiments were conducted on a 2.4 GHz Pentium

IV machine with 768MB RAM running Redhat Linux 8.0.

All the benchmarks in the MCNC benchmark suite were

run through TELS. All the synthesized networks weresimulated for functional correctness to validate our

methodology.


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Experimental Results Contd.

Experimental Results Below table lists the results for 10 of the 60 benchmarks. In this

table, one-to-one mapping refers to replacing each gate in the

optimized Boolean network with a threshold gate.


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On an average, 42% of the total execution time wasspent on threshold network synthesis while the

remaining time was spent on factoring the network.

On an average 52% average reduction is possible in gate

count and less area is required for the network.

Experiments was performed to gauge the impact of

parametric variations in the input weights on the circuit

functionality by varying from zero to three andwas fixed at one.


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The results shown in Fig. 1 demonstrate that as increases, thefailure rate decreases. This is because the network becomes more

robust. The trade-off is that the network area increases as shown

in Fig. 2 for the case V = 0.8.

Fig. 1 Fig. 2


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The results shown in Fig. 1 demonstrate that as increases, thefailure rate decreases. This is because the network is more robust.

The trade-off is that the network area increases as shown in Fig. 2

for the case v = 0.8.

Fig. 1 Fig. 2


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Conclusion

In this paper, first comprehensive threshold network synthesismethodology for multi-output multi-level networks wasintroduced. The algorithm in the introduced methodology isrecursive in nature and is based upon efficient heuristics thatpartition a logic function if it is determined to be non-threshold using an ILP formulation. Any logic sharing that

occurs in the algebraically-factored network is reflected in thethreshold network. Experimental results for the benchmarksshow that the quality of the generated networks, in terms oftotal gate count and the number of levels, is very good.


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References

Zvi Kohavi and Niraj K.Jha Threshold Logic for Nanotechnolologies , PPT.

presentation.

Tejaswi Gowda and Sarma Vrudhula., Decomposition Based Approach forSynthesis of Multi-Level Threshold Logic Circuits, Consortium ofEmbedded Systems, School of Computing and Informatics, Arizona StateUniversity, Tempe, AZ

Peter Celenski, Sorin D. Cotofana, Jose F. Lopez, Said Al-Sarawi and DerekAbbott, State-ofthe-Art in CMOS Threshold -Logic VLSI GateImplementations and Applications Research institute for AppliedMicroelectronics Universidad de Las Palmas de G.C. 35017-Spain.

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Synthesis and Optimization of Threshold Logic Networks-1