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1
IAµE
Logic Synthesis
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What Is Logic SynthesisTranslate HDL description into a cell netlist.
1. Parse (analyze) HDL.2. Translate (elaborate) design into data structure, e.g.
minterms, or generic cell netlist.3. Optimize the structure (minimize the number of terms or
cells) through factoring, substitution, and elimination.4. Technology mapping: generate netlist of technology-specific
cells.
Optimized netlist used for:
1. Post-synthesis simulation and timing analysis.2. Generating layout using place and route tool, or
generating programmable logic configuration file.
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SynthesisDesignFlow
RTL &Schematic Capture
BehavioralSynthesis Tools
RTL Description
TranslationTools
Logic Optimization
Technology Mapping
Physical DesignTools
TestGeneration
Behavioral Specification
Library
RTL Description
Unoptimized Logic Description
Optimized Logic
ModuleGenerators
CustomLayour
Fabrication
Testing Finished IC!
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Two Counter ImplementationsCounter using an adder Counter as state machineENTITY count2 IS
PORT (reset, clock: IN bit;Z: buffer INTEGER range 0 to 3);
END count2;
ARCHITECTURE count OF count2 isBEGIN
PROCESS(reset, clock)BEGIN
IF (clock'EVENT and clock = '1') THENZ <= Z+1;
END IF;IF (Z > 3 or reset = '1') THENZ <= 0;
END IF;END PROCESS;
END count;
ENTITY count2 ISPORT (clock, reset: IN bit;
Z: OUT bit_vector(1 downto 0));END count2;
ARCHITECTURE count OF count2 ISTYPE statetype IS (s0, s1, s2, s3);SIGNAL state : statetype;BEGIN
PROCESS (reset, clock)BEGINIF (reset = '1') THEN
state <= s0; Z <= "00";ELSIF (clock'EVENT and clock = '1') THEN
CASE state ISWHEN s0 => state <= s1; Z <= "00";WHEN s1 => state <= s2; Z <= "01";WHEN s2 => state <= s3; Z <= "10";WHEN others => state <= s0; Z <= "11";
END CASE;END IF;
END PROCESS; END count;
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Realization of 2-bit Counters
D Q
CLR1
2Which is more efficient?
Clock
Reset
D Q
CLR
NextStateLogic
2Adder-Based
Clock
Reset
State Machine
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Limits of VHDL and Verilog for SynthesisVHDL and Verilog we not developed as design languages• Developed as specification and documentation languages• Logic synthesis came later• Not nearly as well-developed or mature as programming languages• The way we code can significantly change the synthesized circuit
In general, we can only synthesize logic• Boolean logic • Synchronous state machines
To get special behavior, design module at low level, then include it as a component.
Examplesignal A,B,F: bit_vector(3 downto 0);F <= A + B;
Usually produces a ripple-carry adderTo get a carry lookahead adder, design it at low level.
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Synthesizing MemoryDigital VLSI systems are made up of:1. “Random” logic2. Memory 3. Interconnects
We treat memory differently from logic• Small memory can be synthesized from logic element.• Memory-from-logic doesn’t work well for large memories: it soon becomes very inefficient.• Memory has very regular structure; is efficiently implemented with special structures, at the transistor level.• Special purpose memory “module builders” are available to generate efficient memories.
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VHDL Model of a 256x4 bit Clocked SRAMentity MEM_MODEL is
port(CLK, RW: in BIT;INDEX: in INTEGER range 0 to 255;DATA_IN: in BIT_VECTOR(3 downto 0);DATA_OUT: out BIT_VECTOR(3 downto 0));
end MEM_MODEL;
architecture BEHAVE of MEM_MODEL istype MEM_TYPE is array(0 to 255) of BIT_VECTOR(3 downto 0);signal REG_FILE: MEM_TYPE;
beginprocess(CLK)begin
wait until CLK='1';if RW = '1' then
DATA_OUT <= REG_FILE(INDEX);else
REG_FILE(INDEX) <= DATA_IN;end if;
end process;end BEHAVE;
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ASIC Static Random Access Memory (SRAM)Random Access means access time independent of location in memory.
Simple Memory: A Register File
D Q
D Q
D QDec
oder
D Qa0 a1
Sele
ctor
Write:1. Present address to decoder2. Enable clock on selected register
a0
a1 Data Out
Read:• Present address to selector• Latch output data
Data In
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Limitations of Register File MemoryUseful memory is large: 103 to 1010 bits
Register file does not scale well to large memories•Address decoder & selector grow very large•Fanout on data line is very large•Fanout on clock line is high•Logic-based latch is not area-efficient
Large chip areaLong propagation delays
Implementing large memories efficiently requires transistor-level design.
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6-Transistor Memory Element
nMOS Pass Transistor
Data Out
nMOS Pass Transistor
Data In
Write Read
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Transistor Sizing for Memory Element
Data In Data Out
Write Read
Question: How can we resolve the bus conflict, where T1 and In2 drive the same node?
Answer: Make β of pass transistors greater the β of inverter transistors.
21 4 InvT ββ ≥
214
InvT LW
LW
≥
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Memory Elements in Row-Column Matrix Organization
Column (Bit) decoder
Row
(Wor
d) D
ecod
er
Address
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Memory Element in Matrix
VDD
VSS
bit -bit
word
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Issues in Memory Design • Use minimal cell in row-column matrix.• Large address requires special design: decoder tree build with pass transistors.• Sense amplifier requires careful design to reliably detect low-level signals.• For large busses, pre-charge to VDD/2, then discharge selected nodes only.• Quasi-dynamic logic requires special timing.
Design of large memories is a specialty• Falls outside the domain of logic synthesis.• Special purpose memory “module builders” sometimes available.• For high performance, us memory-specific fabrication process; use off-chip memory.
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Data Path vs Control Logic
Data Path Data OutData In
ControlLogic
We often divide a design into data path and controlcomponents.•Data path: transforms bit patterns.•Control logic: state machine, determines next processing step.•Special software tools are available for high-level data path design; e.g., Signal Processing applications.
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Synthesis Summary
Logic synthesis is one of the great achievements of the past two decades.•Synthesis enables much larger and complex designs.•Enables technology mapping and design re-use: re-compile a design to a new target technology.•Enables libraries of pre-designed modules for faster time to market.•Logic optimizers today produce designs that are as efficient as hand designs on small problems, and more efficient on large ones.
Logic synthesis is not perfect.•Logic synthesis doesn’t cover all design cases, and must be supplemented with hand designs or special tools.•Hardware Design Languages need to mature.