Synopsis Sam

7/27/2019 Synopsis Sam

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NETAJI SUBHAS INSTITUTE OF TECHNOLOGY

Azad Hind Fauj Marg, Sector-3, Dwarka

New Delhi-110078.

Project Report

On

ELECTRONIC JACKPOT MACHINE

Submitted By: Under the Guidance of:

SAMBHAV JAIN Sh. D.V.GADRE

Roll-No.102/SP/12


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ACKNOWLEDGEMENT

A number of individuals have contributed to the preparation of this project. I gratefully

acknowledge the contribution of each of them.

I take the opportunity to express my gratitude and heartfelt thanks to my project guide

Sh. D.V. Gadre (N.S.I.T) for his valuable guidance and constant inspiration without

which this project might have not come into existence.

SAMBHAV JAIN


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TABLE OF CONTENTS

1. About the project.

2. Implementation

2.1 Hardware Implementation

2.1.1 Component description

2.2 Software Implementation

2.2.1 VHDL Code

2.2.2 Simulation output

3. Circuit Diagram

4. RTL Schematics

5. References


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ABOUT THE PROJECT

This project is a digital game based on digital circuit and logics, implemented in CPLD

(complex programmable logic device) with the help of VHDL as software. This project

facilitates a single player for playing a game in which the player will press the play switches toget different colors on three multicolor led, if he/she can get it then the player will win.

DETAILED DESCRIPTION

ELECTRONIC JACKPOTMACHINE is played by a single player.

Each time the player plays the game he/she will start the game by pressing the RESET switch, it

glows the START led. There is a switch corresponding to each led. On pressing the switch therespective led start changing color till the player pressed the switch. As the player released the

switch, led glow with a fixed color (Red or Green or Blue).

Then the player presses the next leds switches and will do the same.

Wining Condition :

1. All led should have different color, if it happen WIN led will glow.

Losing Condition :

1. Atleast two led have same color, if it happen LOSE led will glow.


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RULES OF THE GAME

a) The game will start by first pressing the RESET switch (START led will glow).

b) Leds switches should be kept pressed only once and one at a time.

c) Once a leds color is set its corresponding switch should not be pressed again.

d) Switches should be pressed in sequence.

e) If either WIN or LOSE led glows, the game is completed and a new game will start only

by pressing RESET switch.


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2) IMPLEMENTATION

2.1) HARDWARE IMPLEMENTATION

The ELECTRONIC JACKPOTMACHINE is programmed onto a CPLD using VHDL. The

system consists of a clock input of 12 Hz .

2.1.1)COMPONENT DESCRIPTION

1) POWER SUPPLY & Other Related Accessories:

a) Four - press and release switch

b) One 230-12 V DC adapter

c) Four- Diodes IN-4007(For Bridge rectifier).

d) One -Regulator IC LM-7805(For 5v regulated output)

e) One - Heat sink(For elimination of heat from the regulator IC)

f) Two Capacitors( 2.2 micro farad/50 volt )

g) Four Ceramic Capacitors( 3 (104), 1(103) )

h) 10 NOS - Resistances 1k(10nos)

i) 6 LED ( 4 RGB , 2 green )

j) One IC 555 Timer ( clock generation)

2) CLOCK :

Clock Frequency generated is of value 12.5 Hz. Following components are used for the

generation of clock:

a) IC 555

b) Two capacitor of value 2.2 microfarads and 10 microfarads.

c) Two resistances of values as 240 Ohms, 5800 ohms.


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3) SWITCHES:

One reset switch with 1k ohm resistance and three play switches with 1k resistance.

4) JTAG CONNECTOR:

JTAG (JOINT TEST ACTION GROUP) connector has been used to program the CPLD.

5) CPLD:

CPLD Used: XILINX XC-9572_15 44 pin IC.

6) LED DISPLAY:

4 RGB LEDS connected via 1 k resistance with CPLD.


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2.2) SOFTWARE IMPLEMENTATION

The coding is done on Xilinx ISE 8.2i using VHDL.

A behavioral model of design is followed for the definition of the subparts of the main design,

like the counters, comparator, adder, decoder etc. This is followed by a structural integration

of these to form the game. The CPLD used was XC-9572PC44.

2.2.1) VHDL Code----------------------------------------------------------------

------------------

----------------------------------------------------------------

------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jack is

port ( sw1, sw2, sw3, clock, reset : in std_logic;

led1, led2, led3 : out std_logic_vector(2 downto 0);

Win, Lose : out std_logic);

end jack;

architecture Behavioral of jack is

component main_fsm is

port( E1,E2,E3,rst,clk,eq1,eq2 : in std_logic;

c1,c2,c3,com1,com2,w,l,rst_out: out std_logic

);

end component;

component counter is

port ( Ea, clk, rst : in std_logic;

Qa: out std_logic_vector(1 downto 0));


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end component;

component decoder is

port ( Q1 : in std_logic_vector(1 downto 0);

Da: out std_logic_vector(2 downto 0));

end component;

component comparator_A is

port (en1,rst : in std_logic ;

A, B: in std_logic_vector(1 downto 0);

eq_1 : out std_logic);

end component;

component comparator_B is

port (en2,rst : in std_logic ;A,B,C: in std_logic_vector(1 downto 0);

eq_2 : out std_logic);

end component;

signal temp_rst : std_logic;

signal cenb1,cenb2,cenb3,coe1,coe2 : std_logic;

signal equal1,equal2: std_logic;

signal tempcount1,tempcount2,tempcount3: std_logic_vector(1 downto 0);

begin

stage1: main_fsm port

map(sw1,sw2,sw3,reset,clock,equal1,equal2,cenb1,cenb2,cenb3,coe1,coe2,win,lose,temp_rst);

stage2: counter port map(cenb1,clock,temp_rst,tempcount1);

stage3: decoder port map(tempcount1,led1);

stage4: counter port map(cenb2,clock,temp_rst,tempcount2);

stage5: decoder port map(tempcount2,led2);

stage6: comparator_A port map(coe1,temp_rst,tempcount1,tempcount2,equal1);

stage7: counter port map(cenb3,clock,temp_rst,tempcount3);stage8: decoder port map(tempcount3,led3);

stage9: comparator_B port map(coe2,temp_rst,tempcount1,tempcount2,tempcount3,equal2);

end Behavioral;

--------------------------------------------------------------------------------------------------------

library IEEE;


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use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main_fsm is

port( E1,E2,E3,rst,clk,eq1,eq2 : in std_logic;

c1,c2,c3,com1,com2,w,l,rst_out: out std_logic

);end main_fsm;

architecture Behavioral of main_fsm is

type state is (S0,S1,S2,S3,S4,S5,S6,S7);

begin

process(E1,E2,E3,rst,clk,eq1,eq2)

variable x:state;

beginif(rst = '1')then

x:= S0;

c1


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c3


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c2


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c1


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end if;

elsif(x = S2)then

if (Ea='1')then

Qa


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end comparator_A;

architecture Behavioral of comparator_A is

begin

process(en1,rst)

begin

if(rst='1')then

eq_1


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end if;

end if;

end process;

end Behavioral;

------------------------------------------------------------------------------------------------------------------

Pin Assignment:-

NET "clock" LOC = "P8" ;NET "led1" LOC = "P13" ;

NET "led1" LOC = "P12" ;







NET "led3" LOC = "P33" ;NET "Lose" LOC = "P44" ;

NET "reset" LOC = "P22" ;

NET "sw1" LOC = "P18" ;

NET "sw2" LOC = "P19" ;

NET "sw3" LOC = "P20" ;

NET "Win" LOC = "P43" ;

--------------------------------------------------------------------------------------------------------------


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CIRCUIT DIAGRAM


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RTL SCHEMATICS


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REFRENCES

a) Circuit Design with VHDL V.A. Pedroni

b) Digital Logic Design with VHDL Stephen Brown & Zvonko Vranesicc) Digital Systems Design using VHDL- Charles Roth

d) CPLD datasheet- Xilinx.com

e) Datasheet.com

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Synopsis Sam