R.V. College of Engineering, Bangalore(Autonomous Institution Affiliated to VTU)

Department of Electronics and Communication Engineering

7th Semester

Synopsis for the Mini Project

Project Title:

DESIGN, DEVELOPMENT AND PERFORMANCE ANALYSIS OF GNRFET BASED 4-BIT CPU

Group Members USN Signature Phone No.

1 KARTHIK R K 1RV12EC075

8050975820

2 MEGARAJ T. MAHADIKAR 1RV12EC088

8792817133

3 MUNIRAJ R. 1RV12EC092

7353481265

4 SURAJ M S 1RV12EC163

9482544822

Accepted/Rejected

Guide Signature:

Guide Name:

1

Date:

INTRODUCTION

The conventional CMOS technology was considered as a replacement to NMOS technology because of the lower power consumption. The chip density increased because of shrinking size of the transistors. Even though each CMOS transistor dissipates very little power, when it switches, the huge number of transistors switching at very high rates of speed have made Power consumption, a major design constraint.

Apart from this, the use of portable electronic devices and micro scale electronic devices has increased exponentially during recent years. The main requirement of these handheld devices is reduced power consumption, compact (small area) and high speed of operation. High performance CPUs that are compact and consume very less power are to be designed. The CPU consists of ALU (Arithmetic and Logic Unit) and Control Unit, which basically consist of registers, shifters, Parallel adder, multiplexers and demultiplexers. The low power concepts are applied at the architectural level to design a low power CPU.

The project goes one step further by making low power design at the device level by using Graphene Nano Ribbon based FET. The GNRFET is an emerging technology that received much attention in recent years. Recent work on GNRFET has shown that they consume very low power and prove to be a potential replacement to conventional CMOS in Low power designs.

AIM

The project aims to build a CPU, essentially individual modules using conventional CMOS and also GNRFET and compare and analyze the results obtained through simulation. The objective is to reason out the behavior of GNRFET that is corresponding to the obtained results.

SCOPE and OBJECTIVE

The primary scope of the project is to implement high performance CPUs in hand-held devices. As Mobile computing is growing with good interfaces like touch screen and voice inputs, the need for 32-bit and 64-bit CPUs is ever increasing. At the same time these interfaces are power hungry. A larger touch-screen will consume higher power. This is where low power modules of the CPU need to be designed.

The objectives of the project are:

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Simulate Parallel adder, multiplexer, demultiplexer, shift register among a few using conventional CMOS technology

Optimize the logic circuit for Low power and simulate to note the results in hSPICE

Simulate all the modules using GNRFET and note the results in hSPICE. Compare the results with conventional CMOS technology

Analyze and find the behaviors of GNRFET responsible for the results obtained.

ADVANTAGES OF PROJECT

The project proposes a 4 bit low power CPU which forms the foundation for larger computers. For applications where power is the major constraint, these designs serve the purpose. All the portable devices would become less power without compromising on speed and area. Also, GNRFETs promote eco-friendliness and spread the “GO GREEN” concept. A detailed analysis of the results would lead us to explore the specific characteristics of graphene, responsible for the results obtained. This would help the use of graphene in different fields, walking along with the emerging technologies.

METHODOLOGY ADOPTED AND SYSTEM IMPLEMENTATION

The CPU consists of ALU and CU. The sub modules and design methodologies are discussed below:

ALU Design: ALU is the digital function that implements the micro-operations on the information stored in processor registers. The methodology includes the design of arithmetic section independently and then modifies the so designed circuit to obtain the required logic operations. The design of ALU depends on the types of logic operations chosen to be implemented. We consider a parallel adder as the basic component and bring out various operations out of it. We then integrate ALU with the processor registers and shifter through multiplexers, to form the whole processor unit.

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Fig1. 4-bit parallel adder with subtractor functionality forms the ALU

CU design: The control unit is a component of the CPU which translates the instructions to op-codes and operates on the ALU. The control circuitry consists of Register file, Multiplexer and shifter. The register file consists of set of registers which store the operands for arithmetic or logic operation input as well as the output is stored in the registers. Multiplexers are used to select the respective registers for input and also to store the output in the destined register. The shifter is used to shift the bits of the output to achieve multiplication functionality. These modules are created using conventional CMOS as well as GNRFET and simulated to compare the results.

MUX design results: Multiplexer (Data selector) is a combinational logic circuit that selects one of the 2n inputs and route it to a single output line. MUX designing is an important aspect of our projects since these are the building block of almost all sub modules. So, multiplexers with low power consumption along with minimum delay and area requirements needs to be designed [2].

We have modeled 32:1 mux using basic gates, 2:1 mux, 4:1 mux, 8:1 mux and simulated all the circuits and analyzed the IC parameters using HSPICE at 10nm MOS and GNRFET technologies. We have found that the MUX designed using GNRFET consumes less power compared to conventional MOS technology.

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Fig2.Power Dissipation in 32:1 MUX using GNRFET, CNFET and MOS technologies

Graphene

Graphene is a promising material in the field of VLSI. It was discovered in the year 2004[3]as a two-dimensional (2D) material. Graphene is pure carbon in the form of a very thin, nearly transparent sheet, one atom thick. Single-layer Graphene is a purely two-dimensional material with a lattice consisting of regular hexagons with one carbon atom at each corner.It can be produced in large quantities using CVD process with electronic mobility as high as 15000 cm2/Vs. Concomitant to the large mobility, Graphene conductivity is also high and is observed to be better than that of Copper. With a most conservative estimate, the conductivity of Graphene, at a carrier density of 1012 m-2 is arrived at 9.6 x 105 Ω-1cm-1 as against a value of 6 x 105 Ω-1cm-1 for Copper [4].

fig 3. Electron mobility vs. band gap for different materials.

Intrinsic 2-D Graphene sheets have zero band gap making them good conductors. But since we require semiconducting characteristics, Graphene is patterned into 1-D narrow strips known as Graphene Nano Ribbon (GNR) which opens up band gaps. The band gap

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of GNR is inversely proportional to its width. With width < 2nm, GNRs exhibit good semiconducting properties.[5]

DETAILS OF HARDWARE AND SOFTWARE USED

HSCPICE is the primary tool used to simulate the circuits and for transient, dc and frequency domain analysis of the circuits. The tool provides GNRFET model files, which is used to simulate the modules based on GNRFET. The model file consists of the design parameters of the GNRFET and plays a crucial role in the behavior of the FET.

Fig4. HSPICE reference manual by SYNOPSIS

FUTURE WORK AND CONCLUSION

The project is a proof of concept that GNRFET based designs provides low power capability to ICs. The project also reasons out the characteristics responsible for the simulated behavior of the modules and the CPU as a whole.

The work can be extended into building other modules like timers, memory and I/O subsystems along with the CPU to build a low power microcontroller.

REFERENCES

[1]E. V. Castro et al., “Biased bilayer Graphene: Semiconductor with a gap tuneable by the electric field effect”, Phys. Rev. Lett., vol. 99, p. 216802, 2007.

[2]B. Dillikumar, K. Charankumar, M. Bharathi “Low power multiplexer based full adder using pass transistor logic”, International Journal of Advanced Research in Computer Engineering & Technology, Vol.1, ISSN: 2278 – 1323

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[3]K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S.V. Dubonos, I. V. Grigorieva, and A. A. Firsov, “Electric field effect in atomically thin carbon films,” Science, vol. 306, pp. 666–669, 2004.

[4] M. Han et al., “Energy band-gap engineering of Graphene nanoribbons”, Phys. Rev. Lett., vol. 98, p.206805, 2007.

[5] Ying-Yu Chen, Amit Sangai, Morteza Gholipour, and Deming Chen, “Graphene Nano-Ribbon Field effect transistors as future low power devices”, Symposium on Low power electronics and designs, IEEE, 2013

[6]Na Gong ,Jinhui Wang, Sridhar R “Application-driven power efficient ALU design methodology for modern microprocessors”, Santa Clara, CA, March 2013,ISSN :1948-3287

[7] Zhijin Guan ,Wenjuan Li, Weiping Ding, Yueqin Hang, “An Arithmetic Logic Unit design based on reversible logic gates” , Victoria, BC, 26 Aug. 2011, ISSN :1555-579

[8] Raut, V.,Dakhole, P.K, “Design and implementation of four bit arithmetic and logic unit using hybrid single electron transistor and MOSFET at 120nm technology” , Pune, Jan. 2015, INSPEC Accession Number: 15058390

[9]Dubey, V.; Sairam, R., “An Arithmetic and Logic Unit Optimized for Area and Power” , Advanced Computing & Communication Technologies (ACCT), 2014 Fourth International Conference on Year: 2014

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