sWitching theory ppt

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CSET 4650Field Programmable Logic Devices

Dan Solarek

Logic FamiliesIntroduction & Overview


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Logic Families

Logic Family : A collection of different ICs thathave similar circuit characteristics

The circuit design of the basic gate of each logicfamily is the same

The most important parameters for evaluating andcomparing logic families include :

Logic Levels

Power Dissipation

Propagation delayNoise margin

Fan-out ( loading )


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Example Logic Families

General comparison or three commonly available logic

families.

the most important to understand


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Implementing Logic Circuits

There are several varieties of transistorsthe

building blocks of logic gatesthe most important

are:

BJT (bipolar junction transistors)one of the first to be invented

FET (field effect transistors)

especially Metal-Oxide Semiconductor types (MOSFETs)

MOSFETs are of two types: NMOS and PMOS


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Transistor Size Scaling

Performance improves as size is decreased: shorter switching time, lower power consumption.

2 orders of magnitude reduction in transistor size in 30 years.


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Moores Law

In 1965, Gordon Moore predicted that the number of

transistors that can be integrated on a die would

double every 18 to 14 months

i.e., grow exponentially with timeConsidered a visionarymillion transistor/chip

barrier was crossed in the 1980s

2300 transistors, 1 MHz clock (Intel 4004/4040) - 1971

42 Million transistors, 2 GHz clock (Intel P4) - 2001

140 Million transistors, (HP PA-8500)


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Moores Law and Intel

From Intels 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond


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TTL and CMOS

Connecting BJTs together gives rise to a family of logic gatesknown as TTL

Connecting NMOS and PMOS transistors together gives rise

to the CMOS family of logic gates

BJTMOSFET

(NMOS, PMOS)

TTL CMOS

transistor types

logic gate families


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Electrical Characteristics

TTL

faster (some versions)

strong drive capability

rugged

CMOS

lower power consumption

simpler to make

greater packing densitybetter noise immunity

Complex ICs contain many millions of transistors

If constructed entirely from TTL type gates would melt

A combination of technologies (families) may be used

CMOS has become most popular and has had greatest development


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For a High-state gate driving a second gate, we define:

VOH(min), high-level output voltage, the minimum voltage level that a logic

gate willproduce as a logic 1 output.

VIH(min), high-level input voltage, the minimum voltage level that a logic

gate will recognize as a logic 1 input. Voltage below this level will not be

accepted as high.IOH, high-level output current, current that flows from an output in the logic

1 state under specified load conditions.

IIH, high-level input current, current that flows into an input when a logic 1

voltage is applied to that input.

Voltage & Current

Ground

VIH

VOH

I OH I IHTest setup formeasuringvalues


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For a Low-state gate driving a second gate, wedefine:

VOL(max), low-level output voltage, the maximum voltage levelthat a logic gate willproduce as a logic 0 output.

VIL

(max), low-level input voltage, the maximum voltage levelthat a logic gate will recognize as a logic 0 input. Voltage abovethis value will not be accepted as low.

IOL , low-level output current, current that flows from an outputin the logic 0 state under specified load conditions.

IIL , low-level input current, current that flows into an input when

a logic 0 voltage is applied to that input.

Voltage & Current

Inputs areconnected to Vccinstead ofGround

Ground

VILVOL

IOL IIL


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Electrical Characteristics

Important characteristics are:

VOHmin

min value of output recognized as a 1

VIHminmin value input recognized as a 1

VILmaxmax value of input recognized as a 0

VOLmax max value of output recognized as a 0

Values outside the given range are not allowed.logic 0

logic 1

indeterminate

input voltage


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Noise Margin

Manufacturers specify voltage limits to represent the logical0 or 1.

These limits are not the same at the input and output sides.For example, a particular Gate A may output a voltage of 4.8V when itis supposed to output a HIGH but, at its input side, it can take a

voltage of 3V as HIGH.

In this way, if any noise should corrupt the signal, there issome margin for error.


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Noise Margin

If noise in the circuit is high enoughit can push a logic 0 up or drop alogic 1 down into the indeterminateor illegal region

The magnitude of the voltagerequired to reach this level is thenoise margin

Noise margin for logic high is:NMH= VOHminVIHmin

VOHmin

VIHmin

VILmax

VOLmaxlogic 0

logic 1

indeterminate

input voltage


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Noise Margin

Difference between the worst case output voltage of

one stage and worst case input voltage of next stage

Greater the difference, the more unwanted signal that

can be added without causing incorrect gateoperation

NMhigh = VOHmin - VIHmin

NMlow= VILmax - VOLmax


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Given the following parameters, calculate the

noise margin of 74LS series.

Parameter 74LS

VIH(min) 2VVIL(max) 0.8V

VOH(min) 2.7V

VOL(max) 0.4V

Solution:High Level Noise Margin, VNH= VOH(min) - VIH(min)=2.7V-2.0V=0.7V

Low Level Noise Margin, VNL= VIL(max) - VOL(max)=0.8V-0.4V=0.4V

Worked Example


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Noise immunity of a logic circuit refers to the circuits abilityto tolerate noise voltages on its inputs.

A quantitative measure of noise immunity is called noisemargin

High Level Noise Margin, VNH= VOH(min) - VIH(min)Low Level Noise Margin, VNL= VIL(max) - VOL(max)

Noise Margin & Noise Immunity

Logic 1

Logic 0Logic 0

Logic 1VOH (min)

VOL (max)

VIH (min)

VIL (max)

VNH

VNL

Output Voltage Ranges Input Voltage Ranges


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Further Important Characteristics

Thepropagation delay (tpd) which is the time

taken for a change at the input to appear at the

output

Thefan-out, which is the maximum number ofinputs that can be driven successfully to either

logic level before the output becomes invalid


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Speed: Rise & Fall Times

Rise Time

Time from 10% to 90% of signal, Low to High

Fall Time

Time from 90% to 10% of signal, High to Low

rise time

10% 90% 90% 10%

fall time


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A logic gate always takes some time to change states

tPLHis the delay time before output changes from low to high

tPHLis the delay time before output changes from high to low

both tPLH& tPHL are measured between the 50% points on the

input and output transitions

Speed: Propagation Delay

50%Input

Output

0

0

tPHL tPLH


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Power Dissipation

Static

I2R losses due to passive components, no input signal

Dynamic

I2R losses due to charging and discharging capacitancesthrough resistances, due to input signal


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Speed (propagation delay) and power consumptionare the two most important performance parametersof a digital IC.

A simple means for measuring and comparing the

overall performance of an IC family is the speed-power product (the smaller, the better).

For example, an IC hasan average propagation delay of 10 ns

an average power dissipation of 5 mWthe speed-power product = (10 ns) x (5 mW)

= 50 picoJoules (pJ)

Speed-Power Product


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Logic Family Tradeoffs

Looking for the best

speed/power product

tpand Pd are normally

included in the data

sheet for each device

Older logic families

are the worst

CMOS is one of thebest

FPGAs use CMOS


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Comparison of Logic Families


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TTL - ExampleSN74LS00

Recommended operating conditionsVccsupply voltage 5V 0.5 V

input voltages VIH= 2VVIL= 0.8V

Electrical Characteristicsoutput voltage VOH= 2.7V(worst case) VOL= 0.5V

max input currents IIH= 20AIIL= -0.4mA

propagation delay tpd= 15 nS

noise margins for a logic 0 = 0.3Vfor a logic 1 = 0.7V

Fan-out 20 TTL loads

5 Volt

0 Volt

0.8

0.5

2.0

2.7

Input

Range

for 1

Input

Range

for 0

Output

Range

for 0

Output

Range

for 1


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Fan-In

Number of input signals to a gate

Not an electrical property

Function of the manufacturing process

NAND gate with a

Fan-in of 8


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Fan-Out

A measure of the ability of the output of one gate todrive the input(s) of subsequent gates

Usually specified as standard loads within a singlefamily

e.g., an input to an inverter in the same family

May have to compute based on current driverequirements when mixing families

Although mixing families is not usually recommended


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VOH

IIH

Low

VOL

IIL

High

Current Sourcing and Sinking

Current-source : the driving gate produces a

outgoing current

Current-sinking : the driving gate receives an

incoming current


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Fan-Out

An illustration of fan-out and the associated sourceand sink currents


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How many 74LS00 NAND gate inputs can be driven

by a 74LS00 NAND gate outputs ?

Solution:Refer to data sheet of 74LS00, the maximum values of

IOH = 0.4mA, IOL= 8mA, IIH= 20uA, and IIL= 0.4mA

Hence,

fan-out(high) = IOH(max) / IIH(max)=0.4mA/20uA=20

fan-out(low) = IOL(max) / IIL(max)=8mA/0.4mA=20,

the overall fan-out = fan-out(high) or fan-out(low) whichever is lower.

Hence, overall fan-out = 20

Worked Example


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A logic gate can supply a maximum outputcurrentIOH(max), in the high state or

IOL(max), in the low state

A logic gate requires a maximum inputcurrentIIH(max), in the high state or

IIL(max), in the low stateRatio of output and input current decide how many logicgates can be driven by a logic gate

fan-out(high) = IOH(max) / IIH (max)

fan-out(low) = IOL(max) / IIL(max)

overall fan-out = fan-out(high) or fan-out(low) whichever is lower

A typical figure of fan-out is ten (10)

Gate Drive Capability: Fan-Out


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Wired-AND

Open collector outputs connected together to a common pull-up resistor

Any collector can pull the signal line low

Logically an AND gate


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Tri-State Logic

Both output transistors of totem-pole output are turned off

Usually used to bus multiple signals on the same wire

Gates not enabled present high-Z to bus and therefore do

not interfere with other gates putting signals on the bus


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Electronic Combinational Logic

Within each of these families there is a large variety of different devicesWe can break these into groups based on the number gates per device

Acronym Description No Gates Example

SSI Small-scale integration 1M 80486/80586


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SSI Devices

Each package contains a code identifying the package

N74LS00

Manufacturers Code

N = National Semiconductors

SN = Signetics

Specification

Family

LLS

H

Member00 = Quad 2 input NAND

02 = Quad 2 input Nor

04 = Hex Invertors

20 = Dual 4 Input NAND


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7400 Series History

1960s space program drove

development of 7400 seriesConsumed all available devices for

internal flight computer

$1000 / device (1960 dollars)

10:1 integration improvement over

discrete transistors

1963 Minuteman missile forced

7400 into mass productionDrove pricing down to $25 / circuit

(1963 dollars)


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7400 Series Evolution

BJT storage time reduction by using a BC Schottky diode.

Schottky diode has a Vfw=0.25V. When BC junction becomes forward

biased Schottky diode will bypass base current.

B

C


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Too Much of a Good Thing?

Families

Packages

Reliability options

Speed grades

Features

Functions

An availability nightmare! >> 500K unique devices

Diff t F ili D t ll S k


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Different Families Dont all Speakthe Same Language


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Sometimes Things Get Lost orAdded in the Translation*

Different families arent always on speaking terms with one another


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The World of TTL


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Success Drives Proliferation

New families introduced based onHigher performance

Lower power

New features

New signaling threshold

Spawned over 32 unique families!

19602003


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Success Drives Proliferation

Products introduced in the 1960are near the end of their lifecycle

Decreasing supplier base

Increasing prices

Not recommended for newdesigns

Products considered to bemature are about 2 decadesinto their life cycle

High-volume production

Multiple suppliers

Low prices

Newer products are only a fewyears into their life cycle

High performanceHigh level of vendor andsupplier support

Newest technologies

Higher prices


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Characteristics: TTL and MOS

TTL stands for Transistor-Transistor Logic

uses BJTs

MOS stands for Metal Oxide Semiconductoruses FETs

MOS can be classified into three sub-families:

PMOS (P-channel)

NMOS (N-channel)CMOS (Complementary MOS, most common)

Remember:


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A

B Y O/P

+Vcc

Q1

Q

2

Q3

Q4

4K 1.6K 130R1 R2

R3

R4

1K

I CQ1

D 3

D1 D2

A B ICQ1

Q1

Q2

Q3

Q4

Y O/P

0 0 + ON OFF OFF ON 1



1 1 OFF ON ON OFF 0

A standard TTL NAND gate circuit

Table explaining the operation of the

TTL NAND gate circuit

TTL Circuit Operation


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Transistor-Transistor Logic Families

Transistor-Transistor Logic Families:

74L Low power

74H High speed

74S Schottky74LS Low power Schottky

74AS Advanced Schottky

74ALS Advance Low power Schottky


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+VDD

O/P

I/P

S

D

D

S

Q

Q

1

2

I / P Q1 Q2 O / P

0 O N O F F 1

1 O F F O N 0

Table explaining the operation ofthe CMOS inverter circuit

A CMOS inverter circuit

MOS Circuit Operation


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CMOS Logic Families

CMOS Logic Families

40xx/45xx Metal-gate CMOS

74C TTL-compatible CMOS74HC High speed CMOS

74ACT Advanced CMOS -TTL compatible


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CMOS Family Evolution

CMOS Logic Trend: Reduction of dynamic losses

(cross-conduction, capacitive charge/discharge cycles)

by decreasing supply voltages:

12V5V 3.3V 2.5V 1.8V 1.5V

Reduction of IC power dissipation is the key to:lower cost (packaging)

higher integration

improved reliability


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vi

vo


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Comparison Logic Families


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speed power product = a constant

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