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Order Number: 272907-001 July, 1996 Switched Ethernet Reference Design Description A SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS

SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

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Page 1: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996Switched Ethernet ReferenceDesign Description

ASWITCHED ETHERNETREFERENCE DESIGN SCHEMATICS

Page 2: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Index to Reference Design Schematics

Circuit Sheets+3.3V Supply for Processor ............................................................................................................3DIP Switch ....................................................................................................................................25DRAM Controller FPGA ..............................................................................................................29Dual Serial Port (AM85C30) ........................................................................................................27EPROM, 128Kx8 ..........................................................................................................................27Flash Memory ...............................................................................................................................28Hx Processor .................................................................................................................................32Input and Output Ports ..................................................................................................................25Input Power Connectors, P25 and P26 .........................................................................................33Jx Processor and Address Latch ...................................................................................................31LED, Processor Fail .........................................................................................................................2LED, User LEDs for Debugging ..................................................................................................25LED, Voltage Indicators ..................................................................................................................2Misc Logic FPGA .........................................................................................................................29PCI Clock Distribution ...................................................................................................................3PCI Bus Arbiter ..............................................................................................................................1PCI Expansion Connector .............................................................................................................33PCI to 80960 Bridge Chip ..............................................................................................................1Processor Clock Distribution ..........................................................................................................2Processor DRAM SIMM Sockets .................................................................................................30Power Up Reset ...............................................................................................................................2Serial EEPROM ............................................................................................................................25Serial Port Driver/Receivers .........................................................................................................27Slow Data Bus Transceiver ...........................................................................................................26VPP Switch (for Flash Programming) ............................................................................................3

NOTE: The reference design schematic was originally scaled for printing on B size (11”x17”) paper. In order to incorporate the drawings into this document, it was necessary to par-tition some of the sheets, resulting in “a” and “b” sheets. For example, Sheet 2 of the original drawing is shown on two sheets in this document identified as sheets “2a” and “2b”.

Note that it was necessary to create “a” and “b” sheets for only about half of the original schematics.

Page 3: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 1a

BYPASS CAPACITORS FOR U10

C10.1

VCC

U10

PKG_TYPE=PQFP208A

25302429

152

49

PCI9060

VCC;1,38,53,60,68,83,105VCC;124,144,157,167,184

GND;143,156,166,183,193,208

GND;22,37,45,52,59,67,75,82GND;90,98,104,114,123,134

NC=6,7,48,99,100,161,162,163,164,168

2731

58

62

174

66

171819

56

50

65

16

74

26

910

23

69

151165

61

55

63

51

57

173171172176175

12131415

8

64

170

54

70717273

20

878889919293

3233

94

34353639404142434446

95

47767778798081848586

9697

10KR6

10KR9R7

10K 10KR8

PLX_USERO

DACK1DACK0DREQ1DREQ0

LINTO

TEST

WAITO

USEROUSERI

TRDY

STOP

SHORT

SERR

S2S1S0

RST

REQ

READYOREADYI

PERR

PCHK

PAR

NB

MODE1MODE0

LW/R#

LSERR LRESETOLRESETI

LOCK

LLOCK

LINTI

LHOLDALHOLD

LDSHOLD

LD9LD8LD7LD6LD5LD4

LD31LD30

LD3

LD29LD28LD27LD26LD25LD24LD23LD22LD21LD20

LD2

LD19LD18LD17LD16LD15LD14LD13LD12LD11LD10

LD1LD0

LCLK

LBE3LBE2LBE1LBE0

LA9LA8LA7LA6LA5LA4

LA31

LA3

LA29LA28LA27LA26LA25LA24LA23LA22LA21LA20

LA2

LA19LA18LA17LA16LA15LA14LA13LA12LA11LA10

IRDY

INTA

IDSEL

GNT

FRAME

EESKEEDOEEDIEECSEE1MC

DT/R

DP3DP2DP1DP0

DMAPF

DEVSEL

DEN

CLKSEL

CLK

C/BE3C/BE2C/BE1C/BE0

BTERMOBTERM

BREQOBREQ

BLASTADS

149

148147137

11150

153159158

160

139140141142

13814528

146

21169

155154

ADMODE

AD9AD8AD7AD6AD5AD4

AD31AD30

AD3

AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20

AD2

AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10

AD1AD0

PLX_HOLDAPROC_HOLD

PLX_DMAPF#

PLX_LSERR#

PLX_BREQPLX_BREQO

PCI_PLX_REQ#

PROC_READY#

PROC_A3PROC_A4PROC_A5PROC_A6PROC_A7PROC_A8PROC_A9PROC_A10PROC_A11PROC_A12PROC_A13PROC_A14PROC_A15PROC_A16PROC_A17PROC_A18PROC_A19PROC_A20PROC_A21PROC_A22PROC_A23PROC_A24PROC_A25PROC_A26PROC_A27PROC_A28PROC_A29PROC_A30

PROC_A2

PROC_A[31:2]

PROC_DT/R#

PROC_BE2#PROC_BE1#

PROC_W/R#

PROC_CLK3

PROC_BE3#

PROC_RESET#

PROC_BE0#

PROC_D0

PROC_D26

PROC_D[31:0]

PROC_D31PROC_D30PROC_D29PROC_D28PROC_D27

PROC_D25PROC_D24PROC_D23PROC_D22PROC_D21PROC_D20PROC_D19PROC_D18PROC_D17PROC_D16PROC_D15PROC_D14PROC_D13PROC_D12PROC_D11PROC_D10PROC_D9PROC_D8PROC_D7PROC_D6PROC_D5PROC_D4PROC_D3PROC_D2PROC_D1

PROC_ADS#PROC_BLAST#

PROC_DEN#

PCI_LOCK#PCI_C/BE0#PCI_C/BE1#

PCI_STOP#

PCI_AD18PCI_AD[31:0]

PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10PCI_AD11PCI_AD12PCI_AD13

PCI_AD15PCI_AD16PCI_AD17

PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28PCI_AD29PCI_AD30

PCI_AD14

PCI_C/BE3#

PCI_DEVSEL#

PU_RESET#

PCI_CLK4

PCI_PERR#PCI_SERR#

PCI_PARPCI_TRDY#PCI_IRDY#

PCI_C/BE2#

PCI_FRAME#

PCI_PLX_GNT#

PROC_XINT4#

PLX_USERI

VCC

VCC

VCC

202203204205206207

177178

2

179180181182185186187188189190

3

191192194195196197198199200201

45

110109108107106103

135

102

133132131130129128127126125122

101

121120119118117116115113112111

2

108

106

133

117

136 PROC_A31LA30

C20.1

VCC

C30.1

VCC

C40.1

VCC

C50.1

VCC

C60.1

VCC

C70.1

VCC

C80.1

VCC

PCI_AD31

Page 4: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 1b

BYPASS CAPACITORS FOR U15

C90.1

VCC

C100.1

VCC

C110.1

VCC

C120.1

VCC

R510K

R310K

10KR4

10KR1

10KR2

U15

PKG_TYPE=PLCC68\SKT

GND;1,35,50,51,53,54NC=47,48,49,55,56,57,67

666830

43

37

17

2016

19

VCC;18,52

PCI_BUS_ARBITER

12

14

221113

2423

21

1025

2615

41

643965382363344

326

7

8

928

27

5846

6340

59

335

31

29

456044614262

40

PLX_USERIPLX_USERO

PCI_SEC1_REQ#

PCI_PLX_GNT#

PCI_SEC3_GNT#

PCI_SEC1_GNT#PCI_SEC2_GNT#

PCI_IRDY#PCI_FRAME#

PCI_RST#

PCI_CLK5

PCI_C/BE3#

PCI_C/BE1#PCI_C/BE0#

PCI_AD15

PCI_AD31PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26PCI_AD25PCI_AD24PCI_AD23PCI_AD22PCI_AD21PCI_AD20PCI_AD19PCI_AD18PCI_AD17PCI_AD16

PCI_AD[31:0]

PCI_AD14PCI_AD13PCI_AD12PCI_AD11PCI_AD10PCI_AD9PCI_AD8PCI_AD7PCI_AD6PCI_AD5PCI_AD4PCI_AD3PCI_AD2PCI_AD1PCI_AD0

PCI_PAR

PCI_C/BE2#

PCI_CONN_GNT#

PCI_SEC3_REQ#PCI_CONN_REQ#

PCI_SEC2_REQ#

PCI_PLX_REQ#REQ1

AD9

AD12AD13AD14AD15AD16AD17AD18AD19AD20

AD23AD24

C/BE1C/BE2C/BE3

AD26

AD28

AD30AD29

AD31

REQ4

AD0AD1

AD10AD11

AD2

AD21AD22

AD25

AD27

AD3AD4AD5AD6AD7AD8

C/BE0CLK

FRAME

GNT0GNT1GNT2

IRDYPAR

PLX_PRI_REQPLX_PRI_GNT

REQ0

REQ2

RST

REQ3

GNT3GNT4

VCCQL8X12B-1PL68C

Page 5: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 2a

C140.1

C130.1

R302

22

22

R30122

R300

C30022

2

1

R303

22

22

R306

R304

22

22

R305

R307

22

PKG_TYPE=HC49SY1

XTAL14.318MHZ

21 21

0.1C16

FB1

1 2

U13

PKG_TYPE=SOIC-20DW

515

164

2

9

1012

20

11

3

19

1

1314

1718

678

AV9155A-23

0.1C15

U11

VCC;1,7,20GND;10,11,14,17PKG_TYPE=SOIC-20DW

CDC340

891213

15161819

4

3

2

65

CLK1.843MHZ

PROC_CLK1

PROC_CLK3

FREQ2FREQ1FREQ0

PROC_CLK2

PROC_CLK4

PROC_CLK5

CLK16MHZ

GND1GND2

VDD2VDD1

X2

1.843MHZ

REF2REF1

AGND

OEPD

SCLK20

SCLK22

X1

SCLK212XCPU1XCPU

16MHZ24MHZ12MHZ

A

2Y42Y32Y22Y12G

1Y41Y31Y21Y11G

P1P0

+

(MEMORY CONTROLLER)

(PCI9060)

(HX)

(JX)

VCCVCC

VCC

VCC

(MISC LOGIC)

VCC

BYPASS CAPACITORS FOR U11

Page 6: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 2b

U14

PKG_TYPE=DIP-8

MAX707CPA

2

4

78

56

1

3

R401

1K

1K

R400

CR1

RED550-1104

2

1

2

1P

11X

3_H

DR

13

2

PKG_TYPE=SMT_SW

SW2PUSHSW

413

2

550-1104RED

CR2

2

1

2

1

74AC86

U8131

2

74AC86

U8164

5

U81

74AC86

8910

U81

74AC86

111213

RST#VCCRST

PFOPFINC

MR

GND PCI_RST#

PU_RESET#

TOP VIEW

VCC

VCC

VCC

TOP VIEW

CR3

RED550-1104

2

11

2R405

1K

R4041.0K

R6008201.0K

R403

1.0KR402

550-1106RED

CR60

2

1

2

1

550-1106RED

CR61

2

11

2

550-1106RED

CR62

2

1

2

1

PROC_FAIL#

TOP VIEW

3.3V

+3.3VVPP+5V

VCC

VCCVPP

RIGHTANGLE

0.1C17

0.1C18

VCCVCC

BYPASS CAPACITORS FOR U14 AND U81

RIGHTANGLE

RIGHTANGLE

Page 7: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 3a

C190.1

C200.1

R406

1.0K

R1010K

U54

SOIC-8D

IRF7202

1

2

4

3

8765

22C301

2

1

TP1

TP2R4071.0K

VPP_EN#

VPP SWITCH

VCC

G

SDD

DD

S

NC

+

VPP

R308

22

0.1C22

U55

SOIC-8D

IRF7101

3

1

4

2

5

87

0.02

5

R94

9U53

SOIC-20DBNC=12

MAX767CAP

98

151410

2

318

16

19

17

13

117

54

20

1

6

L16.8U

H

21

22C302

2

1

TP3

C210.1

VR

2

1N58

172

1

VR

1

1N58

171

2

0.01C448

C240.1

C230.1

TP4

22

R309

220C449

2

1

VCC3VCC2VCC1

SYNC

SS

REF

ON

PGND

LX

GND5GND4GND3GND2GND1

FB

DL

DH

CS

BST

+3.3V Supply

G

D

S

S

DD

G

D

+

3.3V

VCC

+

Page 8: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 3b

0.1C25 C27

0.10.1C26

VCCVCCVCC

BYPASS CAPACITOR FOR U56 BYPASS CAPACITOR FOR U12

10K

R16

10K

R13

10K

R11

23

1

R15

10K

13

2R12

10K

10K

R14

SEC2DADDR5

SEC2DADDR8

SEC3DADDR8

SEC1DADDR8

SEC1DADDR5

SEC3DADDR5

SEC DRAM SIZE

SEC DRAM TYPE

VCC

VCC

1x3_HDRP3

1x3_HDRP2

R8072.7K

2.7KR803

2.7KR800 R801

2.7K 2.7KR802

2.7KR806R805

2.7K2.7KR804

PCI_LOCK#

PCI_DEVSEL#PCI_TRDY#PCI_IRDY#

PCI_FRAME#

PCI_STOP#PCI_SERR#PCI_PERR#

VCC

VCC

22

R31522

R314

R311

22

22

R312

22

R313

U12

VCC;1,7,20GND;10,11,14,17PKG_TYPE=SOIC-20DW

CDC340

891213

15161819

4

3

2

65

22

R310

PKG_TYPE=OSC_DIP14\SKT

U56

8

OSCILLATOR

F6233-33.00

33.000MHZ

PCI_CLK5

PCI_CLK1

PCI_CLK4

PCI_CLK3

PCI_CLK2A

2Y42Y32Y22Y12G

1Y41Y31Y21Y11G

P1P0

PCI_CLK6

OUT

VCC

Page 9: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 4a

PKG_TYPE=OSC_DIP14\SKT

U57

F6233-80.000

80.000MHZ

8

OSCILLATOR

8

22

R316 R327

22

R323

22 R324

22

22

R322

22

R319

10KR18

10KR17

22

R318

R320

22

22

R321

22

R325

22

R317

22

R326

R328

22

0

R946

GT-48001U3

VCC;20,24,42,58,67,90,93,123VCC;130,131,132,133,134,140,142VCC;146,152,158,166,173,181,188VCC;201,208GND;21,25,43,59,68,92,94,124GND;128,129,135,139,141,143,148GND;151,157,165,172,174,180,187GND;194,200,207PQFP208

91

164

126

138137

136

125

323334353637

67

38

89

1011121314151617

39

18192223262728293031

4041

49

64

73

80

87

66

75

82

89

65

74

81

88

61

70

77

84

60

69

76

83

63

72

79

86

62

71

78

85

99

101100

9695

98

97

106

113

120

108

115

122

107

114

121

103

110

117

102

109

116

105

112

119

104

111

118

127

44

45

4647

5051525354555657

48

183

185

189

145

150

186

190

182

144

149

179

184

147

163178191203

199202204205206

1

153154

2

155156159160161162167168169170

3

171175176177192193195196197198

45

OUT

SEC1_LEDCLK

SEC1_LEDSTBSEC1_LEDDATA#

SEC1_RSTQUEUE#

PCI_C/BE0#

SEC1_RXDLP0

SEC1_RXDLP2

SEC1_RXD1

SEC1_POL0

SEC1_POL1

SEC1_POL2

SEC1_POL3

SEC1_POL4

SEC1_POL5

SEC1_POL6

SEC1_POL7

SEC1_RXDLP3

SEC1_RXDLP4

SEC1_RXDLP5

SEC1_RXDLP6

SEC1_RXDLP7

SEC1_RXD0

SEC1_RXD3

SEC1_RXD5

SEC1_TXDDEL0

SEC1_TXDDEL1

SEC1_TXDDEL2

SEC1_TXD0

SEC1_TXD1

SEC1_TXD2

SEC1_TXD3

SEC1_TXD4

SEC1_TXD5

SEC1_TXD6

SEC1_TXD7

SEC1_TXEN0

SEC1_TXEN1

SEC1_TXEN2

SEC1_TXEN3

SEC1_TXEN4

SEC1_TXEN7

PROC_XINT1#

PCI_RST#

PCI_STOP#PCI_FRAME#

PCI_IRDY#PCI_TRDY#

PCI_C/BE1#PCI_C/BE2#PCI_C/BE3#

PCI_CLK1

PCI_DEVSEL#

PCI_PERR#PCI_SERR#

PCI_PAR

PCI_SEC1_GNT#

PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26PCI_AD25PCI_AD24PCI_AD23PCI_AD22PCI_AD21PCI_AD20PCI_AD19PCI_AD18PCI_AD17PCI_AD16PCI_AD15PCI_AD14

PCI_AD12PCI_AD11PCI_AD10PCI_AD9PCI_AD8PCI_AD7PCI_AD6PCI_AD5PCI_AD4PCI_AD3PCI_AD2PCI_AD1

PCI_AD13

PCI_AD31

PCI_AD0

PCI_AD[31:0]

SEC1DDATA[31:0]

SEC1DDATA31SEC1DDATA30SEC1DDATA29SEC1DDATA28SEC1DDATA27SEC1DDATA26SEC1DDATA25SEC1DDATA24SEC1DDATA23SEC1DDATA22SEC1DDATA21SEC1DDATA20SEC1DDATA19SEC1DDATA18SEC1DDATA17SEC1DDATA16SEC1DDATA15SEC1DDATA14SEC1DDATA13SEC1DDATA12SEC1DDATA11SEC1DDATA10SEC1DDATA9SEC1DDATA8SEC1DDATA7SEC1DDATA6SEC1DDATA5SEC1DDATA4SEC1DDATA3SEC1DDATA2SEC1DDATA1SEC1DDATA0

SEC1_TXEN6

SEC1_TXEN5

SEC1_RXDLP1

SEC1_ENDEV#

SEC1_TXDDEL7

SEC1_RXD7

SEC1_TXDDEL6

SEC1_RXD6

SEC1_TXDDEL5

SEC1_TXDDEL4

SEC1_RXD4

SEC1_TXDDEL3

SEC1_RXD2

PCI_SEC1_REQ#

SEC1CHIPSEL#

SEC1WE#

SEC1DADDR[8:0]

SEC1DADDR0

SEC1DADDR1

SEC1DADDR2

SEC1DADDR3

SEC1DADDR4

SEC1DADDR5

SEC1DADDR6

SEC1DADDR7

SEC1DADDR8

SEC1RAS1#

SEC1RAS0#

SEC1CAS#

TRDY

STOP

SERR

RSTQUEUE

RST

REQ

PERR

PAR

LEDSTBLEDDATA

LEDCLK

IRDY

INT

IDSEL

GNT

FRAME

ENDEV

DEVSEL

DDATA9DDATA8DDATA7DDATA6DDATA5DDATA4

DDATA31DDATA30

DDATA3

DDATA29DDATA28DDATA27DDATA26DDATA25DDATA24DDATA23DDATA22DDATA21DDATA20

DDATA2

DDATA19DDATA18DDATA17DDATA16DDATA15DDATA14DDATA13DDATA12DDATA11DDATA10

DDATA1DDATA0

CLK

RESVD

CAS

WE

TXEN7

TXEN6

TXEN5

TXEN4

TXEN3

TXEN2

TXEN1

TXEN0

TXDDEL7

TXDDEL6

TXDDEL5

TXDDEL4

TXDDEL3

TXDDEL2

TXDDEL1

TXDDEL0

TXD7

TXD6

TXD5

TXD4

TXD3

TXD2

TXD1

TXD0

SCLK

RXDLP7

RXDLP6

RXDLP5

RXDLP4

RXDLP3

RXDLP2

RXDLP1

RXDLP0

RXD7

RXD6

RXD5

RXD4

RXD3

RXD2

RXD1

RXD0

RAS1RAS0

POL7

POL6

POL5

POL4

POL3

POL2

POL1

POL0

DADDR8DADDR7DADDR6DADDR5DADDR4DADDR3DADDR2DADDR1DADDR0

CRS7

CRS6

CRS5

CRS4

CRS3

CRS2

CRS1

CRS0

CHIPSEL

C/BE3C/BE2C/BE1C/BE0

AD9AD8AD7AD6AD5AD4

AD31AD30

AD3

AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20

AD2

AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10

AD1AD0

VCC

Page 10: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 4b

C400.1

BYPASS CAPACITOR FOR U57

VCC

C390.10.1

C380.1C36 C37

0.1

BYPASS CAPACITORS FOR U21-U24

VCCVCCVCC VCC

0.1C32 C33

0.1 0.1C34

0.1C35

0.1C31

0.1C30C29

0.10.1C28

BYPASS CAPACITORS FOR U3

VCC VCC VCC VCCVCCVCCVCCVCC

10K

R19

R20

10K

10K

R21

1X3_

HD

R

23

1

1X3_

HD

R

13

2

1X3_

HD

R

23

1

1X3_

HD

R

23

1

R22

10K

P4

P5

P6

P8

P7

1X3_

HD

R

13

2

10K

R23

SEC1DADDR0

SEC1DADDR1

SEC1DADDR2

SEC1DADDR3

SEC1DADDR4

U3 DEVICE NUMBERVCC

SEC1RAS1#SEC1CAS#

SEC1WE#

SEC1DADDR8

SEC1DDATA31

SEC1DDATA16SEC1DDATA17SEC1DDATA18SEC1DDATA19

SEC1DDATA20SEC1DDATA21SEC1DDATA22SEC1DDATA23

SEC1DDATA24SEC1DDATA25SEC1DDATA26SEC1DDATA27

SEC1DDATA28SEC1DDATA29SEC1DDATA30

SEC1DADDR0SEC1DADDR1SEC1DADDR2SEC1DADDR3SEC1DADDR4SEC1DADDR5SEC1DADDR6SEC1DADDR7

SEC1RAS1# SEC1DDATA14

SEC1DDATA11

SEC1DDATA13SEC1DDATA12

SEC1DDATA10SEC1DDATA9SEC1DDATA8

SEC1DDATA7SEC1DDATA6SEC1DDATA5SEC1DDATA4

SEC1DDATA3SEC1DDATA2SEC1DDATA1SEC1DDATA0

SEC1DADDR0

SEC1WE#

SEC1CAS#

SEC1DDATA15

SEC1DADDR8SEC1DADDR7SEC1DADDR6SEC1DADDR5SEC1DADDR4SEC1DADDR3SEC1DADDR2SEC1DADDR1

SEC1DADDR7SEC1DADDR6SEC1DADDR5SEC1DADDR4SEC1DADDR3SEC1DADDR2SEC1DADDR1SEC1DADDR0

SEC1DDATA30SEC1DDATA29SEC1DDATA28

SEC1DDATA27SEC1DDATA26SEC1DDATA25SEC1DDATA24

SEC1DDATA23SEC1DDATA22SEC1DDATA21SEC1DDATA20

SEC1DDATA19SEC1DDATA18SEC1DDATA17SEC1DDATA16

SEC1DDATA31

SEC1RAS0#

SEC1DADDR8

SEC1WE#

SEC1CAS#

U22MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

U21MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

SEC1DADDR1SEC1DADDR2SEC1DADDR3SEC1DADDR4SEC1DADDR5SEC1DADDR6SEC1DADDR7SEC1DADDR8

SEC1DDATA15

SEC1CAS#

SEC1WE#

SEC1DADDR0

SEC1RAS0#

SEC1DDATA0SEC1DDATA1SEC1DDATA2SEC1DDATA3

SEC1DDATA4SEC1DDATA5SEC1DDATA6SEC1DDATA7

SEC1DDATA8SEC1DDATA9SEC1DDATA10

SEC1DDATA12SEC1DDATA13

SEC1DDATA11

SEC1DDATA14

U24MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

U23MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

Page 11: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 5a

PKG_TYPE=OSC_DIP14\SKT

U58

F6233-80.000

80.000MHZ

8

OSCILLATOR

8

22

R329 R340

22

R336

22 R337

22

22

R335

22

R332

10KR25

10KR24

22

R331

R333

22

22

R334

22

R338

22

R330

22

R339

R341

22

0

R947

GT-48001U4

VCC;20,24,42,58,67,90,93,123VCC;130,131,132,133,134,140,142VCC;146,152,158,166,173,181,188VCC;201,208GND;21,25,43,59,68,92,94,124GND;128,129,135,139,141,143,148GND;151,157,165,172,174,180,187GND;194,200,207PQFP208

91

164

126

138137

136

125

323334353637

67

38

89

1011121314151617

39

18192223262728293031

4041

49

64

73

80

87

66

75

82

89

65

74

81

88

61

70

77

84

60

69

76

83

63

72

79

86

62

71

78

85

99

101100

9695

98

97

106

113

120

108

115

122

107

114

121

103

110

117

102

109

116

105

112

119

104

111

118

127

44

45

4647

5051525354555657

48

183

185

189

145

150

186

190

182

144

149

179

184

147

163178191203

199202204205206

1

153154

2

155156159160161162167168169170

3

171175176177192193195196197198

45

OUT

SEC2_LEDCLK

SEC2_LEDSTBSEC2_LEDDATA#

SEC2_RSTQUEUE#

PCI_C/BE0#

SEC2_RXDLP0

SEC2_RXDLP2

SEC2_RXD1

SEC2_POL0

SEC2_POL1

SEC2_POL2

SEC2_POL3

SEC2_POL4

SEC2_POL5

SEC2_POL6

SEC2_POL7

SEC2_RXDLP3

SEC2_RXDLP4

SEC2_RXDLP5

SEC2_RXDLP6

SEC2_RXDLP7

SEC2_RXD0

SEC2_RXD3

SEC2_RXD5

SEC2_TXDDEL0

SEC2_TXDDEL1

SEC2_TXDDEL2

SEC2_TXD0

SEC2_TXD1

SEC2_TXD2

SEC2_TXD3

SEC2_TXD4

SEC2_TXD5

SEC2_TXD6

SEC2_TXD7

SEC2_TXEN0

SEC2_TXEN1

SEC2_TXEN2

SEC2_TXEN3

SEC2_TXEN4

SEC2_TXEN7

PROC_XINT2#

PCI_RST#

PCI_STOP#PCI_FRAME#

PCI_IRDY#PCI_TRDY#

PCI_C/BE1#PCI_C/BE2#PCI_C/BE3#

PCI_CLK2

PCI_DEVSEL#

PCI_PERR#PCI_SERR#

PCI_PAR

PCI_SEC2_GNT#

PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26PCI_AD25PCI_AD24PCI_AD23PCI_AD22PCI_AD21PCI_AD20PCI_AD19PCI_AD18PCI_AD17PCI_AD16PCI_AD15PCI_AD14

PCI_AD12PCI_AD11PCI_AD10PCI_AD9PCI_AD8PCI_AD7PCI_AD6PCI_AD5PCI_AD4PCI_AD3PCI_AD2PCI_AD1

PCI_AD13

PCI_AD31

PCI_AD0

PCI_AD[31:0]

SEC2DDATA[31:0]

SEC2DDATA31SEC2DDATA30SEC2DDATA29SEC2DDATA28SEC2DDATA27SEC2DDATA26SEC2DDATA25SEC2DDATA24SEC2DDATA23SEC2DDATA22SEC2DDATA21SEC2DDATA20SEC2DDATA19SEC2DDATA18SEC2DDATA17SEC2DDATA16SEC2DDATA15SEC2DDATA14SEC2DDATA13SEC2DDATA12SEC2DDATA11SEC2DDATA10SEC2DDATA9SEC2DDATA8SEC2DDATA7SEC2DDATA6SEC2DDATA5SEC2DDATA4SEC2DDATA3SEC2DDATA2SEC2DDATA1SEC2DDATA0

SEC2_TXEN6

SEC2_TXEN5

SEC2_RXDLP1

SEC2_ENDEV#

SEC2_TXDDEL7

SEC2_RXD7

SEC2_TXDDEL6

SEC2_RXD6

SEC2_TXDDEL5

SEC2_TXDDEL4

SEC2_RXD4

SEC2_TXDDEL3

SEC2_RXD2

PCI_SEC2_REQ#

SEC2CHIPSEL#

SEC2WE#

SEC2DADDR[8:0]

SEC2DADDR0

SEC2DADDR1

SEC2DADDR2

SEC2DADDR3

SEC2DADDR4

SEC2DADDR5

SEC2DADDR6

SEC2DADDR7

SEC2DADDR8

SEC2RAS1#

SEC2RAS0#

SEC2CAS#

TRDY

STOP

SERR

RSTQUEUE

RST

REQ

PERR

PAR

LEDSTBLEDDATA

LEDCLK

IRDY

INT

IDSEL

GNT

FRAME

ENDEV

DEVSEL

DDATA9DDATA8DDATA7DDATA6DDATA5DDATA4

DDATA31DDATA30

DDATA3

DDATA29DDATA28DDATA27DDATA26DDATA25DDATA24DDATA23DDATA22DDATA21DDATA20

DDATA2

DDATA19DDATA18DDATA17DDATA16DDATA15DDATA14DDATA13DDATA12DDATA11DDATA10

DDATA1DDATA0

CLK

RESVD

CAS

WE

TXEN7

TXEN6

TXEN5

TXEN4

TXEN3

TXEN2

TXEN1

TXEN0

TXDDEL7

TXDDEL6

TXDDEL5

TXDDEL4

TXDDEL3

TXDDEL2

TXDDEL1

TXDDEL0

TXD7

TXD6

TXD5

TXD4

TXD3

TXD2

TXD1

TXD0

SCLK

RXDLP7

RXDLP6

RXDLP5

RXDLP4

RXDLP3

RXDLP2

RXDLP1

RXDLP0

RXD7

RXD6

RXD5

RXD4

RXD3

RXD2

RXD1

RXD0

RAS1RAS0

POL7

POL6

POL5

POL4

POL3

POL2

POL1

POL0

DADDR8DADDR7DADDR6DADDR5DADDR4DADDR3DADDR2DADDR1DADDR0

CRS7

CRS6

CRS5

CRS4

CRS3

CRS2

CRS1

CRS0

CHIPSEL

C/BE3C/BE2C/BE1C/BE0

AD9AD8AD7AD6AD5AD4

AD31AD30

AD3

AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20

AD2

AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10

AD1AD0

VCC

Page 12: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 5b

C530.1

BYPASS CAPACITOR FOR U58

VCC

C520.10.1

C510.1C49 C50

0.1

BYPASS CAPACITORS FOR U25-U28

VCCVCCVCC VCC

0.1C45 C46

0.1 0.1C47

0.1C48

0.1C44

0.1C43C42

0.10.1C41

BYPASS CAPACITORS FOR U4

VCC VCC VCC VCCVCCVCCVCCVCC

10K

R26

R27

10K

10K

R28

1X3_

HD

R

23

1

1X3_

HD

R

13

2

1X3_

HD

R

23

1

1X3_

HD

R

23

1

R29

10K

P9

P10

P11

P13

P12

1X3_

HD

R

13

2

10K

R30

SEC2DADDR0

SEC2DADDR1

SEC2DADDR2

SEC2DADDR3

SEC2DADDR4

U4 DEVICE NUMBERVCC

SEC2DADDR7SEC2DADDR6SEC2DADDR5SEC2DADDR4SEC2DADDR3SEC2DADDR2SEC2DADDR1SEC2DADDR0

SEC2DDATA30SEC2DDATA29SEC2DDATA28

SEC2DDATA27SEC2DDATA26SEC2DDATA25SEC2DDATA24

SEC2DDATA23SEC2DDATA22SEC2DDATA21SEC2DDATA20

SEC2DDATA19SEC2DDATA18SEC2DDATA17SEC2DDATA16

SEC2DDATA31

SEC2RAS0#

SEC2DADDR8

SEC2WE#

SEC2CAS#

U26MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

U25MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

SEC2DADDR1SEC2DADDR2SEC2DADDR3SEC2DADDR4SEC2DADDR5SEC2DADDR6SEC2DADDR7SEC2DADDR8

SEC2DDATA15

SEC2CAS#

SEC2WE#

SEC2DADDR0

SEC2RAS0#

SEC2DDATA0SEC2DDATA1SEC2DDATA2SEC2DDATA3

SEC2DDATA4SEC2DDATA5SEC2DDATA6SEC2DDATA7

SEC2DDATA8SEC2DDATA9SEC2DDATA10

SEC2DDATA12SEC2DDATA13

SEC2DDATA11

SEC2DDATA14

U28MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

U27MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

SEC2DADDR7SEC2DADDR6SEC2DADDR5SEC2DADDR4SEC2DADDR3SEC2DADDR2SEC2DADDR1SEC2DADDR0

SEC2DDATA30SEC2DDATA29SEC2DDATA28

SEC2DDATA27SEC2DDATA26SEC2DDATA25SEC2DDATA24

SEC2DDATA23SEC2DDATA22SEC2DDATA21SEC2DDATA20

SEC2DDATA19SEC2DDATA18SEC2DDATA17SEC2DDATA16

SEC2DDATA31

SEC2RAS1#

SEC2DADDR8

SEC2WE#

SEC2CAS#

SEC2DADDR1SEC2DADDR2SEC2DADDR3SEC2DADDR4SEC2DADDR5SEC2DADDR6SEC2DADDR7SEC2DADDR8

SEC2DDATA15

SEC2CAS#

SEC2WE#

SEC2DADDR0

SEC2RAS1#

SEC2DDATA0SEC2DDATA1SEC2DDATA2SEC2DDATA3

SEC2DDATA4SEC2DDATA5SEC2DDATA6SEC2DDATA7

SEC2DDATA8SEC2DDATA9SEC2DDATA10

SEC2DDATA12SEC2DDATA13

SEC2DDATA11

SEC2DDATA14

Page 13: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 6a

PKG_TYPE=OSC_DIP14\SKT

U59

F6233-80.000

80.000MHZ

8

OSCILLATOR

8

22

R342 R353

22

R349

22 R350

22

22

R348

22

R345

10KR32

10KR31

22

R344

R346

22

22

R347

22

R351

22

R343

22

R352

R354

22

0

R948

GT-48001U5

VCC;20,24,42,58,67,90,93,123VCC;130,131,132,133,134,140,142VCC;146,152,158,166,173,181,188VCC;201,208GND;21,25,43,59,68,92,94,124GND;128,129,135,139,141,143,148GND;151,157,165,172,174,180,187GND;194,200,207PQFP208

91

164

126

138137

136

125

323334353637

67

38

89

1011121314151617

39

18192223262728293031

4041

49

64

73

80

87

66

75

82

89

65

74

81

88

61

70

77

84

60

69

76

83

63

72

79

86

62

71

78

85

99

101100

9695

98

97

106

113

120

108

115

122

107

114

121

103

110

117

102

109

116

105

112

119

104

111

118

127

44

45

4647

5051525354555657

48

183

185

189

145

150

186

190

182

144

149

179

184

147

163178191203

199202204205206

1

153154

2

155156159160161162167168169170

3

171175176177192193195196197198

45

OUT

SEC3_LEDCLK

SEC3_LEDSTBSEC3_LEDDATA#

SEC3_RSTQUEUE#

PCI_C/BE0#

SEC3_RXDLP0

SEC3_RXDLP2

SEC3_RXD1

SEC3_POL0

SEC3_POL1

SEC3_POL2

SEC3_POL3

SEC3_POL4

SEC3_POL5

SEC3_POL6

SEC3_POL7

SEC3_RXDLP3

SEC3_RXDLP4

SEC3_RXDLP5

SEC3_RXDLP6

SEC3_RXDLP7

SEC3_RXD0

SEC3_RXD3

SEC3_RXD5

SEC3_TXDDEL0

SEC3_TXDDEL1

SEC3_TXDDEL2

SEC3_TXD0

SEC3_TXD1

SEC3_TXD2

SEC3_TXD3

SEC3_TXD4

SEC3_TXD5

SEC3_TXD6

SEC3_TXD7

SEC3_TXEN0

SEC3_TXEN1

SEC3_TXEN2

SEC3_TXEN3

SEC3_TXEN4

SEC3_TXEN7

PROC_XINT3#

PCI_RST#

PCI_STOP#PCI_FRAME#

PCI_IRDY#PCI_TRDY#

PCI_C/BE1#PCI_C/BE2#PCI_C/BE3#

PCI_CLK3

PCI_DEVSEL#

PCI_PERR#PCI_SERR#

PCI_PAR

PCI_SEC3_GNT#

PCI_AD30PCI_AD29PCI_AD28PCI_AD27PCI_AD26PCI_AD25PCI_AD24PCI_AD23PCI_AD22PCI_AD21PCI_AD20PCI_AD19PCI_AD18PCI_AD17PCI_AD16PCI_AD15PCI_AD14

PCI_AD12PCI_AD11PCI_AD10PCI_AD9PCI_AD8PCI_AD7PCI_AD6PCI_AD5PCI_AD4PCI_AD3PCI_AD2PCI_AD1

PCI_AD13

PCI_AD31

PCI_AD0

PCI_AD[31:0]

SEC3DDATA[31:0]

SEC3DDATA31SEC3DDATA30SEC3DDATA29SEC3DDATA28SEC3DDATA27SEC3DDATA26SEC3DDATA25SEC3DDATA24SEC3DDATA23SEC3DDATA22SEC3DDATA21SEC3DDATA20SEC3DDATA19SEC3DDATA18SEC3DDATA17SEC3DDATA16SEC3DDATA15SEC3DDATA14SEC3DDATA13SEC3DDATA12SEC3DDATA11SEC3DDATA10SEC3DDATA9SEC3DDATA8SEC3DDATA7SEC3DDATA6SEC3DDATA5SEC3DDATA4SEC3DDATA3SEC3DDATA2SEC3DDATA1SEC3DDATA0

SEC3_TXEN6

SEC3_TXEN5

SEC3_RXDLP1

SEC3_ENDEV#

SEC3_TXDDEL7

SEC3_RXD7

SEC3_TXDDEL6

SEC3_RXD6

SEC3_TXDDEL5

SEC3_TXDDEL4

SEC3_RXD4

SEC3_TXDDEL3

SEC3_RXD2

PCI_SEC3_REQ#

SEC3CHIPSEL#

SEC3WE#

SEC3DADDR[8:0]

SEC3DADDR0

SEC3DADDR1

SEC3DADDR2

SEC3DADDR3

SEC3DADDR4

SEC3DADDR5

SEC3DADDR6

SEC3DADDR7

SEC3DADDR8

SEC3RAS1#

SEC3RAS0#

SEC3CAS#

TRDY

STOP

SERR

RSTQUEUE

RST

REQ

PERR

PAR

LEDSTBLEDDATA

LEDCLK

IRDY

INT

IDSEL

GNT

FRAME

ENDEV

DEVSEL

DDATA9DDATA8DDATA7DDATA6DDATA5DDATA4

DDATA31DDATA30

DDATA3

DDATA29DDATA28DDATA27DDATA26DDATA25DDATA24DDATA23DDATA22DDATA21DDATA20

DDATA2

DDATA19DDATA18DDATA17DDATA16DDATA15DDATA14DDATA13DDATA12DDATA11DDATA10

DDATA1DDATA0

CLK

RESVD

CAS

WE

TXEN7

TXEN6

TXEN5

TXEN4

TXEN3

TXEN2

TXEN1

TXEN0

TXDDEL7

TXDDEL6

TXDDEL5

TXDDEL4

TXDDEL3

TXDDEL2

TXDDEL1

TXDDEL0

TXD7

TXD6

TXD5

TXD4

TXD3

TXD2

TXD1

TXD0

SCLK

RXDLP7

RXDLP6

RXDLP5

RXDLP4

RXDLP3

RXDLP2

RXDLP1

RXDLP0

RXD7

RXD6

RXD5

RXD4

RXD3

RXD2

RXD1

RXD0

RAS1RAS0

POL7

POL6

POL5

POL4

POL3

POL2

POL1

POL0

DADDR8DADDR7DADDR6DADDR5DADDR4DADDR3DADDR2DADDR1DADDR0

CRS7

CRS6

CRS5

CRS4

CRS3

CRS2

CRS1

CRS0

CHIPSEL

C/BE3C/BE2C/BE1C/BE0

AD9AD8AD7AD6AD5AD4

AD31AD30

AD3

AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20

AD2

AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10

AD1AD0

VCC

Page 14: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 6b

C660.1

BYPASS CAPACITOR FOR U59

VCC

C650.10.1

C640.1C62 C63

0.1

BYPASS CAPACITORS FOR U29-U32

VCCVCCVCC VCC

0.1C58 C59

0.1 0.1C60

0.1C61

0.1C57

0.1C56C55

0.10.1C54

BYPASS CAPACITORS FOR U5

VCC VCC VCC VCCVCCVCCVCCVCC

10K

R33

R34

10K

10K

R35

1X3_

HD

R

23

1

1X3_

HD

R

13

2

1X3_

HD

R

23

1

1X3_

HD

R

23

1

R36

10K

P14

P15

P16

P18

P17

1X3_

HD

R

13

2

10K

R37

SEC3DADDR0

SEC3DADDR1

SEC3DADDR2

SEC3DADDR3

SEC3DADDR4

U5 DEVICE NUMBERVCC

SEC3DADDR7SEC3DADDR6SEC3DADDR5SEC3DADDR4SEC3DADDR3SEC3DADDR2SEC3DADDR1SEC3DADDR0

SEC3DDATA30SEC3DDATA29SEC3DDATA28

SEC3DDATA27SEC3DDATA26SEC3DDATA25SEC3DDATA24

SEC3DDATA23SEC3DDATA22SEC3DDATA21SEC3DDATA20

SEC3DDATA19SEC3DDATA18SEC3DDATA17SEC3DDATA16

SEC3DDATA31

SEC3RAS0#

SEC3DADDR8

SEC3WE#

SEC3CAS#

U30MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

U29MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

SEC3DADDR1SEC3DADDR2SEC3DADDR3SEC3DADDR4SEC3DADDR5SEC3DADDR6SEC3DADDR7SEC3DADDR8

SEC3DDATA15

SEC3CAS#

SEC3WE#

SEC3DADDR0

SEC3RAS0#

SEC3DDATA0SEC3DDATA1SEC3DDATA2SEC3DDATA3

SEC3DDATA4SEC3DDATA5SEC3DDATA6SEC3DDATA7

SEC3DDATA8SEC3DDATA9SEC3DDATA10

SEC3DDATA12SEC3DDATA13

SEC3DDATA11

SEC3DDATA14

U32MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

U31MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

U29MT4C16270DJ-6

1716

1819

27

25

14

22

2829

13

2324

26

2345

10

87

34333231

36373839

9

256KX32 EDO DRAM

D0D1D2D3

D7

D5D4

D11D10D9D8

D12D13D14

A1A0

A2A3

OE

A7

RAS

A4

CASHCASL

WE

D15

A5A6

A8

D6

NC=11,12,15,30GND;21,35,40VCC;1,6,20SOJ-40

SEC3DADDR1SEC3DADDR2SEC3DADDR3SEC3DADDR4SEC3DADDR5SEC3DADDR6SEC3DADDR7SEC3DADDR8

SEC3DDATA15

SEC3CAS#

SEC3WE#

SEC3DADDR0

SEC3RAS0#

SEC3DDATA0SEC3DDATA1SEC3DDATA2SEC3DDATA3

SEC3DDATA4SEC3DDATA5SEC3DDATA6SEC3DDATA7

SEC3DDATA8SEC3DDATA9SEC3DDATA10

SEC3DDATA12SEC3DDATA13

SEC3DDATA11

SEC3DDATA14

SEC3DADDR7SEC3DADDR6SEC3DADDR5SEC3DADDR4SEC3DADDR3SEC3DADDR2SEC3DADDR1SEC3DADDR0

SEC3DDATA30SEC3DDATA29SEC3DDATA28

SEC3DDATA27SEC3DDATA26SEC3DDATA25SEC3DDATA24

SEC3DDATA23SEC3DDATA22SEC3DDATA21SEC3DDATA20

SEC3DDATA19SEC3DDATA18SEC3DDATA17SEC3DDATA16

SEC3DDATA31

SEC3RAS1#

SEC3DADDR8

SEC3WE#

SEC3CAS#

SEC3DADDR1SEC3DADDR2SEC3DADDR3SEC3DADDR4SEC3DADDR5SEC3DADDR6SEC3DADDR7SEC3DADDR8

SEC3DDATA15

SEC3CAS#

SEC3WE#

SEC3DADDR0

SEC3RAS1#

SEC3DDATA0SEC3DDATA1SEC3DDATA2SEC3DDATA3

SEC3DDATA4SEC3DDATA5SEC3DDATA6SEC3DDATA7

SEC3DDATA8SEC3DDATA9SEC3DDATA10

SEC3DDATA12SEC3DDATA13

SEC3DDATA11

SEC3DDATA14

Page 15: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 7a

R468

1.0K

R467

1.0K

R492

1.0K

R489

1.0K

1.0K

R488

1.0K

R466

R465

1.0K

1.0K

R464

R463

1.0K

R485

1.0K

1.0K

R461

R444

1.0K

R443

1.0K

1.0K

R442

R441

1.0K

1.0K

R440

R439

1.0K

R419

1.0K

R420

1.0K

R417

1.0K

1.0K

R416

R415

1.0K

R413

1.0K

U16

LED_INTERFACE

VCC;18,52GND;1,35,50,53,54NC=5,12,23,24,31,36,39,42,44,46,57,59,60,66,68PLCC68\SKT

11

16

20

14

22

51

21

10

19

13

15

17

2526

63

27

32

38

45

55

62

67

6

29

34

41

48

58

64

3

8

30

37

43

49

61

65

4

9

28

33

40

47

56

2

7

63

R462

1.0K R438

1.0K R414

1.0K

R486

1.0K

CR4

2

1

2

1

P191X3_HDR

231

CR711

2

4

3

1

4

32

CR6

2

11

2

CR701

2

4

323

4

1

CR30

2

1

2

1CR31

2

11

2

CR7

2

1

2

1CR5

2

11

2

CR29

2

1

2

1CR28

2

11

2

CR681

2

4

3

1

4

32

CR691

2

4

323

4

1

P201X3_HDR

1 3

2

R41

10K

R40

10K

R38

10KR39

10K

R437

1.0K

R487

1.0K

1.0K

R490

1.0K

R418

R491

1.0K

TEST_STB

TEST_ENABLE

TEST_DATA

TEST_CLK

STATUS7

STATUS6

STATUS5

STATUS4

STATUS3

STATUS2

STATUS1

STATUS0

RESET_OUT

RESET_IN

RESET

RCV_DATA7

RCV_DATA6

RCV_DATA5

RCV_DATA4

RCV_DATA3

RCV_DATA2

RCV_DATA1

RCV_DATA0

LED_STB

LED_DATA

LED_CLK

COLLISION7

COLLISION6

COLLISION5

COLLISION4

COLLISION3

COLLISION2

COLLISION1

COLLISION0

CLK_OUT

CLK_IN

ACT_LED_SEL1ACT_LED_SEL0

ACTIVITY7

ACTIVITY6

ACTIVITY5

ACTIVITY4

ACTIVITY3

ACTIVITY2

ACTIVITY1

ACTIVITY0

PCI_RST#

SEC1_TSTLEDCLKSEC1_LEDCLK

SEC1_TSTLEDSTBSEC1_LEDSTB

SEC1_TSTLEDDATA#SEC1_LEDDATA#

SEC1_TESTENABLE

ACT_LED_SEL1

ACT_LED_SEL0

QL8x12B-XPL68C

VCC

TOP

BOTTOM

VCC

TOP

BOTTOM

VCCVCC

TOP

BOTTOM

VCC

TOP

BOTTOM

C690.1 0.1

C70C680.1

C670.1

VCC VCCVCCVCC

BYPASS CAPACITORS FOR U16

CR8_CTL

CR75_BOT_CTL

CR32_CTL

CR72_TOP_CTL

CR72_BOT_CTL

CR9_CTL

CR33_CTL

CR73_TOP_CTL

CR73_BOT_CTL

CR10_CTL

CR34_CTL

CR74_TOP_CTL

CR74_BOT_CTL

CR11_CTL

CR35_CTL

CR75_TOP_CTL

NOTE: CR4-CR11 AND CR28-CR35 ARE DIALIGHT 550-1304 TOP VIEW GREEN LEDS.

NOTE: CR68-CR75 ARE DIALIGHT 552-0922 RIGHT ANGLE GREEN LEDS.

Page 16: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 7b

CR731

2

4

323

4

1

CR8

2

1

2

1

CR721

2

4

3

1

4

32

CR32

2

11

2

CR33

2

1

2

1

CR9

2

11

2

CR11

2

1

2

1

CR35

2

11

2

CR34

2

1

2

1

CR741

2

4

323

4

1

CR10

2

11

2

CR751

2

4

3

1

4

32

TOP

BOTTOM

VCC

TOP

BOTTOM

VCC VCC

TOP

BOTTOM

VCC

TOP

BOTTOM

CR8_CTL

CR75_BOT_CTL

CR32_CTL

CR72_TOP_CTL

CR72_BOT_CTL

CR9_CTL

CR33_CTL

CR73_TOP_CTL

CR73_BOT_CTL

CR10_CTL

CR34_CTL

CR74_TOP_CTL

CR74_BOT_CTL

CR11_CTL

CR35_CTL

CR75_TOP_CTL

Page 17: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 8a

R476

1.0K

R475

1.0K

R500

1.0K

R497

1.0K

1.0K

R496

1.0K

R474

R473

1.0K

1.0K

R472

R471

1.0K

R493

1.0K

1.0K

R469

R452

1.0K

R451

1.0K

1.0K

R450

R449

1.0K

1.0K

R448

R447

1.0K

R427

1.0K

R428

1.0K

R425

1.0K

1.0K

R424

R423

1.0K

R421

1.0K

U17

LED_INTERFACE

VCC;18,52GND;1,35,50,53,54NC=5,12,23,24,31,36,39,42,44,46,57,59,60,66,68PLCC68\SKT

11

16

20

14

22

51

21

10

19

13

15

17

2526

63

27

32

38

45

55

62

67

6

29

34

41

48

58

64

3

8

30

37

43

49

61

65

4

9

28

33

40

47

56

2

7

63

R470

1.0K R446

1.0K R422

1.0K

R494

1.0K

CR12

2

1

2

1

CR791

2

4

3

1

4

32

CR14

2

11

2

CR781

2

4

323

4

1

CR38

2

1

2

1CR39

2

11

2

CR15

2

1

2

1CR13

2

11

2

CR37

2

1

2

1CR36

2

11

2

CR761

2

4

3

1

4

32

CR771

2

4

323

4

1

R45

10K

R44

10K

R42

10KR43

10K

R445

1.0K

R495

1.0K

1.0K

R498

1.0K

R426

R499

1.0K

TEST_STB

TEST_ENABLE

TEST_DATA

TEST_CLK

STATUS7

STATUS6

STATUS5

STATUS4

STATUS3

STATUS2

STATUS1

STATUS0

RESET_OUT

RESET_IN

RESET

RCV_DATA7

RCV_DATA6

RCV_DATA5

RCV_DATA4

RCV_DATA3

RCV_DATA2

RCV_DATA1

RCV_DATA0

LED_STB

LED_DATA

LED_CLK

COLLISION7

COLLISION6

COLLISION5

COLLISION4

COLLISION3

COLLISION2

COLLISION1

COLLISION0

CLK_OUT

CLK_IN

ACT_LED_SEL1ACT_LED_SEL0

ACTIVITY7

ACTIVITY6

ACTIVITY5

ACTIVITY4

ACTIVITY3

ACTIVITY2

ACTIVITY1

ACTIVITY0

PCI_RST#

SEC2_TSTLEDCLKSEC2_LEDCLK

SEC2_TSTLEDSTBSEC2_LEDSTB

SEC2_TSTLEDDATA#SEC2_LEDDATA#

SEC2_TESTENABLE

QL8x12B-XPL68C

TOP

BOTTOM

VCC

TOP

BOTTOM

VCCVCC

TOP

BOTTOM

VCC

TOP

BOTTOM

C730.1 0.1

C74C720.1

C710.1

VCC VCCVCCVCC

BYPASS CAPACITORS FOR U17

ACT_LED_SEL0ACT_LED_SEL1

CR16_CTL

CR83_BOT_CTL

CR40_CTL

CR80_TOP_CTL

CR80_BOT_CTL

CR17_CTL

CR41_CTL

CR81_TOP_CTL

CR81_BOT_CTL

CR18_CTL

CR42_CTL

CR82_TOP_CTL

CR82_BOT_CTL

CR19_CTL

CR43_CTL

CR83_TOP_CTL

NOTE: CR12-CR19 AND CR36-CR43 ARE DIALIGHT 550-1304 TOP VIEW GREEN LEDS.

NOTE: CR76-CR83 ARE DIALIGHT 552-0922 RIGHT ANGLE GREEN LEDS.

Page 18: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 8b

CR811

2

4

323

4

1

CR16

2

1

2

1

CR801

2

4

3

1

4

32

CR40

2

11

2

CR41

2

1

2

1

CR17

2

11

2

CR19

2

1

2

1

CR43

2

11

2

CR42

2

1

2

1

CR821

2

4

323

4

1

CR18

2

11

2

CR831

2

4

3

1

4

32

TOP

BOTTOM

VCC

TOP

BOTTOM

VCC VCC

TOP

BOTTOM

VCC

TOP

BOTTOM

CR16_CTL

CR83_BOT_CTL

CR40_CTL

CR80_TOP_CTL

CR80_BOT_CTL

CR17_CTL

CR41_CTL

CR81_TOP_CTL

CR81_BOT_CTL

CR18_CTL

CR42_CTL

CR82_TOP_CTL

CR82_BOT_CTL

CR19_CTL

CR43_CTL

CR83_TOP_CTL

Page 19: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 9a

R484

1.0K

R483

1.0K

R508

1.0K

R505

1.0K

1.0K

R504

1.0K

R482

R481

1.0K

1.0K

R480

R479

1.0K

R501

1.0K

1.0K

R477

R460

1.0K

R459

1.0K

1.0K

R458

R457

1.0K

1.0K

R456

R455

1.0K

R435

1.0K

R436

1.0K

R433

1.0K

1.0K

R432

R431

1.0K

R429

1.0K

U18

LED_INTERFACE

VCC;18,52GND;1,35,50,53,54NC=5,12,23,24,31,36,39,42,44,46,57,59,60,66,68PLCC68\SKT

11

16

20

14

22

51

21

10

19

13

15

17

2526

63

27

32

38

45

55

62

67

6

29

34

41

48

58

64

3

8

30

37

43

49

61

65

4

9

28

33

40

47

56

2

7

63

R478

1.0K R454

1.0K R430

1.0K

R502

1.0K

CR20

2

1

2

1

CR871

2

4

3

1

4

32

CR22

2

11

2

CR861

2

4

323

4

1

CR46

2

1

2

1CR47

2

11

2

CR23

2

1

2

1CR21

2

11

2

CR45

2

1

2

1CR44

2

11

2

CR841

2

4

3

1

4

32

CR851

2

4

323

4

1

R49

10K

R48

10K

R46

10KR47

10K

R453

1.0K

R503

1.0K

1.0K

R506

1.0K

R434

R507

1.0K

TEST_STB

TEST_ENABLE

TEST_DATA

TEST_CLK

STATUS7

STATUS6

STATUS5

STATUS4

STATUS3

STATUS2

STATUS1

STATUS0

RESET_OUT

RESET_IN

RESET

RCV_DATA7

RCV_DATA6

RCV_DATA5

RCV_DATA4

RCV_DATA3

RCV_DATA2

RCV_DATA1

RCV_DATA0

LED_STB

LED_DATA

LED_CLK

COLLISION7

COLLISION6

COLLISION5

COLLISION4

COLLISION3

COLLISION2

COLLISION1

COLLISION0

CLK_OUT

CLK_IN

ACT_LED_SEL1ACT_LED_SEL0

ACTIVITY7

ACTIVITY6

ACTIVITY5

ACTIVITY4

ACTIVITY3

ACTIVITY2

ACTIVITY1

ACTIVITY0

PCI_RST#

SEC3_TSTLEDCLKSEC3_LEDCLK

SEC3_TSTLEDSTBSEC3_LEDSTB

SEC3_TSTLEDDATA#SEC3_LEDDATA#

SEC3_TESTENABLE

QL8x12B-XPL68C

TOP

BOTTOM

VCC

TOP

BOTTOM

VCCVCC

TOP

BOTTOM

VCC

TOP

BOTTOM

C770.1 0.1

C78C760.1

C750.1

VCC VCCVCCVCC

BYPASS CAPACITORS FOR U18

ACT_LED_SEL0ACT_LED_SEL1

CR24_CTL

CR91_BOT_CTL

CR48_CTL

CR88_TOP_CTL

CR88_BOT_CTL

CR25_CTL

CR49_CTL

CR89_TOP_CTL

CR89_BOT_CTL

CR26_CTL

CR50_CTL

CR90_TOP_CTL

CR90_BOT_CTL

CR27_CTL

CR51_CTL

CR91_TOP_CTL

NOTE: CR20-CR27 AND CR44-CR51 ARE DIALIGHT 550-1304 TOP VIEW GREEN LEDS.

NOTE: CR84-CR91 ARE DIALIGHT 552-0922 RIGHT ANGLE GREEN LEDS.

Page 20: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 9b

CR891

2

4

323

4

1

CR24

2

1

2

1

CR881

2

4

3

1

4

32

CR48

2

11

2

CR49

2

1

2

1

CR25

2

11

2

CR27

2

1

2

1

CR51

2

11

2

CR50

2

1

2

1

CR901

2

4

323

4

1

CR26

2

11

2

CR911

2

4

3

1

4

32

TOP

BOTTOM

VCC

TOP

BOTTOM

VCC VCC

TOP

BOTTOM

VCC

TOP

BOTTOM

CR24_CTL

CR91_BOT_CTL

CR48_CTL

CR88_TOP_CTL

CR88_BOT_CTL

CR25_CTL

CR49_CTL

CR89_TOP_CTL

CR89_BOT_CTL

CR26_CTL

CR50_CTL

CR90_TOP_CTL

CR90_BOT_CTL

CR27_CTL

CR51_CTL

CR91_TOP_CTL

Page 21: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 10

U60

8

109

12

34

765

PALC16L8-25PC

U63

3

29

1

343128

30

IDT72225

646361595856555352504947464442413938

789

101112131415171920212223242526

33

3566

2

4

3627

5

37

15

U64

3

343128

VCC;16,32,43,48,54,60,65,68GND;6,18,40,45,51,57,62,67IDT72225LB25JPLCC68\SKT

IDT72225

646361595856555352504947464442413938

29

1

30

789

101112131415171920212223242526

33

3566

2

4

3627

5

37

10KR50

SEC1CHIPSEL#GATEDCS 19

1213

151617

11

18

20

14

O12REFRESH

IO15IO16

I8

IO17

I11VSSI9

RAS0RAS1

CHIPSELCAS

I7I6I5

IO18

VCC

IO14

SEC1DDATA[31:0]

SEC1_FIFO_RESET#

LD

WCLK

PAF

FFEF

OERS

REN

RXI

HF

WXI

PAE

FL

WEN

Q17Q16Q15Q14Q13Q12Q11Q10

Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0

RCLK

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

RXO

SEC1_FIFO_EF#SEC1_FIFO_FF#SEC1_FIFO_HF#

SLW_PROC_D[31:0]

SEC1DDATA14

SEC1DDATA31SEC1DDATA30SEC1DDATA29

SEC1DDATA18SEC1DDATA19

SEC1DDATA26SEC1DDATA27SEC1DDATA28

SEC1DDATA25SEC1DDATA24SEC1DDATA23SEC1DDATA22SEC1DDATA21SEC1DDATA20

SEC1DDATA17SEC1DDATA16

SEC1DDATA15

SEC1DDATA13SEC1DDATA12SEC1DDATA11SEC1DDATA10SEC1DDATA9SEC1DDATA8SEC1DDATA7SEC1DDATA6SEC1DDATA5SEC1DDATA4SEC1DDATA3SEC1DDATA2SEC1DDATA1SEC1DDATA0

LD

WCLK

PAF

FFEF

OERS

REN

RXI

HF

WXI

PAE

FL

WEN

Q17Q16Q15Q14Q13Q12Q11Q10

Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0

RCLK

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

RXO

SLW_PROC_D0

SLW_PROC_D2SLW_PROC_D1

SLW_PROC_D3SLW_PROC_D4SLW_PROC_D5SLW_PROC_D6SLW_PROC_D7SLW_PROC_D8

SLW_PROC_D17SLW_PROC_D18SLW_PROC_D19SLW_PROC_D20SLW_PROC_D21SLW_PROC_D22SLW_PROC_D23

SLW_PROC_D30SLW_PROC_D29SLW_PROC_D28SLW_PROC_D27SLW_PROC_D26SLW_PROC_D25SLW_PROC_D24

SLW_PROC_D16

SLW_PROC_D15SLW_PROC_D14SLW_PROC_D13SLW_PROC_D12SLW_PROC_D11SLW_PROC_D10SLW_PROC_D9

SLW_PROC_D31

SEC1_FIFO_OE#

SEC1_FIFO_RCLKSEC1CAS#

SEC1RAS0#SEC1RAS1#

0.1C83

0.1C79

0.1C80 C82

0.10.1C81

BYPASS CAPACITOR FOR U60

VCC

BYPASS CAPACITORS FOR U63 AND U64

VCC VCC VCCVCC

VCC

VCC

VCC

VCC;16,32,43,48,54,60,65,68GND;6,18,40,45,51,57,62,67IDT72225LB25JPLCC68\SKT

Page 22: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 11

U61

8

109

12

34

765

PALC16L8-25PC

U65

3

29

1

343128

30

IDT72225

646361595856555352504947464442413938

789

101112131415171920212223242526

33

3566

2

4

3627

5

37

15

U66

3

343128

VCC;16,32,43,48,54,60,65,68GND;6,18,40,45,51,57,62,67IDT72225LB25JPLCC68\SKT

IDT72225

646361595856555352504947464442413938

29

1

30

789

101112131415171920212223242526

33

3566

2

4

3627

5

37

10KR51

SEC2CHIPSEL#GATEDCS 19

1213

151617

11

18

20

14

O12REFRESH

IO15IO16

I8

IO17

I11VSSI9

RAS0RAS1

CHIPSELCAS

I7I6I5

IO18

VCC

IO14

SEC2DDATA[31:0]

SEC2_FIFO_RESET#

LD

WCLK

PAF

FFEF

OERS

REN

RXI

HF

WXI

PAE

FL

WEN

Q17Q16Q15Q14Q13Q12Q11Q10

Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0

RCLK

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

RXO

SEC2_FIFO_EF#SEC2_FIFO_FF#SEC2_FIFO_HF#

SLW_PROC_D[31:0]

SEC2DDATA14

SEC2DDATA31SEC2DDATA30SEC2DDATA29

SEC2DDATA18SEC2DDATA19

SEC2DDATA26SEC2DDATA27SEC2DDATA28

SEC2DDATA25SEC2DDATA24SEC2DDATA23SEC2DDATA22SEC2DDATA21SEC2DDATA20

SEC2DDATA17SEC2DDATA16

SEC2DDATA15

SEC2DDATA13SEC2DDATA12SEC2DDATA11SEC2DDATA10SEC2DDATA9SEC2DDATA8SEC2DDATA7SEC2DDATA6SEC2DDATA5SEC2DDATA4SEC2DDATA3SEC2DDATA2SEC2DDATA1SEC2DDATA0

LD

WCLK

PAF

FFEF

OERS

REN

RXI

HF

WXI

PAE

FL

WEN

Q17Q16Q15Q14Q13Q12Q11Q10

Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0

RCLK

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

RXO

SLW_PROC_D0

SLW_PROC_D2SLW_PROC_D1

SLW_PROC_D3SLW_PROC_D4SLW_PROC_D5SLW_PROC_D6SLW_PROC_D7SLW_PROC_D8

SLW_PROC_D17SLW_PROC_D18SLW_PROC_D19SLW_PROC_D20SLW_PROC_D21SLW_PROC_D22SLW_PROC_D23

SLW_PROC_D30SLW_PROC_D29SLW_PROC_D28SLW_PROC_D27SLW_PROC_D26SLW_PROC_D25SLW_PROC_D24

SLW_PROC_D16

SLW_PROC_D15SLW_PROC_D14SLW_PROC_D13SLW_PROC_D12SLW_PROC_D11SLW_PROC_D10SLW_PROC_D9

SLW_PROC_D31

SEC2_FIFO_OE#

SEC2_FIFO_RCLKSEC2CAS#

SEC2RAS0#SEC2RAS1#

0.1C84

0.1C85

0.1C86 C88

0.10.1C87

BYPASS CAPACITOR FOR U61

VCC

BYPASS CAPACITORS FOR U65 AND U66

VCC VCC VCCVCC

VCC

VCC

VCC

VCC;16,32,43,48,54,60,65,68GND;6,18,40,45,51,57,62,67IDT72225LB25JPLCC68\SKT

Page 23: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 12

U62

8

109

12

34

765

PALC16L8-25PC

U67

3

29

1

343128

30

IDT72225

646361595856555352504947464442413938

789

101112131415171920212223242526

33

3566

2

4

3627

5

37

15

U68

3

343128

VCC;16,32,43,48,54,60,65,68GND;6,18,40,45,51,57,62,67IDT72225LB25JPLCC68\SKT

IDT72225

646361595856555352504947464442413938

29

1

30

789

101112131415171920212223242526

33

3566

2

4

3627

5

37

10KR52

SEC3CHIPSEL#GATEDCS 19

1213

151617

11

18

20

14

O12REFRESH

IO15IO16

I8

IO17

I11VSSI9

RAS0RAS1

CHIPSELCAS

I7I6I5

IO18

VCC

IO14

SEC3DDATA[31:0]

SEC3_FIFO_RESET#

LD

WCLK

PAF

FFEF

OERS

REN

RXI

HF

WXI

PAE

FL

WEN

Q17Q16Q15Q14Q13Q12Q11Q10

Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0

RCLK

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

RXO

SEC3_FIFO_EF#SEC3_FIFO_FF#SEC3_FIFO_HF#

SLW_PROC_D[31:0]

SEC3DDATA14

SEC3DDATA31SEC3DDATA30SEC3DDATA29

SEC3DDATA18SEC3DDATA19

SEC3DDATA26SEC3DDATA27SEC3DDATA28

SEC3DDATA25SEC3DDATA24SEC3DDATA23SEC3DDATA22SEC3DDATA21SEC3DDATA20

SEC3DDATA17SEC3DDATA16

SEC3DDATA15

SEC3DDATA13SEC3DDATA12SEC3DDATA11SEC3DDATA10SEC3DDATA9SEC3DDATA8SEC3DDATA7SEC3DDATA6SEC3DDATA5SEC3DDATA4SEC3DDATA3SEC3DDATA2SEC3DDATA1SEC3DDATA0

LD

WCLK

PAF

FFEF

OERS

REN

RXI

HF

WXI

PAE

FL

WEN

Q17Q16Q15Q14Q13Q12Q11Q10

Q9Q8Q7Q6Q5Q4Q3Q2Q1Q0

RCLK

D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

RXO

SLW_PROC_D0

SLW_PROC_D2SLW_PROC_D1

SLW_PROC_D3SLW_PROC_D4SLW_PROC_D5SLW_PROC_D6SLW_PROC_D7SLW_PROC_D8

SLW_PROC_D17SLW_PROC_D18SLW_PROC_D19SLW_PROC_D20SLW_PROC_D21SLW_PROC_D22SLW_PROC_D23

SLW_PROC_D30SLW_PROC_D29SLW_PROC_D28SLW_PROC_D27SLW_PROC_D26SLW_PROC_D25SLW_PROC_D24

SLW_PROC_D16

SLW_PROC_D15SLW_PROC_D14SLW_PROC_D13SLW_PROC_D12SLW_PROC_D11SLW_PROC_D10SLW_PROC_D9

SLW_PROC_D31

SEC3_FIFO_OE#

SEC3_FIFO_RCLKSEC3CAS#

SEC3RAS0#SEC3RAS1#

0.1C89

0.1C90

0.1C91 C93

0.10.1C92

BYPASS CAPACITOR FOR U62

VCC

BYPASS CAPACITORS FOR U67 AND U68

VCC VCC VCCVCC

VCC

VCC

VCC

VCC;16,32,43,48,54,60,65,68GND;6,18,40,45,51,57,62,67IDT72225LB25JPLCC68\SKT

Page 24: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 13

C940.1

C950.1 0.1

C96

BYPASS CAPACITORS FOR U69, U82 and U83.

VCC VCCVCC

R105

10K

10K

R104

10K

R106SEC1_TXEN1

SEC1_TXDDEL1

SEC1_TXD1

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R101

10K

R103

10K

10K

R102SEC1_TXDDEL0

SEC1_TXEN0

SEC1_TXD0

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U69

LS32

67

522K

R750

820

R649

U69

LS32

21

3

R77

10K 820

R673

R625

820

R53

10K

5.1

R952

0.1C97

C450150PF

R602820

5.1

R953

U134FL1057

46

32

44

343129

3028

2725

42

36

40

38

1820

1719

2123

22

26

24

150PFC453

U111

45

6

7

8 1

2

3

PT3868

150PFC451

J1RJ45_1OF8

B7B6B5

B2

B4B3

B8

B1

J1RJ45_1OF8

A1

A8

A3A4

A2

A5A6A7

U110

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U82

U82

U82

U82

SOIC-14D

21

54

109

1312 11

3

6

8

U83

U83

U83

U83

74AC86SOIC-14D

21

54

109

1312 11

R951

5.1

R950

5.1

820R601

C452150PF

U106

74AC04

1 2

U106

74AC04

43

R54

10K

R626

820

820

R674R78

10K

U69

LS32

11910

820

R650

R698

820

22K

R751

U69

LS32

131514

R697

820

SEC1_POL0

SEC1_RXDLP0

SEC1_RXD0

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC1_TXD0

SEC1_TXEN0

SEC1_TXDDEL0

SEC1_TXD1

SEC1_TXEN1

SEC1_TXDDEL1

SEC1_RXD1

SEC1_RXDLP1

SEC1_POL1

VCC

+-

VCC

+-

+-

+-

Page 25: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 14

C980.1

C990.1 0.1

C100

BYPASS CAPACITORS FOR U70, U84 and U85.

VCC VCCVCC

R111

10K

10K

R110

10K

R112SEC1_TXEN3

SEC1_TXDDEL3

SEC1_TXD3

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R107

10K

R109

10K

10K

R108SEC1_TXDDEL2

SEC1_TXEN2

SEC1_TXD2

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U70

LS32

67

522K

R752

820

R651

U70

LS32

21

3

R79

10K 820

R675

R627

820

R55

10K

5.1

R956

0.1C101

C454150PF

R604820

5.1

R957

U134FL1057

62

48

60

501513

1412

119

58

52

56

54

2 4

1 3

5 7

6

10

8

150PFC457

U113

45

6

7

8 1

2

3

PT3868

150PFC455

J1

RJ45_1OF8

D7D6D5

D2

D4D3

D8

D1

J1RJ45_1OF8

C1

C8

C3C4

C2

C5C6C7

U112

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U84

U84

U84

U84

SOIC-14D

21

54

109

1312 11

3

6

8

U85

U85

U85

U85

74AC86SOIC-14D

21

54

109

1312 11

R955

5.1

R954

5.1

820R603

C456150PF

U106

74AC04

5 6

U106

74AC04

89

R56

10K

R628

820

820

R676R80

10K

U70

LS32

11910

820

R652

R700

820

22K

R753

U70

LS32

131514

R699

820

SEC1_POL2

SEC1_RXDLP2

SEC1_RXD2

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC1_TXD2

SEC1_TXEN2

SEC1_TXDDEL2

SEC1_TXD3

SEC1_TXEN3

SEC1_TXDDEL3

SEC1_RXD3

SEC1_RXDLP3

SEC1_POL3

VCC

+-

VCC

+-

+-

+-

Page 26: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 15

C1020.1

C1030.1 0.1

C104

BYPASS CAPACITORS FOR U71, U86 and U87.

VCC VCCVCC

R117

10K

10K

R116

10K

R118SEC1_TXEN5

SEC1_TXDDEL5

SEC1_TXD5

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R113

10K

R115

10K

10K

R114SEC1_TXDDEL4

SEC1_TXEN4

SEC1_TXD4

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U71

LS32

67

522K

R754

820

R653

U71

LS32

21

3

R81

10K 820

R677

R629

820

R57

10K

5.1

R960

0.1C105

C458150PF

R606820

5.1

R961

U135FL1057

46

32

44

343129

3028

2725

42

36

40

38

1820

1719

2123

22

26

24

150PFC461

U115

45

6

7

8 1

2

3

PT3868

150PFC459

J1

RJ45_1OF8

F7F6F5

F2

F4F3

F8

F1

J1RJ45_1OF8

E1

E8

E3E4

E2

E5E6E7

U114

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U86

U86

U86

U86

SOIC-14D

21

54

109

1312 11

3

6

8

U87

U87

U87

U87

74AC86SOIC-14D

21

54

109

1312 11

R959

5.1

R958

5.1

820R605

C460150PF

U106

74AC04

11 10

U106

74AC04

1213

R58

10K

R630

820

820

R678R82

10K

U71

LS32

11910

820

R654

R702

820

22K

R755

U71

LS32

131514

R701

820

SEC1_POL4

SEC1_RXDLP4

SEC1_RXD4

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC1_TXD4

SEC1_TXEN4

SEC1_TXDDEL4

SEC1_TXD5

SEC1_TXEN5

SEC1_TXDDEL5

SEC1_RXD5

SEC1_RXDLP5

SEC1_POL5

VCC

+-

VCC

+-

+-

+-

Page 27: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 16

C1060.1

C1070.1 0.1

C108

BYPASS CAPACITORS FOR U72, U88 and U89.

VCC VCCVCC

R123

10K

10K

R122

10K

R124SEC1_TXEN7

SEC1_TXDDEL7

SEC1_TXD7

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R119

10K

R121

10K

10K

R120SEC1_TXDDEL6

SEC1_TXEN6

SEC1_TXD6

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U72

LS32

67

522K

R756

820

R655

U72

LS32

21

3

R83

10K 820

R679

R631

820

R59

10K

5.1

R964

0.1C109

C462150PF

R608820

5.1

R965

U135FL1057

62

48

60

501513

1412

119

58

52

56

54

2 4

1 3

5 7

6

10

8

150PFC465

U117

45

6

7

8 1

2

3

PT3868

150PFC463

J1RJ45_1OF8

H7H6H5

H2

H4H3

H8

H1

J1RJ45_1OF8

G1

G8

G3G4

G2

G5G6G7

U116

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U88

U88

U88

U88

SOIC-14D

21

54

109

1312 11

3

6

8

U89

U89

U89

U89

74AC86SOIC-14D

21

54

109

1312 11

R963

5.1

R962

5.1

820R607

C464150PF

U107

74AC04

1 2

U107

74AC04

43

R60

10K

R632

820

820

R680R84

10K

U72

LS32

11910

820

R656

R704

820

22K

R757

U72

LS32

131514

R703

820

SEC1_POL6

SEC1_RXDLP6

SEC1_RXD6

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC1_TXD6

SEC1_TXEN6

SEC1_TXDDEL6

SEC1_TXD7

SEC1_TXEN7

SEC1_TXDDEL7

SEC1_RXD7

SEC1_RXDLP7

SEC1_POL7

VCC

+-

VCC

+-

+-

+-

Page 28: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 17

C1100.1

C1110.1 0.1

C112

BYPASS CAPACITORS FOR U73, U90 and U91.

VCC VCCVCC

R129

10K

10K

R128

10K

R130SEC2_TXEN1

SEC2_TXDDEL1

SEC2_TXD1

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R125

10K

R127

10K

10K

R126SEC2_TXDDEL0

SEC2_TXEN0

SEC2_TXD0

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U73

LS32

67

522K

R758

820

R657

U73

LS32

21

3

R85

10K 820

R681

R633

820

R61

10K

5.1

R968

0.1C113

C466150PF

R610820

5.1

R969

U136FL1057

46

32

44

343129

3028

2725

42

36

40

38

1820

1719

2123

22

26

24

150PFC469

U119

45

6

7

8 1

2

3

PT3868

150PFC467

J2

RJ45_1OF8

B7B6B5

B2

B4B3

B8

B1

J2RJ45_1OF8

A1

A8

A3A4

A2

A5A6A7

U118

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U90

U90

U90

U90

SOIC-14D

21

54

109

1312 11

3

6

8

U91

U91

U91

U91

74AC86SOIC-14D

21

54

109

1312 11

R967

5.1

R966

5.1

820R609

C468150PF

U107

74AC04

5 6

U107

74AC04

89

R62

10K

R634

820

820

R682R86

10K

U73

LS32

11910

820

R658

R706

820

22K

R759

U73

LS32

131514

R705

820

SEC2_POL0

SEC2_RXDLP0

SEC2_RXD0

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC2_TXD0

SEC2_TXEN0

SEC2_TXDDEL0

SEC2_TXD1

SEC2_TXEN1

SEC2_TXDDEL1

SEC2_RXD1

SEC2_RXDLP1

SEC2_POL1

VCC

+-

VCC

+-

+-

+-

Page 29: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 18

C1140.1

C1150.1 0.1

C116

BYPASS CAPACITORS FOR U74, U92 and U93.

VCC VCCVCC

R135

10K

10K

R134

10K

R136SEC2_TXEN3

SEC2_TXDDEL3

SEC2_TXD3

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R131

10K

R133

10K

10K

R132SEC2_TXDDEL2

SEC2_TXEN2

SEC2_TXD2

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U74

LS32

67

522K

R760

820

R659

U74

LS32

21

3

R87

10K 820

R683

R635

820

R63

10K

5.1

R972

0.1C117

C470150PF

R612820

5.1

R973

U136FL1057

62

48

60

501513

1412

119

58

52

56

54

2 4

1 3

5 7

6

10

8

150PFC473

U121

45

6

7

8 1

2

3

PT3868

150PFC471

J2

RJ45_1OF8

D7D6D5

D2

D4D3

D8

D1

J2RJ45_1OF8

C1

C8

C3C4

C2

C5C6C7

U120

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U92

U92

U92

U92

SOIC-14D

21

54

109

1312 11

3

6

8

U93

U93

U93

U93

74AC86SOIC-14D

21

54

109

1312 11

R971

5.1

R970

5.1

820R611

C472150PF

U107

74AC04

11 10

U107

74AC04

1213

R64

10K

R636

820

820

R684R88

10K

U74

LS32

11910

820

R660

R708

820

22K

R761

U74

LS32

131514

R707

820

SEC2_POL2

SEC2_RXDLP2

SEC2_RXD2

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC2_TXD2

SEC2_TXEN2

SEC2_TXDDEL2

SEC2_TXD3

SEC2_TXEN3

SEC2_TXDDEL3

SEC2_RXD3

SEC2_RXDLP3

SEC2_POL3

VCC

+-

VCC

+-

+-

+-

Page 30: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 19

C1180.1

C1190.1 0.1

C120

BYPASS CAPACITORS FOR U75, U94 and U95.

VCC VCCVCC

R141

10K

10K

R140

10K

R142SEC2_TXEN5

SEC2_TXDDEL5

SEC2_TXD5

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R137

10K

R139

10K

10K

R138SEC2_TXDDEL4

SEC2_TXEN4

SEC2_TXD4

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U75

LS32

67

522K

R762

820

R661

U75

LS32

21

3

R89

10K 820

R685

R637

820

R65

10K

5.1

R976

0.1C121

C474150PF

R614820

5.1

R977

U137FL1057

46

32

44

343129

3028

2725

42

36

40

38

1820

1719

2123

22

26

24

150PFC477

U123

45

6

7

8 1

2

3

PT3868

150PFC475

J2RJ45_1OF8

F7F6F5

F2

F4F3

F8

F1

J2RJ45_1OF8

E1

E8

E3E4

E2

E5E6E7

U122

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U94

U94

U94

U94

SOIC-14D

21

54

109

1312 11

3

6

8

U95

U95

U95

U95

74AC86SOIC-14D

21

54

109

1312 11

R975

5.1

R974

5.1

820R613

C476150PF

U108

74AC04

1 2

U108

74AC04

43

R66

10K

R638

820

820

R686R90

10K

U75

LS32

11910

820

R662

R710

820

22K

R763

U75

LS32

131514

R709

820

SEC2_POL4

SEC2_RXDLP4

SEC2_RXD4

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC2_TXD4

SEC2_TXEN4

SEC2_TXDDEL4

SEC2_TXD5

SEC2_TXEN5

SEC2_TXDDEL5

SEC2_RXD5

SEC2_RXDLP5

SEC2_POL5

VCC

+-

VCC

+-

+-

+-

Page 31: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 20

C1220.1

C1230.1 0.1

C124

BYPASS CAPACITORS FOR U76, U96 and U97.

VCC VCCVCC

R147

10K

10K

R146

10K

R148SEC2_TXEN7

SEC2_TXDDEL7

SEC2_TXD7

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R143

10K

R145

10K

10K

R144SEC2_TXDDEL6

SEC2_TXEN6

SEC2_TXD6

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U76

LS32

67

522K

R764

820

R663

U76

LS32

21

3

R91

10K 820

R687

R639

820

R67

10K

5.1

R980

0.1C125

C478150PF

R616820

5.1

R981

U137FL1057

62

48

60

501513

1412

119

58

52

56

54

2 4

1 3

5 7

6

10

8

150PFC481

U125

45

6

7

8 1

2

3

PT3868

150PFC479

J2

RJ45_1OF8

H7H6H5

H2

H4H3

H8

H1

J2RJ45_1OF8

G1

G8

G3G4

G2

G5G6G7

U124

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U96

U96

U96

U96

SOIC-14D

21

54

109

1312 11

3

6

8

U97

U97

U97

U97

74AC86SOIC-14D

21

54

109

1312 11

R979

5.1

R978

5.1

820R615

C480150PF

U108

74AC04

5 6

U108

74AC04

89

R68

10K

R640

820

820

R688R92

10K

U76

LS32

11910

820

R664

R712

820

22K

R765

U76

LS32

131514

R711

820

SEC2_POL6

SEC2_RXDLP6

SEC2_RXD6

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC2_TXD6

SEC2_TXEN6

SEC2_TXDDEL6

SEC2_TXD7

SEC2_TXEN7

SEC2_TXDDEL7

SEC2_RXD7

SEC2_RXDLP7

SEC2_POL7

VCC

+-

VCC

+-

+-

+-

Page 32: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 21

C1260.1

C1270.1 0.1

C128

BYPASS CAPACITORS FOR U77, U98 and U99.

VCC VCCVCC

R153

10K

10K

R152

10K

R154SEC3_TXEN1

SEC3_TXDDEL1

SEC3_TXD1

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R149

10K

R151

10K

10K

R150SEC3_TXDDEL0

SEC3_TXEN0

SEC3_TXD0

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U77

LS32

67

522K

R766

820

R665

U77

LS32

21

3

R93

10K 820

R689

R641

820

R69

10K

5.1

R984

0.1C129

C482150PF

R618820

5.1

R985

U138FL1057

46

32

44

343129

3028

2725

42

36

40

38

1820

1719

2123

22

26

24

150PFC485

U127

45

6

7

8 1

2

3

PT3868

150PFC483

J3RJ45_1OF8

B7B6B5

B2

B4B3

B8

B1

J3RJ45_1OF8

A1

A8

A3A4

A2

A5A6A7

U126

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U98

U98

U98

U98

SOIC-14D

21

54

109

1312 11

3

6

8

U99

U99

U99

U99

74AC86SOIC-14D

21

54

109

1312 11

R983

5.1

R982

5.1

820R617

C484150PF

U108

74AC04

11 10

U108

74AC04

1213

R70

10K

R642

820

820

R690R94

10K

U77

LS32

11910

820

R666

R714

820

22K

R767

U77

LS32

131514

R713

820

SEC3_POL0

SEC3_RXDLP0

SEC3_RXD0

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC3_TXD0

SEC3_TXEN0

SEC3_TXDDEL0

SEC3_TXD1

SEC3_TXEN1

SEC3_TXDDEL1

SEC3_RXD1

SEC3_RXDLP1

SEC3_POL1

VCC

+-

VCC

+-

+-

+-

Page 33: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 22

C1300.1

C1310.1 0.1

C132

BYPASS CAPACITORS FOR U78, U100 and U101.

VCC VCCVCC

R159

10K

10K

R158

10K

R160SEC3_TXEN3

SEC3_TXDDEL3

SEC3_TXD3

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R155

10K

R157

10K

10K

R156SEC3_TXDDEL2

SEC3_TXEN2

SEC3_TXD2

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U78

LS32

67

522K

R768

820

R667

U78

LS32

21

3

R95

10K 820

R691

R643

820

R71

10K

5.1

R988

0.1C133

C486150PF

R620820

5.1

R989

U138FL1057

62

48

60

501513

1412

119

58

52

56

54

2 4

1 3

5 7

6

10

8

150PFC489

U129

45

6

7

8 1

2

3

PT3868

150PFC487

J3RJ45_1OF8

D7D6D5

D2

D4D3

D8

D1

J3RJ45_1OF8

C1

C8

C3C4

C2

C5C6C7

U128

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U100

U100

U100

U100

SOIC-14D

21

54

109

1312 11

3

6

8

U101

U101

U101

U101

74AC86SOIC-14D

21

54

109

1312 11

R987

5.1

R986

5.1

820R619

C488150PF

U109

74AC04

1 2

U109

74AC04

43

R72

10K

R644

820

820

R692R96

10K

U78

LS32

11910

820

R668

R716

820

22K

R769

U78

LS3213

1514

R715

820

SEC3_POL2

SEC3_RXDLP2

SEC3_RXD2

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC3_TXD2

SEC3_TXEN2

SEC3_TXDDEL2

SEC3_TXD3

SEC3_TXEN3

SEC3_TXDDEL3

SEC3_RXD3

SEC3_RXDLP3

SEC3_POL3

VCC

+-

VCC

+-

+-

+-

Page 34: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 23

C1340.1

C1350.1 0.1

C136

BYPASS CAPACITORS FOR U79, U102 and U103.

VCC VCCVCC

R165

10K

10K

R164

10K

R166SEC3_TXEN5

SEC3_TXDDEL5

SEC3_TXD5

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R161

10K

R163

10K

10K

R162SEC3_TXDDEL4

SEC3_TXEN4

SEC3_TXD4

00=UTPSERIAL MODE

H/F DUPLEX

0=HALF DUPLEX

U79

LS32

67

522K

R770

820

R669

U79

LS32

21

3

R97

10K 820

R693

R645

820

R73

10K

5.1

R992

0.1C137

C490150PF

R622820

5.1

R993

U139FL1057

46

32

44

343129

3028

2725

42

36

40

38

1820

1719

2123

22

26

24

150PFC493

U131

45

6

7

8 1

2

3

PT3868

150PFC491

J3

RJ45_1OF8

F7F6F5

F2

F4F3

F8

F1

J3RJ45_1OF8

E1

E8

E3E4

E2

E5E6E7

U130

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U102

U102

U102

U102

SOIC-14D

21

54

109

1312 11

3

6

8

U103

U103

U103

U103

74AC86SOIC-14D

21

54

109

1312 11

R991

5.1

R990

5.1

820R621

C492150PF

U109

74AC04

5 6

U109

74AC04

89

R74

10K

R646

820

820

R694R98

10K

U79

LS32

11910

820

R670

R718

820

22K

R771

U79

LS32

131514

R717

820

SEC3_POL4

SEC3_RXDLP4

SEC3_RXD4

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC3_TXD4

SEC3_TXEN4

SEC3_TXDDEL4

SEC3_TXD5

SEC3_TXEN5

SEC3_TXDDEL5

SEC3_RXD5

SEC3_RXDLP5

SEC3_POL5

VCC

+-

VCC

+-

+-

+-

Page 35: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 24

C1380.1

C1390.1 0.1

C140

BYPASS CAPACITORS FOR U80, U104 and U105.

VCC VCCVCC

R171

10K

10K

R170

10K

R172SEC3_TXEN7

SEC3_TXDDEL7

SEC3_TXD7

0=HALF DUPLEX

H/F DUPLEX

SERIAL MODE00=UTP

R167

10K

R169

10K

10K

R168SEC3_TXDDEL6

SEC3_TXEN6

SEC3_TXD6

00=UTPSERIAL MODE

H/F DUPLEX0=HALF DUPLEX

U80

LS32

67

522K

R772

820

R671

U80

LS32

21

3

R99

10K 820

R695

R647

820

R75

10K

5.1

R996

0.1C141

C494150PF

R624820

5.1

R997

U139FL1057

62

48

60

501513

1412

119

58

52

56

54

2 4

1 3

5 7

6

10

8

150PFC497

U133

45

6

7

8 1

2

3

PT3868

150PFC495

J3

RJ45_1OF8

H7H6H5

H2

H4H3

H8

H1

J3RJ45_1OF8

G1

G8

G3G4

G2

G5G6G7

U132

45

6

7

8 1

2

3

PT3868

3

6

8

74AC86

U104

U104

U104

U104

SOIC-14D

21

54

109

1312 11

3

6

8

U105

U105

U105

U105

74AC86SOIC-14D

21

54

109

1312 11

R995

5.1

R994

5.1

820R623

C496150PF

U109

74AC04

11 10

U109

74AC04

1213

R76

10K

R648

820

820

R696R100

10K

U80

LS32

11910

820

R672

R720

820

22K

R773

U80

LS32

131514

R719

820

SEC3_POL6

SEC3_RXDLP6

SEC3_RXD6

AGND

NPX

NPY

RCVNX

RCVNY

RCVPX

RCVPY

RXNX

RXNY

RXPX

RXPY

TXDNX

TXDNY

TXDPX

TXDPY

TXPNX

TXPNY

TXPPX

TXPPY

XMITNX

XMITNY

XMITPX

XMITPY

CGND

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

NC3TXNEGNC2

RXNEG

NC1TXPOS

NC4

RXPOS

SEC3_TXD6

SEC3_TXEN6

SEC3_TXDDEL6

SEC3_TXD7

SEC3_TXEN7

SEC3_TXDDEL7

SEC3_RXD7

SEC3_RXDLP7

SEC3_POL7

VCC

+-

VCC

+-

+-

+-

Page 36: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 25a

C1460.1 0.1

C1470.1C148

C1450.1

C1440.10.1

C143C1420.1

0.1C149

VCC VCC VCC

VCCVCCVCCVCC

VCC

BYPASS CAPACITORS FOR U42-U48,U52

1.0KR410

R4081.0K

R4091.0K R411

1.0K 1.0KR412

CR52

2

1

550-1304

1

2

CR56

2

1

550-1304

1

2

CR55

2

1

550-1304

2

1CR54

2

1

550-1304

2

1CR53

2

1

550-1304

1

2

U45

SOIC-20DW

2 193 184 175 166 157 148 139 12

111

74ACT574

SOIC-20DW

U46

2 193 184 175 166 157 148 139 12

111

74ACT574

U47

SOIC-20DW

2 193 184 175 166 157 148 139 12

111

74ACT574

SOIC-20DW

U48

2 193 184 175 166 157 148 139 12

111

74ACT574

POS_PROC_RESET

SLW_PROC_D0SLW_PROC_D1SLW_PROC_D2SLW_PROC_D3SLW_PROC_D4SLW_PROC_D5SLW_PROC_D6SLW_PROC_D7

SLW_PROC_D31SLW_PROC_D30SLW_PROC_D29SLW_PROC_D28SLW_PROC_D27SLW_PROC_D26SLW_PROC_D25SLW_PROC_D24

SLW_PROC_D23SLW_PROC_D22SLW_PROC_D21SLW_PROC_D20SLW_PROC_D19SLW_PROC_D18SLW_PROC_D17SLW_PROC_D16

SLW_PROC_D[31:0]

SLW_PROC_D15SLW_PROC_D14SLW_PROC_D13SLW_PROC_D12SLW_PROC_D11SLW_PROC_D10SLW_PROC_D9SLW_PROC_D8

SEC1_ENDEV#SEC1_RSTQUEUE#

SEC1_FIFO_RESET#

SEC1_TSTLEDSTBSEC1_TSTLEDDATA#

SEC1_TESTENABLESEC1_TSTLEDCLK

SEC2_TSTLEDCLKSEC2_TESTENABLE

SEC2_TSTLEDDATA#SEC2_TSTLEDSTB

SEC2_FIFO_RESET#

SEC2_RSTQUEUE#SEC2_ENDEV#

SEC3_ENDEV#SEC3_RSTQUEUE#

SEC3_FIFO_RESET#

SEC3_TSTLEDSTBSEC3_TSTLEDDATA#

SEC3_TSTLEDCLK

IO_CLK

SEC3_TESTENABLE

1D 1Q2D 2Q3D 3Q4D 4Q5D 5Q6D 6Q7D 7Q8D 8Q

1D 1Q2D 2Q3D 3Q4D 4Q5D 5Q6D 6Q7D 7Q8D 8Q

1D 1Q2D 2Q3D 3Q4D 4Q5D 5Q6D 6Q7D 7Q8D 8Q

1D 1Q2D 2Q3D 3Q4D 4Q5D 5Q6D 6Q7D 7Q8D 8Q

USER LEDS FOR DEBUGGING

VCC

OE

OE

OE

OE

10KR181R183

10K 10KR184

R18210K

SOIC-8D

U52

1

93C46

23

56

87

4

CSCLKDI

VSSTEST2

VCCTEST1

DO

VCC

VCC

NOTE: CR52-CR56 ARE TOP VIEW GREEN LEDs.

EEPROM_DO

Page 37: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 25b

U42

SOIC-20DW

74ACT573

111

12 913 814 715 616 517 418 319 2

10KR173

10KR174

10KR176

10KR175

10KR179

10KR180

10KR178

10KR177

SOIC-20DW

U4374ACT573

111

12 913 814 715 616 517 418 319 2

SOIC-20DW

U4474ACT573

111

12 913 814 715 616 517 418 319 2

SOIC-16SPEC2

SW1SO_SWX8

AUGAT_GDH08S

98765432

16151413121110

1 161

98765432 15

1413121110

8Q 8D7Q 7D6Q 6D5Q 5D4Q 4D3Q 3D2Q 2D1Q 1D

SWAP_ROM#

FREQ1FREQ0

SLW_PROC_D6SLW_PROC_D5SLW_PROC_D4SLW_PROC_D3SLW_PROC_D2SLW_PROC_D1SLW_PROC_D0

SLW_PROC_D[31:0]

SLW_PROC_D8SLW_PROC_D9SLW_PROC_D10SLW_PROC_D11SLW_PROC_D12SLW_PROC_D13SLW_PROC_D14

SLW_PROC_D17SLW_PROC_D18SLW_PROC_D19SLW_PROC_D20SLW_PROC_D21SLW_PROC_D22SLW_PROC_D23

SLW_PROC_D16

SLW_PROC_D15

SLW_PROC_D7

PLX_DMAPF#

SEC3_FIFO_HF#SEC3_FIFO_EF#

SEC2_FIFO_EF#SEC2_FIFO_HF#SEC2_FIFO_FF#

SEC1_FIFO_HF#SEC1_FIFO_EF#

SEC3_FIFO_FF#

IO_OE#

FREQ2

8Q 8D7Q 7D6Q 6D5Q 5D4Q 4D3Q 3D2Q 2D1Q 1D

8Q 8D7Q 7D6Q 6D5Q 5D4Q 4D3Q 3D2Q 2D1Q 1D

SEC1_FIFO_FF#

LATCHOELE

VCC

VCC

VCC

LATCHOELE

LATCHOELE

EEPROM_DO

Page 38: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 26

0.1C153

0.1C152C151

0.10.1C150

BYPASS CAPACITORS FOR U34-U37.

VCCVCCVCCVCC

U34

NOTE: U34-U37 ARE 74ACT245 IN SOIC-20DW

12

5

3

11

14

16

18

6

19

4

2

13

15

17

789

1

U35

1

987

17

15

13

2

4

19

6

18

16

14

11

3

5

12

U36

12

5

3

11

14

16

18

6

19

4

2

13

15

17

789

1

U37

1

987

17

15

13

2

4

19

6

18

16

14

11

3

5

12

SLW_PROC_D[31:0]

SLW_PROC_D0

SLW_PROC_D1SLW_PROC_D2SLW_PROC_D3SLW_PROC_D4SLW_PROC_D5SLW_PROC_D6SLW_PROC_D7

SLW_PROC_D8

SLW_PROC_D9SLW_PROC_D10SLW_PROC_D11SLW_PROC_D12SLW_PROC_D13SLW_PROC_D14SLW_PROC_D15

SLW_PROC_D16

SLW_PROC_D17SLW_PROC_D18SLW_PROC_D19SLW_PROC_D20SLW_PROC_D21SLW_PROC_D22SLW_PROC_D23

SLW_PROC_D24

SLW_PROC_D25SLW_PROC_D26SLW_PROC_D27SLW_PROC_D28SLW_PROC_D29SLW_PROC_D30SLW_PROC_D31

PROC_D0

PROC_D1PROC_D2PROC_D3PROC_D4PROC_D5PROC_D6PROC_D7

PROC_D8

PROC_D9PROC_D10PROC_D11PROC_D12PROC_D13PROC_D14PROC_D15

PROC_D16

PROC_D17PROC_D18PROC_D19PROC_D20PROC_D21PROC_D22PROC_D23

PROC_D24

PROC_D25PROC_D26PROC_D27PROC_D28PROC_D29PROC_D30PROC_D31

PROC_D[31:0]

SLW_BUS_EN#SLW_BUS_DIR

EN2[AB]EN1[BA]G

EN2[AB]EN1[BA]G

EN2[AB]EN1[BA]G

2

2

2

2

EN2[AB]EN1[BA]G

Page 39: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 27a

U33

VCC;32GND;16AM27C010-150DIP32\SKT

23

1

23

29

425

1314151718192021

121110

98765

2726

28

3031

2422

AM27C010

PROC_A18

PROC_BE0#PROC_BE1#

SLW_PROC_D7

SLW_PROC_D0

SLW_PROC_D6SLW_PROC_D5SLW_PROC_D4SLW_PROC_D3SLW_PROC_D2SLW_PROC_D1

EPROM_CS#

PROC_A16PROC_A15PROC_A14PROC_A13PROC_A12PROC_A11PROC_A10PROC_A9PROC_A8PROC_A7PROC_A6PROC_A5PROC_A4PROC_A3PROC_A2

PROC_RD#

PROC_A17

A10

VPP

A16A15A14

A12A11

D0D1D2D3D4D5D6D7

A0A1A2A3A4A5A6A7A8A9

A13

NCPGM

OECE

BYPASS CAPACITORS FOR U33.

0.1C154

VCC

BYPASS CAPACITOR FOR U49.

C1550.1

VCC

U49

GND;35VCC;10

2

40

3411

41

23

9

678

542

443

344

1

3729

16

30

15

33

12

31

14

32

13

26

20

27

19

24

22

25

21

3839

AM85C30

PLCC44AM85C30-8JC

NC=17,18,28,36

R186

10K

R185

10K

R187

10K

10K

R188

TXDB

TXDA

TRXCB

TRXCA

SYNCB

SYNCA

RXDB

RXDA

RTXCB

RTXCA

RTSB

RTSA

DTR/REQB

DTR/REQA

DCDB

DCDA

CTSB

CTSA

D1

WR

W/REQBW/REQA

RD

PCLK

INTACK

INTIEOIEI

D7D6D5D4D3D2

D0

D/C#CEA/B#

DUART_CLK

PROC_XINT5#

DUART_CS#

DUART_WR#

SLW_PROC_D1SLW_PROC_D2SLW_PROC_D3SLW_PROC_D4SLW_PROC_D5SLW_PROC_D6

SLW_PROC_D0

DUART_RD#

PROC_BE1#

PROC_BE0#

CLK1.843MHZ

SLW_PROC_D7

VCC

U50_3

U50_1U50_20

U50_2

U51_3

U51_1U51_20

U51_2

Page 40: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 27b

AMP_555165-1

MOD_JACKJ5

1

3456

21

3456

2

AMP_555165-1

MOD_JACKJ4

1

3456

22

6543

1

U50

DIP-20

MAX233CPP

14

17

12

7

5

19

1

2

18

20

3 4

96

15

11

10

16

8

13

U51

DIP-20

MAX233CPP

14

17

12

7

5

19

1

2

18

20

3 4

96

15

11

10

16

8

13

CH2_RTS

CH1_RTS

CH1_TXD

CH1_CTS

CH2_CTS

CH2_TXD

CH1_RXD

CH2_RXD

VCC

VCC

BYPASS CAPACITORS FOR U50 AND U51.

0.1C156

0.1C157

VCC VCC

GND

C2-

C2-

C2+

C2+

C1-

V-

V-

C1+

VCC

T1IN T1OUT

T2OUTT2IN

R1OUT R1IN

R2OUT R2IN

V+

GND

GND

C2-

C2-

C2+

C2+

C1-

V-

V-

C1+

VCC

T1IN T1OUT

T2OUTT2IN

R1OUT R1IN

R2OUT R2IN

V+

GND

U50_1

U50_3

U50_20

U50_2

U51_1

U51_3

U51_20

U51_2

Page 41: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 28a

U628F400CV

E28F400CV-T80TSOP48

32304442

43

393634

2931

3533

3840

41

45

13

46

1112

28

27

26

47

8181920

2223

23

56

2425

1

4

7

14

48

21

37

1716

NC=9,10,15

U728F400CV

E28F400CV-T80TSOP48

32304442

43

393634

2931

3533

3840

41

45

13

46

1112

28

27

26

47

8181920

2223

23

56

2425

1

4

7

14

48

21

37

1716

NC=9,10,15

C1580.1

P211X3_HDR

1 3

2

VPP

GND2

WERP

OE

GND1

DQ9DQ8DQ7DQ6

DQ14

DQ12DQ11DQ10

DQ0

CE

BYTE

A8A7A6A5

A3A2

A14A13

A11A10

A1A0

A15

A12

A9

WP

A16

A4

DQ1

DQ3DQ2

DQ4

VCC

DQ5

DQ13

DQ15

A17NC

VPP

GND2

WERP

OE

GND1

DQ9DQ8DQ7DQ6

DQ14

DQ12DQ11DQ10

DQ0

CE

BYTE

A8A7A6A5

A3A2

A14A13

A11A10

A1A0

A15

A12

A9

WP

A16

A4

DQ1

DQ3DQ2

DQ4

VCC

DQ5

DQ13

DQ15

A17NC

FLASH_WR#

PROC_RD#FLASH_BANK1_CS#

PROC_D13

PROC_D15

PROC_D[31:0]

PROC_D31PROC_D30PROC_D29PROC_D28PROC_D27PROC_D26PROC_D25PROC_D24PROC_D23PROC_D22PROC_D21PROC_D20PROC_D19PROC_D18PROC_D17PROC_D16

PROC_D14

PROC_D12PROC_D11PROC_D10PROC_D9PROC_D8PROC_D7PROC_D6PROC_D5PROC_D4PROC_D3PROC_D2PROC_D1PROC_D0

PROC_A20PROC_A19

PROC_A2PROC_A3PROC_A4PROC_A5PROC_A6PROC_A7PROC_A8PROC_A9PROC_A10PROC_A11PROC_A12PROC_A13PROC_A14PROC_A15PROC_A16PROC_A17PROC_A18

PROC_A[31:2]

PROC_A2PROC_A3PROC_A4PROC_A5PROC_A6PROC_A7PROC_A8PROC_A9PROC_A10PROC_A11PROC_A12PROC_A13PROC_A14PROC_A15PROC_A16PROC_A17PROC_A18PROC_A19PROC_A20

PROC_RESET#

DISABLEENABLE

PROGRAMMING ENABLE

VCC

VCC

BOOT BLOCK

VCC

VPP

VPP

C1610.1 0.1

C162C1600.1

C1590.1

VCC VCCVCCVCC

BYPASS CAPACITORS FOR U6 AND U7.

Page 42: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 28b

U9

4627

28F400CV

E28F400CV-T80TSOP48

32304442

43

393634

2931

3533

3840

41

45

13

1112

2826

47

8181920

2223

23

56

2425

1

4

7

14

48

21

37

1716

NC=9,10,15

U828F400CV

E28F400CV-T80TSOP48

32304442

43

393634

2931

3533

3840

41

45

NC=9,10,15

13

1112

2826

47

8181920

2223

23

56

2425

1

4

7

14

48

21

37

1716

2746

VPP

GND2

WERP

OE

GND1

DQ9DQ8DQ7DQ6

DQ14

DQ12DQ11DQ10

DQ0

CE

BYTE

A8A7A6A5

A3A2

A14A13

A11A10

A1A0

A15

A12

A9

WP

A16

A4

DQ1

DQ3DQ2

DQ4

VCC

DQ5

DQ13

DQ15

A17NC

VPP

GND2

WERP

OE

GND1

DQ9DQ8DQ7DQ6

DQ14

DQ12DQ11DQ10

DQ0

CE

BYTE

A8A7A6A5

A3A2

A14A13

A11A10

A1A0

A15

A12

A9

WP

A16

A4

DQ1

DQ3DQ2

DQ4

VCC

DQ5

DQ13

DQ15

A17NC

FLASH_WR#

PROC_RD#FLASH_BANK2_CS#

PROC_D0PROC_D1PROC_D2PROC_D3PROC_D4PROC_D5PROC_D6PROC_D7PROC_D8PROC_D9PROC_D10PROC_D11PROC_D12PROC_D13PROC_D14PROC_D15

PROC_D16PROC_D17PROC_D18PROC_D19PROC_D20PROC_D21PROC_D22PROC_D23PROC_D24PROC_D25PROC_D26PROC_D27PROC_D28PROC_D29PROC_D30PROC_D31

PROC_D[31:0]

PROC_A19

PROC_A20

PROC_A[31:2]

PROC_A2PROC_A3PROC_A4PROC_A5PROC_A6PROC_A7PROC_A8PROC_A9PROC_A10PROC_A11PROC_A12PROC_A13PROC_A14PROC_A15PROC_A16PROC_A17PROC_A18

PROC_A2PROC_A3PROC_A4PROC_A5PROC_A6PROC_A7PROC_A8PROC_A9PROC_A10PROC_A11PROC_A12PROC_A13PROC_A14PROC_A15PROC_A16PROC_A17PROC_A18PROC_A19

PROC_A20

PROC_RESET#

VCC

VCCVPP

VPP

0.1C163 C164

0.1 0.1C166C165

0.1

VPPVPPVPPVPP

BYPASS CAPACITORS FOR U8 AND U9.

Page 43: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 29a

U20

VCC;4,25,46,67GND;19,40,61,82PKG_TYPE=PLCC84\SKT

MISC_LOGIC

1312

74

73

62

60

55

54

44

3231

14

30

15

2616

18

2728

23

414243

68

1765

66

64

2429

20

22

63

59585756

21

373839797877

653

184838180727170

75

691133341035

367

2

98

76

454748505253

4951

22

R356

22

R357

R355

22

R8082.7K

P221X3_HDR

1 3

2

W_R#

SWAP_ROM

SLW_BUS_ENSLW_BUS_DIR

RESET

FLASH_WR

PROC_READY

PROC_RD

PROC_HOLDAPROC_BOFFPLX_HOLDA

PLX_HOLD

PLX_BREQO

JXPROC_ONCE

IO_OEIO_CLK

HXPROC_ONCE

FLASH2_CSFLASH1_CS

FIFO3_RCLK

FIFO3_OE

FIFO2_RCLK

FIFO2_OE

FIFO1_RCLK

FIFO1_OE

EPROM_CS

DUART_WRDUART_RDDUART_CS

DATA7DATA6DATA5DATA4DATA3DATA2

DATA0

CLK

BUS_ERR_INT

BLAST

BE3BE2BE1BE0

ADS ADLATCH_OE

ADDR9ADDR8ADDR7ADDR6ADDR5ADDR4

ADDR31ADDR30ADDR29

ADDR27ADDR26ADDR25ADDR24ADDR23ADDR22ADDR21ADDR20

ADDR2

ADDR19ADDR18ADDR17ADDR16ADDR15ADDR14

ADDR11ADDR10

ADDR28

ADDR13ADDR12

ADDR3

DATA1

DUART_WR#DUART_RD#

PROC_HOLDAPROC_HOLD

SEC1_FIFO_RCLK

PROC_W/R#

SLW_PROC_D6

PLX_BREQO

SLW_BUS_EN#

POS_PROC_RESET

FLASH_WR#

PROC_READY#

PROC_RD#

JXPROC_ONCE#

SEC3_FIFO_OE#SEC2_FIFO_OE#SEC1_FIFO_OE#

PROC_CLK5

PROC_BLAST#

PROC_BE3#PROC_BE2#PROC_BE1#PROC_BE0#

PROC_A31PROC_A30PROC_A29PROC_A28PROC_A27PROC_A26PROC_A25PROC_A24PROC_A23PROC_A22PROC_A21PROC_A20PROC_A19PROC_A18PROC_A17PROC_A16PROC_A15PROC_A14PROC_A13PROC_A12PROC_A11PROC_A10PROC_A9PROC_A8PROC_A7PROC_A6PROC_A5PROC_A4PROC_A3PROC_A2

PROC_A[31:2]

SLW_BUS_DIR

HXPROC_ONCE#

EPROM_CS#SWAP_ROM#

ADLATCH_OE#

PROC_BOFF#

SLW_PROC_D5SLW_PROC_D4SLW_PROC_D3SLW_PROC_D2SLW_PROC_D1SLW_PROC_D0

SLW_PROC_D7

PROC_ADS#

FLASH_BANK1_CS#FLASH_BANK2_CS#

SEC3_FIFO_RCLK

SEC2_FIFO_RCLK

IO_CLKIO_OE#

PLX_HOLDA

PROC_XINT6#

DUART_CS#

QL12X16B-1PL84C

VCC

CX/HXJX

C1690.1 0.1

C170C1680.1

C1670.1

VCC VCCVCCVCC

BYPASS CAPACITORS FOR U20.

2.7KR811R810

2.7KR8092.7K

PROC_READY#

PROC_ADS#PROC_BLAST#

VCC

Page 44: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 29b

R360

22

U19

VCC;4,25,46,67GND;19,40,61,82GND;22,23,63PLCC84\SKTQL8X12B-2PL84C

4139383736353433

32

9

65

10

79

87

328180

72707169

52535150

73

20

62

42

31

DRAM_CONTROLLER 22

R358

22

R359

22

R377

22

R361

22

R363

22

R366

22

R367

22

R369

R375

22

22

R374

22

R376

22

R37322

R372

R371

22

R370

22

22

R368

R362

22

22

R364

22

R365

PROC_DRAM_ADDR7

PROC_DRAM_ADDR0

PROC_DRAM_ADDR9

PROC_DRAM_ADDR10

PROC_DRAM_ADDR8

PROC_DRAM_ADDR6

PROC_DRAM_ADDR5

PROC_DRAM_ADDR4

PROC_DRAM_ADDR3

PROC_DRAM_ADDR2

PROC_DRAM_ADDR1

PROC_DRAM_ADDR[10:0]

ADDR10ADDR11

ADDR21

ADDR7ADDR8

ADDR12ADDR13ADDR14ADDR15ADDR16ADDR17ADDR18ADDR19

ADDR2

ADDR20

ADDR22ADDR23ADDR24ADDR25ADDR26ADDR27ADDR28ADDR29

ADDR3

ADDR30ADDR31

ADDR4ADDR5ADDR6

ADDR9

ADS

BE0BE1BE2BE3

BLAST

CLK

DATA0DATA1DATA2DATA3DATA4DATA5DATA6DATA7

PU_RESET

REF_CLK

DRAM_ADDR1

DRAM_ADDR4DRAM_ADDR5

DRAM_ADDR0

DRAM_ADDR10

DRAM_ADDR2DRAM_ADDR3

DRAM_ADDR6DRAM_ADDR7DRAM_ADDR8DRAM_ADDR9

DRAM_CAS0DRAM_CAS1DRAM_CAS2DRAM_CAS3

DRAM_RAS0DRAM_RAS1DRAM_RAS2DRAM_RAS3

DRAM_WE

DUART_CLK

POS_WD_RST

PROC_READY

VPP_EN

WD_RESET

W_R#

PROC_DRAM_RAS3#

PROC_DRAM_CAS0#PROC_DRAM_CAS1#PROC_DRAM_CAS2#PROC_DRAM_CAS3#

VPP_EN#

PROC_RESET#SLW_PROC_D7

CLK16MHZ

PROC_A2PROC_A3PROC_A4PROC_A5PROC_A6PROC_A7PROC_A8PROC_A9PROC_A10PROC_A11PROC_A12PROC_A13PROC_A14PROC_A15PROC_A16

PROC_A31PROC_A30PROC_A29PROC_A28PROC_A27PROC_A26PROC_A25PROC_A24PROC_A23PROC_A22PROC_A21PROC_A20PROC_A19PROC_A18PROC_A17PROC_A[31:2]

PROC_ADS#

PROC_BE0#PROC_BE1#PROC_BE2#PROC_BE3#

PROC_BLAST#

PROC_CLK4

PROC_W/R#

PU_RESET#

SLW_PROC_D4SLW_PROC_D5

SLW_PROC_D1SLW_PROC_D0

SLW_PROC_D2SLW_PROC_D3

POS_PROC_RESET

PROC_DRAM_RAS2#PROC_DRAM_RAS1#PROC_DRAM_RAS0#

PROC_READY#

SLW_PROC_D6

PROC_DRAM_WE#

DUART_CLK

QL12X16B-2PL84C

C1710.1

C1720.1 0.1

C174C1730.1

VCC VCC VCCVCC

BYPASS CAPACITORS FOR U19.

7615

43

7826

141312111

848375

16

44

4845474958605955

77

56

271718

28

65

29307468

24

6454

21

66

57

Page 45: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 30a

J7

3579

2468

5153555761636537

2123252735

505254565860626438

2022242636

49

67686970

44453433

1213

19

1415161718283132

40434142

47

SIMM1

AMP822134-3

NC=11,29,46,48,66,71VCC;10,30,59GND;1,39,72SIMM72\SKT

PROC_DRAM_ADDR[10:0]PROC_DRAM_ADDR6PROC_DRAM_ADDR7PROC_DRAM_ADDR8PROC_DRAM_ADDR9PROC_DRAM_ADDR10

PROC_DRAM_ADDR5PROC_DRAM_ADDR4PROC_DRAM_ADDR3PROC_DRAM_ADDR2PROC_DRAM_ADDR1PROC_DRAM_ADDR0

PROC_DRAM_RAS2#

PROC_DRAM_RAS0#

PROC_DRAM_CAS0#

PROC_DRAM_WE#

A0A1

A10

A2A3A4A5A6A7A8A9

CAS0CAS1CAS2CAS3

DQ0DQ1

DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17

DQ18DQ19

DQ2

DQ20DQ21DQ22DQ23DQ24DQ25DQ26

DQ27DQ28DQ29

DQ3

DQ30DQ31DQ32DQ33DQ34DQ35

DQ4DQ5DQ6DQ7DQ8

DQ9

PD1PD2PD3PD4

RAS0RAS1RAS2RAS3

W

PROC_DRAM_CAS3#PROC_DRAM_CAS2#PROC_DRAM_CAS1#

PROC_D[31:0]

PROC_D31PROC_D30PROC_D29PROC_D28PROC_D27PROC_D26PROC_D25PROC_D24

PROC_D23PROC_D22PROC_D21PROC_D20PROC_D19PROC_D18PROC_D17PROC_D16

PROC_D0PROC_D1PROC_D2PROC_D3PROC_D4PROC_D5PROC_D6PROC_D7

PROC_D8PROC_D9PROC_D10PROC_D11PROC_D12PROC_D13PROC_D14PROC_D15

C1770.10.1

C1760.1C175

BYPASS CAPACITORS FOR J7.

VCCVCCVCC

Generic DRAM 72 Pin Socket

Page 46: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 30b

J8

3579

2468

5153555761636537

2123252735

505254565860626438

2022242636

49

67686970

44453433

1213

19

1415161718283132

40434142

47

SIMM1

AMP822134-3

NC=11,29,46,48,66,71VCC;10,30,59GND;1,39,72SIMM72\SKT

PROC_DRAM_ADDR[10:0]PROC_DRAM_ADDR6PROC_DRAM_ADDR7PROC_DRAM_ADDR8PROC_DRAM_ADDR9PROC_DRAM_ADDR10

PROC_DRAM_ADDR5PROC_DRAM_ADDR4PROC_DRAM_ADDR3PROC_DRAM_ADDR2PROC_DRAM_ADDR1PROC_DRAM_ADDR0

PROC_DRAM_RAS3#

PROC_DRAM_RAS1#

PROC_DRAM_CAS0#

PROC_DRAM_WE#

A0A1

A10

A2A3A4A5A6A7A8A9

CAS0CAS1CAS2CAS3

DQ0DQ1

DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17

DQ18DQ19

DQ2

DQ20DQ21DQ22DQ23DQ24DQ25DQ26

DQ27DQ28DQ29

DQ3

DQ30DQ31DQ32DQ33DQ34DQ35

DQ4DQ5DQ6DQ7DQ8

DQ9

PD1PD2PD3PD4

RAS0RAS1RAS2RAS3

W

PROC_DRAM_CAS3#PROC_DRAM_CAS2#PROC_DRAM_CAS1#

PROC_D[31:0]

PROC_D31PROC_D30PROC_D29PROC_D28PROC_D27PROC_D26PROC_D25PROC_D24

PROC_D23PROC_D22PROC_D21PROC_D20PROC_D19PROC_D18PROC_D17PROC_D16

PROC_D0PROC_D1PROC_D2PROC_D3PROC_D4PROC_D5PROC_D6PROC_D7

PROC_D8PROC_D9PROC_D10PROC_D11PROC_D12PROC_D13PROC_D14PROC_D15

C1800.10.1

C1790.1C178

BYPASS CAPACITORS FOR J8.

VCCVCCVCC

Generic DRAM 72 Pin Socket

Page 47: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 31a

80960JXU1

B4

C12

A14D12B13

C13

A11B10A12B11B12A13C10C11

E12

F12

A10

C1

C9

H14

B1

A2B3

C2

B2D3

E3

F3

C3

L2L1J3H3

A3G3

A1

C6

M11M12N13P14L12M13

K3M1

N14

M2L3N1N2P1N3M4P2M5N4

K12

P3P4M6M7M8M9P12M10P13N12

L13M14

C4C5

PGA132\SKTVCC;A6,A7,A8,A9,D1,D14,E1,E14,F1,F14,G1,G14,H1VCC;J1,J14,K1,K14,L14,P5,P6,P7,P8,P9,P10,P11,H12GND;B6,B7,B8,B9,D2,D13,E2,E13,F2,F13,G2,G13GND;H2,H13,J2,J13,K2,K13,N5,N6,N7,N8,N9,N10,N11

10KR189

TP5

R19010K

STEST

XINT7XINT6XINT5XINT4XINT3XINT2XINT1XINT0

TRST

TMSTDITCK

RESET

RDYRCV#

NMI

LOCK#_ONCE#

HOLD

CLKIN

W_R

WIDTH1WIDTH0

TDO

HOLDA

FAIL

D_CDT_R

DEN

BSTAT

BLAST

BE3#BE2#BE1#BE0#

ALE#ALE

ADS

AD9AD8AD7AD6AD5AD4

AD31AD30

AD3

AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20

AD2

AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10

AD1AD0

A3A2

JXPROC_ONCE#

PROC_CLK1PROC_BE3#PROC_BE2#PROC_BE1#PROC_BE0#

PROC_HOLD

PROC_XINT4#PROC_XINT5#PROC_XINT6#PROC_XINT7#

PROC_XINT3#PROC_XINT2#PROC_XINT1#PROC_XINT0#

PROC_NMI#

PROC_READY#

PROC_RESET#

PROC_D16PROC_D17PROC_D18PROC_D19PROC_D20PROC_D21PROC_D22PROC_D23PROC_D24PROC_D25PROC_D26PROC_D27PROC_D28PROC_D29PROC_D30PROC_D31

PROC_D12PROC_D11PROC_D10PROC_D9

PROC_D7PROC_D6PROC_D5

PROC_D1PROC_D0

PROC_D2PROC_D3PROC_D4

PROC_D8

PROC_D13PROC_D14PROC_D15

PROC_FAIL#

VCC

VCC

0.1C185

0.1C181 C182

0.1 0.1C183

0.1C184

0.1C188

0.1C187C186

0.1

VCC VCC VCC VCC VCCVCCVCCVCC

BYPASS CAPACITORS FOR U1

R8122.7K 2.7K

R8142.7KR813

PROC_XINT6#PROC_XINT5#PROC_XINT4#

PROC_XINT0#PROC_XINT1#PROC_XINT2#PROC_XINT3#

VCC

2.7KR817

2.7KR818

2.7KR816

2.7KR815

VCC

PROC_ADS#

PROC_DT/R#

PROC_DEN#PROC_BLAST#

PROC_W/R#

PROC_HOLDA

PROC_BSTAT

PROC_ALE

PROC_A3PROC_A2

PROC_D[31:0]

Page 48: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 31b

PROC_XINT7#

PLX_LSERR#

PROC_NMI#

P231X3_HDR

1

2

3

R8192.7K

R8202.7K

VCC

0.1C191 C192

0.10.1C190

0.1C189

VCC VCCVCCVCC

BYPASS CAPACITORS FOR U38-U41.

74ABT573U40

111

129138147156165174183192

U3974ABT573

111

129138147156165174183192

74ABT573U38

111

129138147156165174183192

74ABT573U41

111

129138147156165174183192

8Q8D7Q7D6Q6D5Q5D4Q4D3Q3D2Q2D1Q1D

8Q8D7Q7D6Q6D5Q5D4Q4D3Q3D2Q2D1Q1D

8Q8D7Q7D6Q6D5Q5D4Q4D3Q3D2Q2D1Q1D

ADLATCH_OE#

PROC_A31PROC_A30PROC_A29PROC_A28PROC_A27PROC_A26PROC_A25PROC_A24

PROC_A23PROC_A22PROC_A21PROC_A20PROC_A19PROC_A18PROC_A17PROC_A16

PROC_A15PROC_A14PROC_A13PROC_A12PROC_A11PROC_A10PROC_A9PROC_A8

PROC_A7PROC_A6PROC_A5PROC_A4

PROC_A[31:2]

PROC_D16PROC_D17PROC_D18PROC_D19PROC_D20PROC_D21PROC_D22PROC_D23

PROC_D24PROC_D25PROC_D26PROC_D27PROC_D28PROC_D29PROC_D30PROC_D31

PROC_D15PROC_D14PROC_D13PROC_D12PROC_D11PROC_D10PROC_D9PROC_D8

PROC_D7PROC_D6PROC_D5PROC_D4PROC_D3PROC_D2PROC_D1PROC_D0

8Q8D7Q7D6Q6D5Q5D4Q4D3Q3D2Q2D1Q1D

LATCHOELE

LATCHOELE

LATCHOELE

LATCHOELE

PROC_ALE

PROC_D[31:0]

PROC_A3

PROC_A2

Page 49: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 32a

U140

AUGAT_TS04

SHUNT4

432

8765

1

432

8765

1

TP6

10K

R198 10K

R197

10K

R200

10K

R196 10K

R195

10K

R193

10K

R194

U280C960HX

PGA168\SKTA80960HD-66NC=A9,A10,B13,B14,D3

F15C12C11C10C9C8C7

Q11Q10Q9Q8Q7M15M3

C4

L15L3K15K3J15J3H15H3G15G3

A1

C17C16B17C15B16A17A15B15

A6B6A7

B5

B2

A16

S3

C3

D15

R5

G1F1E1F2D1E2

R3Q5

C1

S2Q4R2Q3S1R1Q2P3Q1P2

D2

P1N2N1M1L1L2K1J1H1H2

C2E3

C13

R4

B1

A5

A8B8

A2

B4A4B3A3

A14A13A12A11

S10

S12Q12

S14

S4

S13

S11

S9

R12

R13

S8

S5S6S7R9

R6

H17G17G16F17E17E16

S15Q13

D17

R14Q14S16R15S17Q15R16R17Q16P15

D16

P16Q17P17N16N17M17L16L17K17J17

C5

G2F16

F3E15C6

B12B11

C14B10R11R10

R8R7

B9

Q6N15

N3M16

M2K16

K2J16J2

H16

B7

R191

10K

U141

AUGAT_TS04

SHUNT4

432

8765

11

5678

234

R299

100

10K

R199

HX_VOLT

HX_VOLT

PROC_BSTAT

PROC_HOLDA

PROC_RESET#

PROC_BOFF#PROC_HOLD

PROC_D[31:0]

PROC_D0PROC_D1PROC_D2PROC_D3PROC_D4PROC_D5PROC_D6PROC_D7PROC_D8PROC_D9PROC_D10PROC_D11PROC_D12PROC_D13PROC_D14PROC_D15PROC_D16PROC_D17PROC_D18PROC_D19PROC_D20PROC_D21PROC_D22PROC_D23PROC_D24PROC_D25PROC_D26PROC_D27PROC_D28PROC_D29PROC_D30PROC_D31

HXPROC_ONCE#

PROC_READY# PROC_BE2#PROC_BE1#PROC_BE0#

PROC_XINT4#PROC_XINT5#PROC_XINT6#PROC_XINT7#

PROC_XINT3#PROC_XINT2#PROC_XINT1#PROC_XINT0#

PROC_ADS#

PROC_W/R#

PROC_BLAST#

PROC_NMI#

PROC_BE3#

PROC_CLK2

PROC_DT/R#

TDO

PROC_DEN#

PROC_BREQ

HX_VOLT

INTALL THIS SHUNTFOR CX PROCESSOR

3.3V

VCC

VCC

W_R#

WAIT#

VOLTDET

SUP#

PCHK#

LOCK#

HOLDA

FAIL#

D_C#

DT_R#

DP3DP2DP1DP0

DEN#

CT3CT2CT1CT0

BSTALL

BREQ

BLAST#

BE3#BE2#BE1#BE0#

ADS#

A9A8A7A6A5A4

A31A30

A3

A29A28A27A26A25A24A23A22A21A20

A2

A19A18A17A16A15A14A13A12A11A10

GNDGND

GNDGNDGNDGND

GNDGNDGNDGNDGND

GNDGNDGNDGNDGND

GNDGNDGNDGNDGND

GNDGNDGNDGNDGND

XINT7#XINT6#XINT5#XINT4#XINT3#XINT2#XINT1#XINT0#

VCC5

TRST#TMSTDI

TCK

STEST

RESET#

READY#

ONCE#

NMI#

HOLD

D9D8D7D6D5D4

D31D30

D3

D29D28D27D26D25D24D23D22D21D20

D2

D19D18D17D16D15D14D13D12D11D10

D1D0

CLKIN

BTERM#

BOFF#

VCCPLLVCC

VCCVCCVCCVCCVCC

VCCVCCVCCVCCVCCVCCVCC

VCCVCCVCCVCCVCCVCCVCCVCC

VCC

VCC

VCC

PROC_FAIL#

PROC_A31PROC_A30PROC_A29PROC_A28PROC_A27PROC_A26PROC_A25PROC_A24PROC_A23PROC_A22PROC_A21PROC_A20PROC_A19PROC_A18PROC_A17PROC_A16PROC_A15PROC_A14PROC_A13PROC_A12PROC_A11PROC_A10PROC_A9PROC_A8PROC_A7PROC_A6PROC_A5PROC_A4PROC_A3PROC_A2

PROC_A[31:2]

INTALL THIS SHUNTFOR HX PROCESSOR

Page 50: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 32b

R19210K

P241X3_HDR

3

2

1

PROC_BSTAT

PROC_BREQ

PLX_BREQ

C2020.1

C2010.1

C31022UF2

1C30922UF2

1C30722UF2

1

22UFC306

2

1C30522UF2

1

22UFC304

2

1

0.1C205 C206

0.1 0.1C207 C208

0.10.1C204

0.1C203

C30322UF2

1

22UFC308

2

1

C1930.1

C1940.1 0.1

C1950.1C196

0.1C197 C198

0.1 0.1C199 C200

0.1

HX_VOLT

HX_VOLT

HX_VOLT

+++++++ +

BULK CAPACITORS FOR U2.

BYPASS CAPACITORS FOR U2.

BYPASS CAPACITORS FOR U2.

Page 51: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 33a

2.7K

R822

22UFC340

P26

8

5

1234

67

PWRCON8

5

1234

6

R824

2.7K 2.7K

R823

2.7K

R821

J6

PCI_CONN

B62B61

B59

B19

B6B5

B54

B43

B41

B36

B31

B25

B4

B2

B42

B14

B10

B18

B11

B9

B40

B1

B39

B35

B8B7

B38

B34

B28

B22

B17

B15

B13B12

B57

B49

B46

B3

B37

B26

B33

B44

B16

B52B53

B55

B20

B56

B21

B23B24

B27

B29B30

B32

B45

B47B48

B58

B60

22UFC336

22UFC335

2

1

C33722UF 22UF

C338 C33922UF 22UF

C341

PCI_AD[31:0]

PCI_AD30

PCI_AD26

PCI_AD24

PCI_AD22

PCI_AD0PCI_AD2

PCI_AD4

PCI_AD18

PCI_AD28

PCI_AD20

PCI_AD16

PCI_AD15

PCI_AD13PCI_AD11

PCI_AD9

PCI_AD6

PCI_AD31PCI_AD29

PCI_AD27PCI_AD25

PCI_AD23

PCI_AD21PCI_AD19

PCI_AD17

PCI_AD1

PCI_AD3PCI_AD5

PCI_AD7PCI_AD8

PCI_AD10PCI_AD12

PCI_AD14

PROC_XINT0#

PCI_CLK6

TRST

TRDY

TMSTDO TDI

TCK

STOP

SERR

SDONESBO

RST

REQ64

REQ

PRSNT2

PRSNT1

PERR

PAR

LOCK

IRDY

INTDINTCINTBINTA

IDSEL

GNT

FRAME

A10

A8

A5

A16

A27

A21

A1

A3A4

A15

A19

A14

A11

A9

A2

A7A6

A26

A17

A30

A24

A18

A13A12

A20

A22A23

A25

A28A29

A31A32

A33

A45

A39

A36

A38

A40A41

A43

A48

A42

A37

A35A34

A49

A44

A46A47

A62A61

A59

A53

A60

A56

A52

A54A55

A57A58

A37DEVSEL

CLK

AD9

AD8AD7

AD6AD5 AD4

AD31 AD30

AD3

AD29AD28

AD27 AD26AD25

AD24

AD23AD22

AD21 AD20

AD2

AD19AD18

AD17 AD16

AD15AD14

AD13AD12 AD11AD10

AD1 AD0

ACK64

PCI_FRAME#

PCI_LOCK#

PCI_DEVSEL#

PCI_IRDY#

PCI_CONN_REQ#

PCI_RST#

PCI_CONN_GNT#

PCI_TRDY#

PCI_STOP#

PCI_PERR#

PCI_SERR#

PCI_C/BE2#

PCI_C/BE3#

PCI_C/BE1#

PCI_C/BE0#

PCI_PAR

PROC_XINT0#

VCC

VCC

VCC

+12V

+12V

+5V

GND

+3.3V

+3.3V

GND

+3.3V

GND

+5V

GNDGND

+5V

+5V+5V

+5V

GND

+3.3V

GND

+3.3V

GND

+3.3V

GND

GND

+3.3V

GND

GND

+5V

+3.3V

GND

+5V

+5V

GND

+3.3V

GNDC/BE2

+3.3V

+3.3V

GND

+3.3VC/BE3

GND

GND

+5V

GNDGND

C/BE1

GND

GND

+5V

+5V

+5V

C/BE0

-12V

VCC

+

-12V

PCI +3.3V 2

1

2

1

2

1

2

1

2

1

2

1+

+

+ + + +

VCC

Page 52: SWITCHED ETHERNET REFERENCE DESIGN SCHEMATICS · pci_conn_req# pci_sec2_req# pci_plx_req# req1 ad9 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad23 ad24 c/be1 c/be2 c/be3 ad26 ad28

Order Number: 272907-001 July, 1996

Appendix A: Switched Ethernet Reference Design Schematics

Switched Ethernet ReferenceDesign Description

Switched Ethernet Reference Design—Sheet 33b

C33022UF

C32522UF 22UF

C326

C32722UF 22UF

C32822UFC329

22UFC331

C32322UF

C31922UF 22UF

C320 C32122UF 22UF

C32222UFC324

22UFC332 C333

22UF 22UFC334

P25

65

1234

PWRCONN

4321

56

VCC

VCC

BULK CAPACITORS DISTRIBUTED ACROSS THE PCB

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 + +++ + + + +

VCC

BULK CAPACITORS DISTRIBUTED ACROSS THE PCB

22UFC318

2

1C31722UF

2

1C31522UF

2

122UFC314

2

1C31322UF

2

122UFC312

2

122UFC311

2

122UFC316

2

1 +++++++ +

VCC

BULK CAPACITORS DISTRIBUTED ACROSS THE PCB

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1++ + + + + + +