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7/29/2019 Switched Cap Circuits I
1/22
Switched Capacitor Circuits I
Prof. Paul Hasler
Georgia Institute of Technology
7/29/2019 Switched Cap Circuits I
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Switched Capacitor Circuits
Making a resistor using a capacitor and switches;
therefore resistance is set by a digital clock and the capacitor.
Filters built in this technology are set by external clocks,
and ratio of capacitors (matching of 0.1% to 1%)
The precision of the frequency response is realized by ratios of capacitors
(1% to 0.1%better matching, larger caps; therefore more power/area),and a clock signal (which can be set precisely with a crystal reference)
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Capacitor Circuits
Vout
(t)
GND
C2
C1
V1(t)
Capacitive Voltage Divider
Vout(t) = V1(t) +CT
C1
CT
Q
Q
Vout(t)
GND
C3
C2
V2(t)
C1
V1(t)
Multiple Input Voltage Divider
Vout
(t) = V1(t) + V
2(t) +
CT
C1
CT
Q
CT
C2
Capacitive Feedback
V1(t)
Vout
(t)
GND
C2
C1
Q
CT
Vfg
Vout
(t) = - V1(t) -
C2
C1
C2
Q
V2(t)
Vout
(t)GND
C2
C1
Q
CT
Vfg
Vout
(t) = (1 + ) V1(t) -
C2
C1
C2
Q
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Non-Overlapping Clocks
We will always be using non-overlapping clocks; therefore, we want a waveform like
1
2
We effectively have
four phases.
t
td
[n] cycle
(1) (2) (3) (4)
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Non-Overlapping Clocks
We will always be using non-overlapping clocks; therefore, we want a waveform like
1
2
We effectively have
four phases.
t
td
Would want td
as small as possible
for proper operation
[n] cycle
(1) (2) (3) (4)
We will also assume that the input
is held constant through
the entire [n]th cycle
7/29/2019 Switched Cap Circuits I
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Non-Overlapping Clocks
We will always be using non-overlapping clocks; therefore, we want a waveform like
1
2
We effectively have
four phases.
t
td
Would want td
as small as possible
for proper operation
[n] cycle
(1) (2) (3) (4)
We will also assume that the input
is held constant through
the entire [n]th cycle
N-stages of delay(sets t
d)
Circuit to generate waveform
Clock in 1
2
7/29/2019 Switched Cap Circuits I
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Basic Switched Capacitors
1
GND
V1(t)
2
C1
V2(t)
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Basic Switched Capacitors
1
GND
V1(t)
2
C1
V2(t)
V1[n] V
2[n]
C1
V1[n]
I(1), [n] cycle
Q = C1(V1[n] V2[n-1])
GND
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Basic Switched Capacitors
1
GND
V1(t)
2
C1
V2(t)
V1[n] V
2[n]
C1
V1[n]
V1[n] V
2[n]
C1
V2[n]
I
I
(3), [n] cycle
(1), [n] cycle
Q = C1(V1[n] V2[n-1])
Q = C1(V1[n] V2[n])
GND
GND
7/29/2019 Switched Cap Circuits I
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Basic Switched Capacitors
1
GND
V1(t)
2
C1
V2(t)
V1[n] V
2[n]
C1
V1[n]
V1[n] V
2[n]
C1
V2[n]
I
I
(3), [n] cycle
(1), [n] cycle
If we assume the input changes slowly
(V2[n-1] ~ V2[n]; therefore we are oversampling),
we get
I = Q f = f C1(V1(t) V2(t)) ; R = 1 / (C1 f)
where f = clock frequency.
Q = C1(V1[n] V2[n-1])
Q = C1(V1[n] V2[n])
GND
GND
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Basic Switched Capacitors
1
GND
V1(t)
2
C1
V2(t)
I
where f = clock frequency.
V1
(t) V2
(t)
R = 1 / (C1 f)~
7/29/2019 Switched Cap Circuits I
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Basic Switched Capacitors
1
GND
V1(t)
2
C1
V2(t)
I
where f = clock frequency.
V1
(t) V2
(t)
R = 1 / (C1 f)~For 0.1pF capacitor,
and a 10kHz clock,
we get a resistance of 1GOhm
7/29/2019 Switched Cap Circuits I
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Basic Switched Capacitors
1
GND
V1(t)
2
C1
V2(t)
I
where f = clock frequency.
V1
(t) V2
(t)
R = 1 / (C1 f)~
Rule of thumb: slow moving means
we oversample the Nyquist frequency of the
input signal by a factor of20 or more.
For 0.1pF capacitor,
and a 10kHz clock,
we get a resistance of 1GOhm
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Basic Switch-Cap Integrator
C2
V1[n]
Vout
[n]
GND
C2
R1
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Basic Switch-Cap Integrator
1
GND
V1[n]
Vout
[n]
2
GND
C2
C1
We will step through all four phases, to get the proper result.
V1[n]
Vout
[n]
GND
C2
R1
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Basic Switch-Cap Integrator
GND
V1[n-1]
Vout
[n-1]
GND
C2
C1
Vout
[n-1]
This case is important to understand our starting point
charge is stored on a capacitor ; therefore we need to know the initial state
(4), [n-1] cycle
Q = -C2Vout[n-1]
Voltage = 0V(Voltage remains held)
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Basic Switch-Cap Integrator
GND
V1[n]
Vout
[n-1]
GND
C2
C1
Vout
[n-1]
Charge up the capacitor with voltage V1[n]
(1), [n] cycle: 1
Q = -C2Vout[n-1]
(Output unchanged)
V1[n]
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Basic Switch-Cap Integrator
GND
V1[n]
Vout
[n-1]
GND
C2
C1
Vout
[n-1]
We remove the capacitor from the input voltage.
The voltage is stored across the capacitor
(2), [n] cycle
Q = -C2Vout[n-1]
(Output unchanged)
Q1 = C1V1[n]
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Basic Switch-Cap Integrator
GND
V1[n]
Vout
[n] = Vout
[n-1] -
GND
C2
C1
(C1/C
2) V
1[n]
We connect the capacitor to the charge summing node
The charge initially stored on the capacitor as well as the resulting
charge from the second input (V2[n]) contributes to the total charge
(3), [n] cycle: 2
Q = -C2Vout[n-1]
+ C1V1[n]
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Basic Switch-Cap Integrator
GND
V1[n]
Vout
[n]
GND
C2
C1
Vout
[n] = Vout
[n-1] -
(C1/C2) V1[n]
We disconnect the capacitor from the charge summing node,
and return to our initial case
(4), [n] cycle
(Output unchanged)
Q = -C2Vout[n-1]
+ C1V1[n]
Vout[n] = Vout[n-1] - (C1/C2) V1[n]
Voltage = 0V
Q1 = 0
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Basic Switch-Cap Integrator
1
GND
V1[n]
Vout
[n]
2
GND
C2
C1
Vout[n] = Vout[n-1] - (C1/C2) V1[n]
Vout(z)
1 - z-1V1(z)= H(z) = - (C1/C2)
1
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Basic Switch-Cap Integrator
1
GND
V1[n]
Vout
[n]
2
GND
C2
C1
Vout[n] = Vout[n-1] - (C1/C2) V1[n]
Vout(z)
1 - z-1V1(z)= H(z) = - (C1/C2)
1
H(j) = - (C1/C2)1 - e-jT
1
~ - (C1/C2) / jT
assumesT