Survey of Programmable Video Signal Processors

CET-520

Kshipra Bopardikar

Agenda

• Digital Multimedia Applications• Explanation of MPEG Concepts• Discussion of Algorithms used• MPEG Encoder• PVSP architecture proposed in Paper 1 (1989)

• PVSP architecture proposed in Paper 2 (2002)

• Comparison • Conclusion

Multimedia Applications• Entertainment

• HDTV• Video on Demand (VoD)• Music (MP3) Sharing

• Communication• Video Phone / 3G Mobile Phones• PDAs• Video Conferencing

• Cameras• IP Cameras• Digital Camcorders

• Other Fields• Image Processing• Robotics

Traditional Microprocessor Limitations

Modern multimedia applications are characterized by large amounts of data processing at a very high speed. Traditional general purpose Microprocessors are ill-suited for these applications because:

Logic overhead: Various Data types,Registers, Memory hierarchy, etc. are designed with desktop data processing in mind – not Video Signal Processing.

Unpredictability: Because of the complexity of logic, microprocessors can be unpredictable.

Speeds: In applications such as MPEG-4 encoding, over 50% of processor cycles may be spent evaluating one block of an algorithm (e.g. motion estimation, etc.). Hence there is a need for hardware implementation of these algorithms.

What is a PVSP ?

• Video Signal Processor (VSP) is a processor which is specifically designed to cater the needs of complex digital video signal computations.

• P-VSP is programmable VSP. It is designed by abstracting a wide range of video processing algorithms that need to be supported.

P-VSP Requirements

ThroughputFast clock speedHigh parallelismHigh utilization

StorageLarge on-chip memoryLarge register fileEfficient memory I/O

Programmability

MPEG Fundamentals

• MPEG• A video stream is a sequence of

video frames. Each frame is a still image.

• Frames are divided into 16x16 pixel macro-blocks.

• Macro-blocks are the units for motion-compensated compression.

Motion Estimation/Compensation

M.E. Output i.e. Motion

Vector

Motion Compensation from previous frame for data compression

M.C. Signal to Recover Image

MPEG Encoder Architecture

DCT

Motion Estimation

Frame Memory

Encoding

Inverse DCT

Quantization

+

-

InverseQuantization

Motion Compensation

Raw Video Signal

MPEG Signal

Old Frame Information

for M.E.

Old Frame Information

for M.C.

Recover Original Image

Forward Path

Video Processing Algorithms

Motion Estimation Motion Compensation Discrete Cosine Transform (DCT) Inverse-DCT Quantization / Inverse

Quantization Variable Length Coding (VLC) Variable Length Decoding (VLD)

Overview of Research Paper-1

Chip Level Architecture

Module Level Architecture

Overview of Research Paper-2

Paralleling Techniques in Research Paper 2: Pipelining

Algorithm Pipeline Stages

Motion Estimation ID MR PALU TA ACC    

Motion Compensation ID MR PALU MW      

DCT ID MR PALU PMA0 PMA1 PMA2 MW

Inverse DCT ID MR PMA0 PMA1 PMA2 PALU MW

Quantization / Inverse Q.

ID MR PMA0 PMA1 MW    

VLC IS SA ECO        

VLD CAD SM SR        

Other Optimization Techniques in Research Paper 2: Tree Adder SIMD PMA

Comparison

Research Paper 1(1989)

Research Paper 2(2002)

It has multiple VSP chips

It has only single chip

Techniques like Tree Adder , SIMD for parallel processing were not available.

Made use of pipelining,SIMD to for parallel processing.

Works at frequency of 27MHz

Can Work at frequency of 133MHz

1.8 million transistors used

4 million transistors used

Conclusion

• The architecture proposed in Research Paper-1 is over a decade old.

• Research Paper 1 was proposed before the MPEG standards were formulated, and hence it does not address the specific requirements of the MPEG compression algorithms such as DCT, I-DCT.

• It involves multiple VSP chips thus increasing cost.• Research paper 2 has strong advantages in price,

size, state-of-the-art technology and usefulness.

References1. "Programmable parallel processor for video processing" by Takao Nishitani, Ichiro

Tamitani and Hidenobu Harasaki2. "A reconfigurable digital signal processor for high-efficiency MPEG-4 video encoding"3. “MultiProcessor performance for Real-Time Processing of Video Coding Applications”

By Peter Pirsch, Klaus Gaedke4. "A general purpose video signal processor: architecture and programming" by Dijkstra,

Essink, Hafkamp, den Hengst, Huizer, van Roermund, Sluyter and Snijder5. Amphion MPEG-4 Video Encoder (CS6701) Preliminary Product Brief

(http://www.amphion.com)6. “Datapath Design for a VLIW Video Signal Processor” Presentation by Json Fritts

(Princeton University)7. “A Video Signal Processor for MIMD Multiprocessing” Presentation by Jorg Hilgenstock,

Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer & Peter Pirsch (University of Hannover)8. “MPEG Compression” Presentation from Xilinx.9. “Array-of-Arrays Architecture for Parallel Floating Point Multiplication” by Dhanesha,

Falakshahi and Horowitz, Stanford University

10. “A high performance low-power asynchronous matrix-vector multiplier for discrete

cosine transform” by Kim and Beerel, University of Southern California