IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-23, NO. 2, FEBRUARY 1916 257

Supply Charge Isolation-A Simple Surface Potential Equilibration Charge-Injection Technique for

Charge-Coupled Devices ROGER A. HAKEN

Absfract-A simple high-linearity charge-injection technique for charge-coupled devices (CCD’s) is described, analyzed, and practical re- sults presented. The technique is of the potential equilibration type and utilizes the formation of a potential barrier and charge-storage site under one CCD electrode adjacent to an input diode. This obviates the need for an input clock, as used in previously reported surface potential equilibration charge-injection techniques, by isolating a fiied quantity of “supply charge” from the input diode and the CCD transfer elec- trodes. The analog signal is applied to the succeeding CCD electrode and depending upon its amplitude some, or all, of the supply charge is transferred to under this electrode, and by subsequent CCD action through the register. A theoretical analysis of the technique predicts that nonlinearity vanishes as the effects of the depletion region capaci- tance are eliminated. In practice, however, a small nonlinear effect, being mainly attributed to charge “slopping,” does occur, causing a re- duction in the useful dynamic range of the device for a particular level of linearity. Experiments have indicated that a useful dynamic range of 47.5 dB is attainable with all harmonic components at least 45 dB below the fundamental with a total harmonic distortion of less than 1.2 percent.

Variations in threshold voltages between different input stages does not effect the quantity of charge injected (within certain operating limits), but does result in small variations of the maximum useful dy- namic range of the devices.

The technique is particularly suited to two-phase CCD’s because it allows linear charge injection, charge transfer, and reset sensing to be accomplished using only one clock.

F I. INTRODUCTION

OR ANALOG signal processing applications, charge- coupled devices (CCD’s) require a charge-input technique that will inject charge packets into the CCD which are

proportional to the amplitude of the analog signal. Ideally, the input technique should exhibit a high linearity over a wide dynamic range with a minimum of circuitry for controlling the injection of charge into the CCD.

Several simple CCD charge-injection techniques that utllize an input diode and an input gate have been reported [ 11 -[4] . However, these simple techniques are unsatisfactory in appli- cations requiring a linear voltage-to-charge conversion because of the nonlinearity of the depletion region capacitance. Tech- niques discussed in [ 13 -[4] also suffer from the disadvantage that when the input gate is turned off an indefinite amount of charge spills forward. This quantity of charge depends in a nonlinear manner on the rise time of the trailing edge of the

Manuscript received May 20, 1975; revised September 17, 1975. This work was supported by Southern Television Limited and the Science Research Council.

The author was with the Department of Electronics, Southampton University, Southampton, England. He is now with Fairchild Semicon- ductor Limited, Bristol, England.

gate pulse and the original channel charge. Furthermore, very low signal levels (less than a volt) are required with these tech- niques and the quantity of charge transferred is both very sen- sitive to the threshold voltage of the input gate and the dc bias levels.

In order to overcome the nonlinearities due to charge spill- ing and variations in depletion capacitance surface potential equilibration, charge-injection techniques have been proposed [ 5 ] , [6]. These techniques also offer the advantage in that they are independent of threshold voltage variations and can handle high-signal levels (several volts). However, a disadvan- tage of both these techniques is the requirement of an addi- tional clock which must be applied to the input diode.

A further disadvantage of all the techniques mentioned above is that they cannot be used in conjunction with two-phase devices that have their barrier and storage sites of each element automatically joined together (i.e., where independent access to the electrodes on the barrier and storage sites is not possible) unless separate nondirectional gates are fabricated next to the input diode. Two-phase fabrication technologies that exhibit the technological advantage of automatic barrier and storage site electrode interconnection are, for example, ion-implanted barrier devices [7] and devices fabricated by the oblique de- position of aluminium over gate-oxide steps [8]. If any of the above input techniques are used in conjunction with these types of two-phase structures, where additional nondirectional input gates have not been fabricated, the storage site under the analog signal input gate will eventually saturate. Consequently, the signal injected into the CCD will become independent of the amplitude of the input signal.

A technique used for injecting a linear quantity of charge into a two-phase implanted barrier device has been reported [7], but this requires the generation of an input clock on to which the analog signal is superimposed. The amount of charge injected into the CCD is then a function of both the analog signal amplitude and the frequency of the input clock.

A surface potential equilibration charge-injection technique that utilizes the formation of a potential barrier and a charge- storage site under one CCD electrode will be described in this paper. It will be shown that although the technique does not require the generation of an input clock, it does satisfy the above mentioned requirements for the linear conversion of voltage to charge. Furthermore, it will be shown that the in- jection technique can be used not only for two-phase CCD’s, where the electrodes of the barrier‘and storage sites of each element are joined together, but for devices that use only a single thickness of oxide; for example three-phase structures.

2 5 8 IEEE TRANSACTIONS ON ELECTRON DEVICES, FEBRUARY 1976

\ - n-type substrate

- - - - - - - - -

proportional to Input signal amplitude

Fig. 1. Charge-injection technique used in conjunction with a : w e phase stepped oxide device. (a) Cross section through input slage. (b) @’l “off” and no signal applied to the input gate. (c) @\ “on”’ and signal present on the input gate. (d) @’l “off” and signal present on the input gate.

11. CHARGE-INJECTION TECHNIQUE The technique utilizes the formation of a potential ballrier

and a charge-storage site under one CCD electrode adjacent to the input diode. This allows a fixed quantity of charge termed the “supply charge” (no larger than the maximum that can be transferred through the CCD) to be isolated from the irput diode and the CCD transfer electrodes. The analog signill is applied simultaneously to the next CCD electrode and, de- pending upon the amplitude of the signal, some, or all, of the supply charge will be transferred to the potential well u.nder this electrode, and by subsequent CCD action through the register. Any remaining supply charge under the first electlrode is not transferred forward, but simply added to from the ir.put diode on the next cycle. Consequently, saturation of the de- vice from the input diode is avoided.

Fig. 1 shows diagrammatically the principal stages of opera- tion of the charge-injection technique for a stepped-oxide 1wo- phase device. In practice the supply gate 4; would be con- nected to the G1 clock line and each would have a dc al’fset voltage equal to the threshold voltage for the thick oxide, In Fig. l(b) the $ J ~ clock is “off” and hence both $; and (bl are at their dc resting potentials; the reverse bias on the input diode is such that its potential is lower than the surface pote:ltial under the thick oxide of 4; (or G I ) . The analog signal i2 ap- plied to the input gate 4; which has a dc offset equal to the threshold voltage of the thick oxide plus the average ampli :ude of the analog signal. Fig. l(c) shows the depths of the pcten- tial wells when 4; is “on” and a signal is applied to 4;. Charge will now fill the q5; potential well, under both the thick and

input GLclocked by a, d i f f is lono G3

0

I

Fig. 2. (a) Chargeinjection technique adapted for use with a single-level oxide structure. (b) Position of depletion regions with C1 “off” and a signal present on G3.

thin oxides until the surface potential under the thick and thin oxides of @\ equals the potential of the reverse bias across the input diode. Fig. l(d) shows the situation when G1 is turned “off.” All the excess charge under 4; returns to the input diffusion as this charge sees a barrier to the right of 4; and a well to the left as the clock is turned off. (It should be noted that if the reverse bias on the ipput diode is insuffi- cient or the 41 clock is collapsed too quickly, some of this excess charge may be “slopped” into 4; .) When 4; reaches its resting potential the amount of charge transferred from the thin-oxide well of 4; into 4; is determined by the condition that the surface potential under the thin oxide of 4; equals the surface potential under the thick oxide of 4;; this amount of transferred charge is proportional to the amplitude of the sig- nal on 4;.

This technique may be extended to single-level oxide CCD structures, for example three-phase devices, by connecting the first two-gates together and clocking them with the $l clock but providing a dc offset between them so that a barrier and storage site are formed as shown in Fig. 2. The analog signal is applied to the third gate and the $2 clock to the fourth. With the device connected in this manner the same charge-injection mechanism as described for the two-phase device results.

To ensure correct operation of the charge-injection tech- nique, care must be taken in the design and operation of the devices. For example, in the case of the two-phase device the amplitude of the clock voltage applied to G1 must be large enough to ensure that the potential well depth under the thick oxide of q51 is greater than the maximum potential well-depth experienced under the thin oxide of 4; . In practice this means that in two- and three-phase operation higher clock voltages than normal are required. However, in the case of two-phase devices operated in uniphase, where G2 is biased at a potential midway between the extremes of G1 and double the clock height is used, correct operation of the input stage occurs automatically.

111. ANALYSIS OF CHARGE-INJECTION TECHNIQUE The brief description of the charge-injection technique used

in the last section did not take into account the fact that the surface potential differential between the thick and thin oxides, and hence the maximum charge-carrying capacity, is a strong

HAKEN: SUPPLY CHARGE ISOLATION 259

function of the gate voltage for a two-phase stepped oxide device. This is in contrast to the case for a three-phase single level oxide device where the injection capacity is mainly a function of the dc offset differential used between gates G1 and G2, Fig. 2.

Because the operation of the injection technique is slightly more complicated for the case of a two-phase stepped oxide structure an analysis will be performed for this device in order to determine 1) the maximum charge that can be stored under the supply gate for a particular gate voltage and 2 ) whether the charge transferred to the input gate is a linear function of the @; gate voltage. This analysis will then be applied to the case of a single-level oxide structure.

In a two-phase device the maximum charge-carrying capacity occurs when the inversion layer charge is such that the surface potential under the thin-oxide region equals that under the thick-oxide region. However, because of the modulation of the surface potential differential between the thick- and thin- oxide region by the gate voltage, this maximum amount of charge is not constant. In the charge-injection scheme out- lined in the last section, charge begins to flow from under $; to @; when the two gate voltages are equal. The maximum amount of charge that can be stored under @; before transfer occurs therefore is a function of the thick-oxide surface poten- tial under @; and hence the gate voltage on @;. Bearing this fact in mind an expression for the maximum amount of charge stored under @’, before transfer occurs can be derived and from this a relationship can be established between the input signal amplitude on 9; and the quantity of charge injected into the @; well from @;.

The expression relating the surface potential of an MOS structure to the gate voltage and inversion layer charge is well known [9] and is given below (assuming substrate grounded)

where @s is the surface potential, Cox is the oxide capacitance, Qs is the inversion layer charge, and

qND €si v o = 7 c o x

where q is the electronic charge, N D is the level of donor atom doping/cm3, esi is the permittivity of silicon, and

v& = vG - vffb where VG is the gate voltage and vffb is the flatband voltage.

A knowledge of the threshold voltages, Vt, for the thin and thick oxides allows calculation of the corresponding flat-band voltages by use of ( 2 ) :

where

@ s = = @ F

to, the oxide thickness fox the permittivity of silicon dioxide.

I2 N ~ = 1 . 1 0 ’ ~ atom/cm

v; = V G - V F B I V O l t S )

Fig. 3. Surface potential versus effective gate voltage.

Fig. 3 shows a graph of versus V& using (l), for the case of Qs = 0, for a practical device to be considered later. The modulation effect of the surface-potential differential between the thin and thick oxide by the gate voltage is clearly evident.

Inserting the condition for a full well into (l), i.e.,

$sn (Qs = QS ma,) = @sk (Qs = 0)

(subscripts n and k refer to thin and thick oxides, respectively) yields

Lox n

where

Now the depletion capacitance

(4)

Substitution of (5) into (4) yields

QS max = c o x n (VknS - @sk) - 2 @sk cDk (6 )

where Vbns is equal to V,, when charge is just about to trans- fer out of @;, i.e., when V G on @; equals VG on @;.

Charge will cease flowing from @; when 1) the gate voltage on @; has returned to its resting potential and the potential well depth under the thick oxide of @; is less than that under the thin oxide of @; or 2) when the potential well depth under the thick oxide of 4; is greater than that under the thin oxide of @; .

In case 1) charge will be left behind in the thin-oxide well under @;. To determine the quantity of charge left behind in $:, Vcns in (3) must be replaced by using the value corre- sponding to the resting gate voltage on @; , V G ~ R . The surface

260

potential under the thick oxide, @sk, still corresponds to the value under @; as that gate voltage has not been changed. 'The charge left is therefore given by

QSleft = cox n (VknR - @8k) - 2 @sk C D k . (7) It should be noted that in both (6 ) and (7) @& = @sn and

In order to determine the charge transferred to the @; PC ten- cDk = C D n *

tial well, (7) must be subtracted from (6), yielding

estrans = cox n (Vbns - V b n ~ 1, (8)

but Vbns corresponds to Vbn on $; which equals

VG ($;I - Vfb n

and V& corresponds to

VGR (6; - Vfb n

where ) is the resting potential on the @ \ gate. Substitution of these expressions into (8) yields

QStrans - Cox n (VG($; ) - VGR (G; 1). - (9 1

It should be noted that the expressions for Qs,,, and Qslef, contain a term which includes the nonlinear depletion Capacitance CD. However, this term is eliminated betweer the expressions in determining the quantity of charge transferred from 4; to @;. This results from the fact that the injection technique is of the potential equilibration variety; in this case the surface potential under the thin oxide of @; remains :on- stant throughout charge transfer at a value equal t o the surface potential under the thick oxide of @;. The fact that the flat- band voltages of the thick and thin oxides do not appear i r . (9) results from the assumption that the threshold voltages u:J.der adjacent @: and 4; electrodes are the same. Hence, from (9) the amount of charge transferred is directly proportionsi to the difference in gate voltage between 4; and the resting po- tential of @;. This is provided that the potential well dl:pth under the thick oxide of @; is less than or, at most, equal to the potential well depth under the thin oxide of @; , when its gate voltage is at the resting potential. If the potential well depth under the thick oxide of @; is greater than that wider the thin oxide of & (case 2 ) above), then (9) is no lotlger valid and the quantity of charge transferred is given by (6).

The charge-injection technique is independent of thres :told voltage variations in so far that the charge injected by o x in- put stage, under given operating potentials, is the same as another providing that the resting potential of @; is always equal to, or greater than, the threshold voltage of the thick oxide. However, variations in threshold voltages will cause variations in the maximum amount of charge that is lincarly related to the input signal amplitude. This is ta be expected because a device with a smaller threshold voltage differential requires a smaller input signal amplitude to make the potential well depth under the thick oxide of 4; equal to the potential well depth under the thin oxide of @;, with its gate vo1ta::e at the resting value. In practical terms variation in threshold volt- ages from one input stage to another results in a variation of the useful dynamic range (UDR) of the devices.

IEEE TRANSACTIONS ON ELECTRON DEVICES, FEBRUARY 1976

Input slgnal ornplltude In vol ts

Fig. 4. Theoretical values of Qs ,ax, Q,yleft, and Q,ytrans Versus input signd amplitude for a typical two-phase stepped oxide device.

The theoretical values of the maximum amount of charge storedunder @; before transfer, the charge transferred, and the charge left under $; after transfer are plotted in Fig. 4. These values correspond to a practical two-phase, stepped oxide, CCD having oxide thicknesses of 0.18 pm and 0.58 pm, correspond- ing to threshold voltages of 3.5 V and 7.5 V. The substrate was n-type with a doping of 1 X 10'' atoms/cm3 and the resting potentials of @; and 6; were equal to the threshold voltage of the thick oxide. The & versus V G characteristics of this device were those plotted in Fig. 3.

As expected in Fig. 4, the maximum amount of charge stored under @; before transfer and the charge left under @; after transfer vary in a nonlinear manner due to the depletion region capacitance. The amount of charge transferred from @\ to &, however, is a linear function of @; with a slope equal

to the capacitance of the thin oxide. At a gate voltage of ap- proximately 14 V on @; the potential well depth under the thick oxide of @; is equal to the potential well depth under the thin oxide of I$; with its gate voltage at the resting poten- tial. This value of gate voltage on @; corresponds to the point where the transfer characteristic becomes nonlinear, and repre- sents the maximum amplitude of an analog signal over which t h s charge-injection technique is linear.

Defining the maximum UDR of a CCD as the ratio of the minimum charge packet that can be detected to the maximum charge that can be transferred along the CCD, over which the input signal amplitude versus charge injection is linear, then the device considered has a UDR of 5 5 dB. This calculation is based upon a typical output diode capacitance of 0.5 pF and a minimum detectable charge-packet size of 0.5 X C. (It should be noted that the UDR is a function of the oxide step- height differential and the resolution of the output circuitry. For example, it has been reported that as few as 1000 electrons may be detected [IO] in which case the UDR for this structure would be 80 dB.) According to the above theory, the non- linearity should be zero over this range but in practice it is likely to be nonzero due to charge slopping.

If we now consider applying a similar technique and analysis to a single-level oxide device, as shown in Fig. 2 , then the equa-

HAKEN: SUPPLY CHARGE ISOLATION 261

under G, pocnt at which equatlon 12 is no longer mlid

A 8 1 / \? left under G2

I / \ D. C. offset between G, 8 G2 = 5 V

V I 1 \ I 0 I 2 3 L 5 6 7

Fig. 5. Theoretical values of Q s max, Qs,,,, and Qs,,,,, versus input signal amplitude for a typical single-level oxide CCD structure.

Input slgnal unplltude In volts

tions for determining Qs max, and Qstrans become

QS max = COX (VbZS - 4SG3) - 2 4 ~ ~ 3 cDG3 (10)

QSleft = COX (VbZR - 4SG3) - 2 $ 3 ~ 3 CDG3 (1 1)

Qstrans = COX ( V G ~ - VGZR) (12)

where Vb2s equals Vb on the second gate at the point at which transfer starts, q5sG3 is the surface potential under the third gate, C D G ~ is the depletion capacitance under the third gate, and VbZR equals V& on the second gate when its gate voltage is at the resting value.

The theoretical values of Qs max, Qsleft and versus the gate voltage on G3 are plotted in Fig. 5 . These values cor- respond to a device with the same physical parameters as those used in Fig. 4, except that a single level of oxide 0.18 pm thick is used and the dc offset applied between gates G1 and G2 is 5 V.

From Fig. 5 it may be observed that the maximum charge stored under G2 just before transfer starts is almost indepen- dent of the gate voltage on G3. This results from the fact that a single level of oxide is used, which tends to make the surface potential differential between gates one and two virtually inde- pendent of the clock voltage. This is in contrast to the two- phase stepped oxide device considered previously. It is ex- pected therefore that charge slopping in the single-level oxide structure will be less than in the stepped-oxide device because no charge will be pushed out of the G2 potential well as the clock is turned off. The amount of charge transferred, as in the case of the two-phase device, is a linear function of the amplitude of the signal on the input gate until the point is reached where the gate voltage on G3 is equal to the resting potential plus dc offset voltage on G2. At this point (12) is no longer valid and the amount of charge transferred is given by (10). It is possible to increase the maximum amount of charge injected into the CCD by simply increasing the dc offset volt- age between gates one and two, up to a limit determined by the amplitude of the clock voltages used.

QHAxunder 0,’

I I

0 1 2 3 L 5 6 7 8 In@ slgnol omplltude In volts

Fig. 6 . Measured values of Qstrans versus input signal amplitude for two different two-phase stepped oxide CCD structures.

IV. EXPERIMENTAL RESULTS In order to confirm the theoretically predicted properties of

the proposed charge injection technique, experiments have been performed on several different two-phase, stepped-oxide CCD’s fabricated by a self-aligned gap technique using the oblique deposition of aluminium (8). The first “bit” of these devices was used for the two gates required to perform charge injection. 4; was connected to the clock line and Q2 to a dc bias whose value was midway between the extremes of G1. Reset sensing was performed using the $1 clock, as described in a previous paper [ 11 ] .

The dependence of the quantity of charge injected into the CCD on the amplitude of the signal on 4; for two different two-phase structures is shown in Fig. 6. Curve (a) is for a 40- bit device with electrode dimensions of I 2 pm X 200 pm (ths device has the same physical parameters as the theoretical two- phase structure considered in the last section) and curve (b) is for a 25-bit device having electrode dimensions of 20 pm and 200 pm; in both cases the clock amplitude used was 20 V. From the curves it is evident that for a signal swing of approxi- mately 6 V the relationship is basically linear. When the signal amplitude on 4; exceeds approximately 6 V the relationship, as theory predicts, becomes nonlinear. The above theoretical analysis does not predict, however, the nonlinear effect at the lower end of the characteristics. This nonlinearity is attributed to charge slopping, becoming more prominent at low signal levels because the ratio of slopped charge to signal charge is greater.

Charge slopping is likely to occur because when is turned off some of the excess charge under 4; may not have sufficient time to return to the input diffusion before the 4; well be- comes more attractive. For all the devices investigated it was found that charge slopping was only slightly affected by varia- tions in the fall time of the G1 clock for times greater than ap- proximately 15 ns; for faster fall times an increase in the non- linearity of the transfer characteristics resulted. It was also found that the quantity of slopped charge was virtually inde- pendent of the reverse bias applied to the input diffusion, providing the value of this bias lay in between the two ex-

262 IEEE TRANSACTIONS ON ELECTRON DEVICES, FEBRUARY 1916

tremes of the surface potential experienced under the thick oxide of q5;.

In order to characterize the linearity of the charge-injection technique, measurements of harmonic distortion have been made as a function of both the input signal amplitude arld the dc bias level on the input gate. (These measurements were made in a similar manner as described in [I21 .) In the latter case the input signal was kept constant at one-half the rnaxi- mum value, this value being determined from the trmsfer characteristic of the device, did the dc bias varied to cover the full input range. The two sets of measurements allow deter- mination of the maximum signal amplitude that may be ap- plied to the input before an unacceptable level of haranonic distortion occurs, and the nonlinearity of the injection -tech- nique at different operating points on the transfer charac feris- tic. In order to make these measurements a sinusoidal signal of 10 kHz was applied to the input gate after being filtered to ensure spectral purity, all harmonic components were at least 65 dB below the fundamental, and the devices operat1:d at 1 MHz.

It has been established in [ 121 that for potential equi,ibra- tion charge-injection techniques (the technique consider :d in this paper being of that type) the harmonic distortion Intro- duced by sampling effects can be ignored providing the signal frequency is small compared with the Nyquist limit (halF the clock frequency), as is the case above, and the sampling pmiod is of the order of 1 ps or less. Furthermore, the effects of transfer inefficiency on harmonic generation are insignif cant for signal frequencies low compared with the Nyquist limit (providing the transfer inefficiency is small enough to h: ap- proximated to a fixed fraction of the signal charge [ 131 ) this is because a linear smearing of the signal occurs which does not contribute towards harmonic generation.

It is possible, therefore, by first characterizing the linetrity of the on-chip amplifier, to determine the nonlinearities intro- duced by the charge-injection technique. In the case of' the on-chip amplifiers used at the output of the CCD's consickred, it was found that all second harmonic components were :ypi- cally at least 55 dB below the fundamental and consequently all the second harmonic measurements shown in Fig. 7(a) and (b) are actually k0.17 percent. (Higher harmonic components due to the on-chip amplifiers were typically at least 10-lfi dB below the second, and their effect on the harmonic distortion measurements can be ignored.) All harmonic distortion mea- surements were made using a narrow-band wave analyzer (HP model 3 1 OA) and performed on devices similar to the structure whose transfer characteristic is represented by curve (,a) in Fig. 6 .

In order to measure the harmonic distortion as a functio -I of the input signal amplitude the dc bias on the input gate was adjusted such that its value corresponded to the middle of the linear section of the transfer characteristic of the device, ap- proximately 10.5 V. The input signal was then superimpclsed on this bias and its amplitude increased until eventually sat .ma- tion occurred, approximately 5.5 V pp, corresponding to a lxge increase in the harmonic components. The results for the P ~ C -

ond, third, and fourth harmonics are shown in Fig. 7(a); higher harmonics than the fourth are not shown because these 'awe

I I I I I 0 I 2 3 L 5

I n p u t srgnal amplitude in volts

(a)

0,C. bios-level on input gate in vdts

(b 1 Fig. 7. Measurements of harmonic distortion for a typical two-phase

stepped-oxide CCD with electrode dimensions of 12 pm X 200 pm. (a) Harmonic distortion versus input signal amplitude. (b) Harmonic distortion versus bias level on the input gate.

typically 15 dB lower. From the figure it may be observed that for an input signal amplitude of 3 V pp or less, all the har- monic components are at least 45 dB below the fundamental, with a total harmonic distortion of less than 1.2 percent. As- suming the same output-diode capacitance and minimum- detectable charge packet as used in the last section, then for a 3 V pp input signal the device has a UDR of 47.5 dB. If the input signal amplitude is increased to 5.3 V pp, then all har-

HAKEN: SUPPLY CHARGE ISOLATION 263

potential difference between two gates, although in the tech- nique described here the actual signal package is constituted by the skimmed-off part of the isolated charge packet, in Tompsett’s technique it is formed by the “trapped” part of the packet. A further difference between the two techniques is that the one presented here uses directional input gates to iso- late charge from the input diode, thus obviating the need for an input-diode clock. Signal charge isolation in Tompsett’s technique is achieved by using two nondirectional electrodes in conjunction with an input-diode clock. The absence of an in- put clock is particularly advantageous in two-phase operation as it means that the whole system can be operated with just one clock. However, because the @; electrode is clocked, any noise on the pulse generator will appear in the signal packet, a problem not experienced with the reversed potential equilibra- tion method [ 141 . As might be expected, the linearity of the

Fig. 8. Linear ramp (upper trace) of 2.5 kHz delayed by 40 p s using a two different potential equilibration injection techniques is

The high linearity of the charge-injection technique described in this paper is illustrated in Fig. 8, which shows a linear ramp

40-bit two-phase device operated at 1 MHz. Vertical scale: 1 V/div. Horizontal scale: 22 ps/div.

Fig. 9. Analog signal processing application of two-phase CCD’s using a single clock. Upper trace: Input signal to first CCD (vertical scale 5 V/div, horizontal scale 0.3 ms/div). Middle trace: Output signal from first CCD (vertical scale 0.5 V/div, horizontal scale 7 ps/div). Lower trace: Output signal from second CCD (vertical scale 0.5 V/div, horizontal scale 0.3 ms/div).

monic components are 40 dB below the fundamental; the total harmonic distortion is approximately 2.3 percent and the U D R is 52 dB.

Measurements of harmonic distortion as a function of the level of dc bias on the input gate were made using a signal amplitude of 2.5 V pp. From Fig. 7(b) it is evident that over the bias range of 9.2-10.8 V the harmonic components are at least 48 dB below the fundamental with a total harmonic dis- tortion of less than 0.9 percent. Over the range of 8.2-1 1.2 V the harmonic components are 45 dB below the fundamental and the total harmonic distortion is approximately 1.3 percent.

At this stage it is interesting to compare the injection tech- nique presented here with a similar potential equilibration method described by Tompsett [ 6 ] . In both methods the quantity of charge transferred is directly proportional to the

of 2.5 kHz delayed by 40 p s using a 40-bit device operated at 1 MHz.

In order to demonstrate how simply a two-phase CCD can be operated when used in conjunction with this charge- injection technique, a typical CCD analog signal processing ap- plication is shown in Fig. 9 1151 . In this application two 40- bit two-phase C C D s have been connected up in cascade, both being operated by a single clock, the first of which has a signal clocked into it at 14 kHz (upper trace). When the first CCD is full of information the incoming signal is gated and the infor- mation clocked out of the device at 1 MHz (middle trace). The compressed information is applied to the input gate of the sec- ond CCD and subsequently clocked into the device at 1 MHz. When this device is full, corresponding to the first CCD being empty, the clock frequency is changed to 14 kHz and the in- formation clocked out (lower trace). This signal is then a replica of what was fed into the first device but having under- gone compression and expansion in time.

This signal processing application clearly demonstrates how simply two-phase C C D s may be operated using just one clock. The single clock is used 1) for providing linear charge injection, 2) charge shifting, and 3) reset charge sensing. For systems operation this technique has significant advantages over others described hitherto.

V. CONCLUSIONS A high-linearity charge-injection technique of the potential

equilibration type that does not require the generation of an input clock has been described and analyzed. The technique is particularly well suited to two-phase CCD’s as it allows linear charge injection, charge transfer, and detection to be accom- plished using just one clock. The technique can also be used in conjunction with other stepped-oxide CCD structures or de- vices that use only a single level of oxide, for example three- phase CCD’s.

Experimental results obtained using different two-phase CCD structures have shown that the theoretically predicted high linearity of the technique is realized in practice. However,

2 64 IEEE TRANSACTIONS ON ELECTRON DEVICES, FEBRUARY 1976

small nonlinearities, mainly attributed to charge slopping, have been found to occur, being most prominent at the lower and of the transfer characteristic. These nonlinearities have the effect of reducing the UDR of the device for a particular level of distortion. Experiments have indicated that with a ty.>ical output diode capacitance of 0.5 pF and a minimum detecl able charge packet size of 0.5 X C, a UDR of 47.5 dB is at- tainable using a signal swing of 3 V pp, with all harmonic (:om- ponents at least 45 dB below the fundamental and a iota1 harmonic distortion of less that 1.2 percent k 0.17 percent. If the signal amplitude is increased to 5.3 Vpp, then all harmonics are 40 dB below the fundamental, the total harmonic dlistor- tion is 2.3 percent rt 0.17 percent, and the UDR of the dwice is 52 dB.

ACKNOWLEDGMENT The author wishes to express his appreciation to Dr. C ; ~ G.

Bloodworth,Dr. J. D. E. Beynon, and Dr. D. R. Lamb for their comments on the manuscript, and to Dr. P. C. T. Robert:; and C. P. Trayner for helpful discussions.

REFERENCES [ 11 M. F. Tompsett, G. F. Amelio, and G . E. Smith, “Charge-coupled

8-bit shift register,” Appl. Phys. Lett., vol. 17, pp. 111 -115, Aug. 1970.

[2] W. F. Kosonocky and J. E. Carnes, “Chargecoupled digital cir- cuits,” IEEE J. Solid-state Circuits (Special Issue on Semicon- ductor Memories and Digital Circuits), vol. SC-6, pp. 314-322, Oct. 1971.

[3] M. F. Tompsett and E. J . Zimany, “The use of charge-codpled devices for delaying analog signals,” IEEE J. Solid-state C i w i t s (Special Issue on Charge Transfer Device Applications), vol. SC-8, pp. 151-157, Apr. 1973.

[4] H. Wallinga, “A comparison of CCD analogue input circuit char- acteristics,” in Proc. CCD Technology and Applications Con$, Edinburgh University, Edinburgh, Scotland, Sept. 1974, pp.

[5] S. P. Emmons and D. D. Buss, “Noise measurements on the floating diffusion input for charge-coupled devices,” J. Appl .

[ 6 ] M. F. Tompsett, “Surface potential equilibration method of set- ting charge in charge-coupled devices,” IEEE Trans. Electrcn De- vices, vol. ED-22, pp. 305-309, June 1975.

13-21.

Phys., V O ~ . 45, pp. 5305-5306, 1974.

[91

R. H. Krambeck, R. H. Walden, and K. A. Pickar, “A doped sur-

Oct. 1972. face two-phase CCD,” Bell Syst. Tech J . , vol. 5 1, pp. 1849-1866,

R. A. Haken, J. D. E. Beynon, I. M. Baker, and P. C. T. Roberts,

IEEE Trans. Electron Devices, vol. ED-22, pp. 289-293, May “Chargecoupled structures with self-aligned submircon gaps,”

1975. G. F. Amelio, W. J. Bertram, and M. R. Tompsett, “Charge- coupled imaging devices: Design considerations,” IEEE Trans. Electron Devices (Special Issue on Image-Sensing Devices), vol.

arrays,’’ in h o c . CCD Technology and Applications Conf., Edin- G. F. Amelio, “The impact of large CCD image sensing area

burgh University, Edinburgh, Scotland, Sept. 1974, pp. 133-152. R. A. Haken, I. M. Baker, and J. D. E. Beynon, “A simple driving and frequency characterization technique for two-phase charge- coupled devices”, IEEE J. Solid-state Circuits (Corresp.), vol.

C. H. SBquin and A. M. Mohsen, “Linearity of electrical charge injection into charge-coupled devices,” IEEE J. Solid-state Cir- cuits, vol. SC-10, pp. 81-91, Apr. 1975. W. B. Joyce and W. J. Bertram, “Linearized dispersion relation and Green’s function for discrete charge transfer devices with in- complete transfer,” Bell Syst. Tech. J., vol. 50, pp. 1741-1759,

A. M. Mohsen, M. F. Tompsett, and C. H. Sequin, “Noise mea- surements in charge-coupled devices,” IEEE Trans. Electron De- vices, vol. ED-22, pp. 209-218, May 1975. G. G. Bloodworth and C. P. Traynar, “Application of charge- coupled devices to the compression and expansion of audio sig- nals in a T.V. transmission system,” Microelectronics J., vol. I, Dec. 1975.

ED-18, pp. 986-992, NOV. 1971.

SC-9, pp. 199-203, Aug. 1974.

July-Aug. 1971.

Roger A. Haken was born in Purley, Surrey, En- gland, on April 27, 1950. He received the Higher National Diploma in electrical and elec- tronic engineering from Southampton College of Technology, Southhampton, England, in 1971, and the M.Sc. degree in electronics from the University of Southampton, Southampton, England, in 1972.

He has recently concluded his Ph.D. studies at Southampton University and submitted his dissertation on the technology and operation

of surface and bulk channel CCD’s. He is currently a Design Engineer with Fairchild Semiconductor, Bristol, England where he is engaged in the design of CMOS LSI circuits.