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Summer 2000 Yield Management Solutions 3

S U M M E R 2 0 0 0

S e c t i o n s

4 Editorial: The Shrinking Lithography Window

7 Business NewsStrategic Acquisitions Expand Litho PMC

25 KLA-Tencor Trade Show Calendar

37 Q & AAn interview with KLA-Tencor’s Senior Director of Marketing,Worldwide Support Operations on the iSupport Program.

59 Yield Management Seminar Series

P r o d u c t N e w s

78 iSupportFast, Comprehensive, On-line Customer Support Program

AIT IIIHigh-Speed, High-SensitivityDarkfield Patterned WaferInspection System

79 8250 and 8450Fully Automated CD SEMSystem

eS20XPHigh-Speed, In-Line E-beamInspection System

Yield Management Solutions ispublished by KLA-Tencor

Corporation. To receive YieldManagement Solutions contactCorporate Communications at:

KLA-Tencor Corporation160 Rio Robles

San Jose, CA 95134Tel 408.875.4200Fax 408.875.4144www.kla-tencor.com

For literature requests call:800.450.5308

©2000 KLA-Tencor Corporation. All rights reserved. Material may not be

reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective

companies or organizations.

55 748

50 Matching Automated CD SEMS in Multiple ManufacturingEnvironmentsThe ultimate technical performance of CD SEMs is dependent onconsistent and tight operational controls, especially in multiple manu-facturing environments where system matching is required. Matchingand repeatability of CD SEMS can be evaluated using a standarddaily monitor wafer.

55 Improving Process Control for 0.18 µm Technology and BeyondAs the industry moves to 0.18 µm manufacturing and beyond, CDmeasurements alone are not providing enough information about theprinted structures. An improved method uses information already col-lected by a CD SEM to automatically compare the stored imageand linescan information of a correctly processed structure to that ofthe structure being measured.

60 Optimizing Yield by Detecting Lithography and Etch CD ProcessExcursionsThere are many different yield-limiting excursion signatures in photoand etch, and a given excursion signature at photo may turn into adifferent excursion signature at etch with a different impact on yieldand performance. Many current sampling plans and monitoringschemes miss these excursions. An improved procedure for effectivedetection of CD process excursions can have a significant impacton yield and revenue.

65 Run-to-Run Control of Photolithography ProcessesBecause the device fabrication process is extremely sensitive to keyphotolithography parameters, the benefits of superior process controlare significant. Run-to-run (R2R) is rapidly becoming a key processcontrol tool in the semiconductor industry.

Process Parametric Control

74 Analysis of Phosphorous Auto-doping in P-type Silicon Measuredusing Corona Oxide Silicon TechniquesCross contamination of P-type silicon to N-type carriers or vice versain the near surface region of the silicon can be detrimental to device performance. In-line monitoring of these near-surface doping effectsenhances the ability to diagnose auto-doping problems.

Summer 2000 Yield Management Solutions4

EditorialS E C T I O N S

Photolithographers know more about the lithographyprocess than ever before. This knowledge is essen-tial because the process is more challenging thanever before. With device performance competitionpushing designs smaller, all aspects of the processwindow are squeezed more tightly. The job ofthe lithography engineer is to integrate eachcomponent of the system, minimizing itscontribution to linewidth and overlay errorand defectivity, while simultaneously controlling costs. This month’s issue ofYield ManagementSolutions examinesmethods for under-standing, optimizing,and controlling thelithography system.

The contribution of each compo-nent should not be consideredindividually, but rather as a partof the whole lithography system.The optimization and controlstrategy encompasses design formanufacturing, quantification of sources of variation from thestepper, resist system, reticle, and track, and howthey interact with each other.

KLA-Tencor has worked with several fabs to quan-tify the components of CD variance and helped toprioritize and improve the overall error; this isdescribed in the paper “Optimizing Yield By DetectingLithography and Etch CD Process Excursions” co-authoredby AMD and KLA-Tencor. The two companies also

The Shrinking Lithography Process Window

collaborated on “Improving Process Control for 0.18 µmTechnology and Beyond,” which describes the use ofthe 8100XP CD SEM’s capability to control thepatterning process by measuring more than CDerror with pQC (pattern quality confirmation).

Metrology also contributes to the totalCD budget; KLA-Tencor worked withMotorola APRDL on“Matching AutomatedCD SEMs in MultipleManufacturingEnvironments” toidentify and mini-

mize the measurementcontribution within a

company’s virtual factory.Working with NEC Scotland,

KLA-Tencor used the 2401macro defect inspection sys-tem to control aspects of thestepper which also contribute

to CD error in a manufacturingenvironment. Each of these papers

describes methods which are valuable in designingmanufacturing processes for shrinking budgets.

The NEC work also examined litho process defec-tivity. Current resist, application, and develop systems must work within tighter tolerances; inaddition to linewidth errors, failures often resultin defect mechanisms. The work done by NEC

Inspectionand

Metrology

Modeland

Control

Stepper

Reticle

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ResistSystem

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Metrology

Modeland

Control

Stepper

Reticle

Track

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Defect

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S O L U T I O N SYield Management

CORPORATE HEADQUARTERSKLA-Tencor Corporation160 Rio RoblesSan Jose, California 95134408.875.3000

INTERNATIONAL OFFICESKLA-Tencor France SARLEvry Cedex, France011 33 16 936 6969

KLA-Tencor GmbHMunich, Germany011 49 89 8902 170

KLA-Tencor (Israel) CorporationMigdal Ha’Emek, Israel011 972 6 6449449

KLA-Tencor Japan Ltd.Yokohama, Japan011 81 45 335 8200

KLA-Tencor Korea Inc.Seoul, Korea011 822 41 50552

KLA-Tencor (Malaysia) Sdn. Bhd.Johor Bahru, Malaysia011 607 557 1946

KLA-Tencor (Singapore) Pte. Ltd.Singapore011 65 782 6788

KLA-Tencor Taiwan BranchHsinchu, Taiwan011 886 35 335163

KLA-Tencor LimitedWokingham, United Kingdom011 44 118 936 5700

EDITOR-IN-CHIEFKern Beare

MANAGING EDITORJudy Dale

CONTRIBUTING EDITORSCarol Johnson Uma SubramaniamDavid Viera

ART DIRECTOR AND

PRODUCTION MANAGERCarlos Hueso

DESIGN CONSULTANTHarry Wichmann

CIRCULATION ANDASSOCIATE EDITORCathy Correia

KLA-Tencor Worldwide

Scott Ashkenaz

Vice President, Lithography Module Solutions

Yield ManagementS O L U T I O N S

illustrated the opportunity in better controlling litho defectivity. “LithographyDefects: Reducing and Managing Yield Killers through Photo Cell Monitoring”describes a strategy for quantifying litho defectivity and applying focusedimprovement through pareto analysis. It focuses on the defect generationprocess, and represents work which has been successfully implemented in manufacturing at numerous fabs worldwide.

As process tolerances shrink faster than individual variation sources can beimproved, it becomes necessary to actively control the process. “Run-to-RunControl of Photolithography Processes” describes how fabs apply Advanced ProcessControl (APC). Using KLA-Tencor’s recently acquired Control Solutions Division’sCatalyst product, fabs apply APC to tighten CD and overlay performance.

Cost management is also a very important consideration of advanced lithographyand control. APC can have significant cost benefit, as can careful application ofmanagement strategies. “Enhancing Overlay Metrology Productivity and StabilityUsing an Off-line Recipe Database Manager” describes how overlay productivitywas improved at Texas Instruments’ DMOS 5 fab. At the same time, RDMalso helped to improve consistency of performance across multiple measurementtools of multiple generations. This increased utilization, and reduced the vari-ance contribution from multiple measurement systems.

Lithography process budgets require careful attention to CD and overlay controlstrategies, and to defect management and reduction. Escalating costs in thelitho area also require similar attention. We hope that this issue of YieldManagement Solutions can help in devising improved lithography strategies.

Be sure to get a copy of our reticle supplement scheduled for this fall, which willcontain articles addressing issues in reticle and quality photomask control andoptimization.

circle RS#046

ALREADY THERE.

©2000 KLA-Tencor Corporation

At 0.13µ, the old rules no longer apply. In their place, new

complexities are emerging. Including high NA lithography.

Copper/low-k interconnect. And the 300mm wafer. That’s

why we’re already charting a course for the 0.13µ transition -

continuously developing, testing and refining new tools and

yield management methodologies that will help you get

there. Our process module control solutions combine defect

reduction, process parametric control and yield management

software systems that are optimized for each process module -

films, litho, etch and CMP. And while the volume of process

information continues to grow, our analysis software quickly

reduces it to yield-relevant, actionable data. So you can make

better decisions, quicker. Improve yield. And reduce time

to market. To be sure, the transition to 0.13µ may not always

be smooth sailing. But with our help you can be certain of

reaching your destination. For more information, please call us

at 1-800-450-5308, or visit us online at www.kla-tencor.com.

IT WILL EITHER BE ROUGH WATERS OR SMOOTH SAILING.

HOW WILL YOU NAVIGATE THE MOVE TO 0.13µ?


S E C T I O N S

Despite advances in lithography, chip-makers are stretching technology limitsas they migrate to 0.13 µm and smallergeometries. Deep sub-wavelength lith-ography — a process that alters thepattern on the reticle to enable theprinting of design rules at least 30 per-cent smaller than the wavelength oflight used in the imaging process — isbeing considered as a necessaryapproach to successfully transition tothe 0.13 µm node.

When utilizing deep sub-wavelengthlithography at these geometries, thelithography process window becomesso narrow that chipmakers must haveunprecedented lithography processcontrol, in addition to the right tools,to maintain high yields. KLA-Tencor’sLithography Process Module ControlSolution (Litho PMC™) addresses thefour critical components that drive thesuccessful implementation of advancedlithography — critical dimension (CD)control, overlay accuracy, defectreduction and simulation/modeling.

KLA-Tencor made several strategicacquisitions that brought new analysis,modeling and advanced process con-trol (APC) capabilities to Litho PMC,augmenting its performance. Thesecapabilities, combined with the defectreduction and parametric process con-trol components that comprise LithoPMC, provide chipmakers with theyield management strategies and lith-ography process control needed tonavigate the transition to 0.13 µm.

Fab SolutionsAs a result of its acquisition of FabSolutions in March 2000, KLA-Tencorgained new APC capabilities, includ-ing Catalyst APC software. Catalyst

STRATEGIC ACQUISITIONSEXPAND LITHO PMC

provides a scalable open architecturethat supports fab-wide, run-to-runprocess control and fault detection.This capability allows engineers to effi-ciently deploy feed-forward and feed-back process controls in all keyprocess areas with a single integratedsoftware solution.

When integrated into KLA-Tencor’sPMC-Net™ yield information network— a critical component of Litho PMC— Catalyst enables the correlation ofreal-time, in-situ data from a givenprocess tool with in-line defect, metrol-ogy, work in progress (WIP) and end-of-line wafer sort data alreadyobtained by PMC-Net. The result isvastly improved identification of thekey process parameters that adverselyaffect yield, or which can be tuned toincrease device value.

FINLE TechnologiesKLA-Tencor’s acquisition of FINLETechnologies in February 2000 alsoadded new capabilities to Litho PMC.FINLE’s PROLITH Toolkit of simulationsoftware helps chipmakers reducelithography development time andcosts by reducing the number of exper-imental wafer runs required to validatea new process. When researchinglithography process window issues,PROLITH can be used to narrow thescope of the search and determine thecriticality of the process parameters tobe investigated. PROLITH can alsospeed new process development bysimulating the performance of new orunavailable materials or equipment.

Combining FINLE’s software withsome of KLA-Tencor’s inspection andmetrology tools has resulted in thedevelopment of KLARITY ProData, a

BBuussiinneessss NNeewwss

software tool that standardizes andautomates experimental lithographydata analysis. Using this technology,customers can speed the insertion ofnew lithography processes into theirproduction line.

ACMEKLA-Tencor further augmented the per-formance of Litho PMC through itsacquisition of ACME Systems inNovember 1999. With the capabili-ties gained from ACME, a softwaredeveloper specializing in yield engi-neering analysis software used to cor-relate parametric electrical test andwafer sort yield data with in-line data,KLA-Tencor developed the Klarity ACEsoftware module. Klarity ACE pro-vides low yielding lot, split lot andwafer yield spatial analysis when integrated into PMC-Net. This enablesusers to clearly identify relationshipsbetween in-line data, such as gateCDs, and test data, such as speed bin,to more rapidly identify and resolveprocess problems that impact deviceyield, performance and reliability.

SummaryKLA-Tencor is continuing to strengthenits technology portfolio through a com-bination of new product introductions,in-house research and development,and strategic acquisitions. With thenew capabilities acquired from FabSolutions, FINLE Technologies andACME Systems, combined with KLA-Tencor’s leading inspection andmetrology tools, customers can nowemploy a complete lithographyprocess control solution to optimizethe critical areas of lithographic con-trol, and help them successfully transi-tion to the 0.13 µm node.


Defect Reduction

The Advantages of In-line Electron-Beam Wafer Inspection

by Rob Cappel and Jay Rathert, KLA-Tencor Corporation

Electron-beam (e-beam) wafer inspection is emerging from its well-established place in the research and development laboratory and is moving onto the production floor. Changes in both semiconductor technology and economics are driving thisexpansion, taking advantage of the unique strength of e-beam inspection, and making its use more routine.

The pace of change within the semiconductorindustry is unrivaled. The SemiconductorIndustry Association road map, the forecastof technology trends for the industry, hasbeen reviewed and updated annually for thelast three years. Each revision has acceleratedthe design rule milestones that indicate theindustry’s technological progress. Historically,the industry has paused at each of thesemilestones to reap the production benefitsof its R&D work before leaping to the next node. This is no longer the case, as theeconomics of the “first mover” advantagecreate a continuing push to ever-smallerdesign rules. The period between nodes hasbeen reduced to less than two years, andhas brought the predicted arrival date forthe 100 nm node, once forecast to appear in2009, in by more than six years.

The difficulty for fab development andintegration engineers tasked with keepingpace with shrinking design rules and theconcomitant changes in acceptable processvariations, has been compounded by theemergence of new processes and materialsin the quest for faster, smaller, low powerdevices. These new materials, includinglow-k dielectrics and deep ultra-violetresists, add uncertainty to the processdevelopment phase, bringing new issues,interactions, and defect types. Furthermore,the rapidly emerging copper dual damascene

process is replacing 30 years of aluminum-based expe-rience, while simultaneously introducing new issues,such as high aspect ratio structures and copper inter-connect fill. Despite these challenges, chip manufacturersare striving to complete development more quickly,and transfer to production ramp at increasingly higheryields. Once on the production floor, their goal is todrive out systematic failures, learn as quickly as possi-ble, and rapidly attain high yields, while keeping toolutilization efficient and capital costs down.

Industry dynamics require new defectdetection solutionsIn the face of these economic and technology pressures,defectivity management is more critical today thanever before. To effectively accelerate the developmentand ramp phases, the engineering team must be able todetect and characterize all defect types, regardless ofsize, location, or material. The current difficulty induplicating historically high aluminum yield levels inthe new copper processes indicates that the scope ofdefects that should be considered critical is actuallyexpanding. Dual damascene processing, critical for copperdevices, changes the requirements for defect inspection.While the detection of many surface defects remainsimportant, the emphasis on yield-limiting defectschanges from surface defects to defects at the interfaces,such as residues and particles within the trenches, andvoids within the copper fill. Current automated opticalimaging and light-scattering inspection technologieshave limited success detecting physical defects withinhigh aspect ratio structures and cannot detect electrical

F E A T U R E S


inspection system, and appears at first glance to be a“nuisance” defect. However, review on a a tilting reviewSEM revealed that this “nuisance” defect was actually asmall micro bridge and almost certainly a killer defect.

Detection of defects in high aspect ratio structuresAs the number of device metal layers grows, qualitycontrol of interconnect layer issues will have an increas-ing effect on yield, and the bottom line. Moreover, thedetection of partial defects within these high aspectratio structures is critical since they can impact thereliability and performance of the device as well as leadto fatal defects during the plug fill process. Figure 3shows a top view, high-resolution image of a small par-ticle at the bottom of a via. The e-beam inspector’slarge depth of focus enables the detection of particles,residues, coring, and scumming well beyond the limitsof optical detection. It is important to note that thisdefect would not be detected using the voltage contrastcapability of a typical e-beam inspection system, as thedefect does not completely block the via.

Detection of voids and electrical defectsThe electron-beam inspector’s most unique feature, the voltage contrast effect, is illustrated in Figure 4.Electrically isolated structures charge differently in thepresence of an electron beam than the grounded refer-ence structure to which they are compared. The charge

F E A T U R E S

Figure 3. Top view of a small particle at the bottom of a via.

Detecting this kind of defect is made possible only by the e-beam

inspection system’s high depth of focus.

changes the number of electrons collected from the iso-lated area relative to grounded area. This difference isdetected by the image computer, and indicates a likelyfault. In this example, the under-etched via isolates thestructure from ground, and results in a localized charg-ing that differs from the reference image. Typically,this difference is quite large, resulting in a clear signalof a problem. Because these defects are electrical innature, they tend to have a very high correlation toyield. In the absence of e-beam inspection, there arefew viable methods to detect defects of this nature.Customers trying to detect these problems without e-beam inspection technology might wait until finalprobe six to eight weeks later, leaving many weeks ofmaterial at risk. Alternatively, material could be ran-domly cross-sectioned and defects counted manually.This inevitably leads to delays and confidence issueswhen dealing with such a small ample. In this case, thee-beam inspector provides a real-time electrical testwith the capability to scan an entire wafer for systematicsignatures or random electrical failures.

E-beam inspection challengesThroughputThe primary concern with e-beam inspection has beenthe tradeoff of throughput for sensitivity. Previous gen-eration tools measured whole wafer inspections in termsof days. Advanced e-beam inspection systems are nowable to complete a whole wafer in a little more than onehour, making it ready for the fab floor. To effectivelymaximize throughput, an e-beam inspector needs a highbrightness gun and a low noise, high bandwidth collectionsystem. Additionally, the system’s image computer mustbe fast enough to perform real-time image alignment toa 1/10th pixel level to ensure success in die-to-die com-parisons. Thirdly, the system requires a scanning stagewith interferometer control to provide both sufficientimage acquisition speed, and real-time feed-forward andfeedback to the beam scanning system and stage to keep

Figure 4. The under-etched topography of the via creates localized

charging, causing the electron yield to increase, resulting in a clear

voltage contrast signal. E-beam inspection provides the only practical

method for detecting these defect types.

Figure 2. This sub-100 nm defect is from a Metal 1 layer, yet no

grain, color variation, or prior-level defects are discernible. The small

protrusion is a small micro bridge and almost certainly a killer defect.


Detection of yield signaturesIn one evaluation of a 0.18 µm design rule aluminumprocess contact wafer, the system was set up for a wholewafer using a small area on the die, representing about10 percent of the total die area. In this example, theinspection was focused on voltage contrast effects in anattempt to detect a known localized signature that wasoptically invisible. The inspection scan time for thiswhole-wafer test was only six minutes. The electricalsignature was clearly found and perfectly matched theyield loss signature seen at final probe. In addition, thesystem also found many additional random defects thatimpacted yield. As a result, this customer was able toquickly isolate the cause of the yield loss, implementan immediate fix, and set-up an inspection recipe thatcould be used to monitor the production line to pre-vent further occurrences of this problem.

Isolation of in-line yield problemsIn another example of good yield correlation, the e-beaminspector was challenged with finding a group of yieldsignatures that had been previously defined at probe:primarily missing vias, blocked vias, or partially blockedvias. The inspector was run at a high sensitivity toaccentuate both voltage contrast defect detection as well as small physical defects. All of the signatureswere replicated by the e-beam inspector, including thesubtle, partially blocked vias (Figure 6). Again, theinspection showed an extremely high correlation to

the beam constantly on its intended target. Finally, thesystem must have advanced image-processing algorithmsthat are able to keep pace with the hardware whileresolving subtle defects and rejecting nuisance and false defects.

Charge control The second significant challenge for e-beam inspectionsystems is charge control, which is the ability of thesystem to compensate for material interactions with theelectron beam. Without good charge control, the surfaceof the material being inspected could develop a positiveor negative charge, resulting in image distortions,darkened images, or unwanted beam deflections. Randomdie-to-die inspection is particularly sensitive to thisphenomenon, as the pair of die images under compari-son must be relatively uniform, with evenly distributedgray levels and no charging artifacts to avoid false defects.Figure 5 presents a charge-sensitive oxide layer withoutcharge control to illustrate these effects. KLA-Tencor’spropietary charge-control techniques largely eliminatecharge-related issues. Charging artifacts can be seen asdarkening and “comet tails” on the image.

Yield correlation using e-beam inspectionCustomer demonstrations of the eS20 on product waferhave clearly indicated a high correlation between thedefects found and e-test results.

F E A T U R E S

Figure 5. The importance of good charge control for random die-to-die

inspection. For die-to-die inspection to work properly the images must

be uniform with no charging artifacts. Here the image does not have

adequate charge control. Random mode inspection would be impossi-

ble; false defects due to variation would be detected.

Figure 6. Customer data from a KLA-Tencor eS20 demo at 0.1 µm

pixel, demonstrating detection of yield signatures previously found only

at probe.

Blocked vias Partially blocked vias

Partially blocked viasDark images, uneven gray levels and charging artifacts


yield (less than 90 percent) and allowed the customerto isolate a yield problem within the line, instead ofhaving to rely on end-of-the-line electrical testing followed by a lengthy and sometimes unproductivefailure analysis process.

Tungsten plug fill issues in Cu dual damasceneThe e-beam inspector has also demonstrated repeatedlythat the value in finding fill issues in tungsten plugs isreplicated in copper dual damascene. The system hasdetected sub-surface killer voids as far as three metallayers back that presented no surface indication of fail-ure when using optical inspection methods. Since thenumber of layers requiring high aspect ratio etch, cop-per fill and CMP polish is growing, e-beam inspectionremains the only practical and reliable way of findingand eliminating these issues.

Optimizing e-beam and optical inspection strategiesThe benefits of e-beam inspection are clear, but mostfabs are accustomed to operating with an installed baseof optical inspection systems. These optical inspectorscurrently have a better cost of ownership and usually seemost defect types of interest. With the pressure to opti-mize capital expenditures, the optimum solution is tointegrate e-beam inspection systems with optical inspec-tion systems to gain the best data at the best cost. (Figure 7).

During the development phase of the product, the focusshould be on detecting all defect types, at the surfaceand below, visible, and sub-optical. While characteriz-ing the defects, the quality of the data is paramount,and the e-beam inspection system should be prioritized.Special emphasis should be given to the electrical layersthat can take advantage of the voltage contrast effect.

As the product moves into ramp, understanding ofmany of the layers will begin to mature. The defectivi-ty is better understood - the types are characterized andknown to be systematic or random. In this phase,inspection of well-characterized layers with opticallydiscernible defect types should move toward a lowercost of ownership (CoO) inspection system. The e-beamtool can be used synergistically with darkfield andbrightfield optical inspection systems to optimize theirrecipes to ensure they capture the critical defect types.Meanwhile, the e-beam inspector should continue to beused to get rapid DOE results for process changes, orto investigate any issues that arise from e-test, particu-larly on critical interconnect layers.

Finally, as the product moves into full production, andyields approach entitlement, the inspection strategyshould emphasize optical inspection for the best-costcontainment. The e-beam system should continue to beused in an audit mode to make sure that no new defecttypes are emerging. Any layers that are not indicatinggood yield correlation using the optical systems shouldbe moved back to the e-beam systems until they arewell understood.

SummaryNext generation processes are creating many chal-lenges. Electron beam inspection provides solutions tohelp engineering teams surmount these challenges bygiving them the means to detect unique defect typesimpossible to find by any other practical method:defects in high aspect ratio structures, hidden electricaldefects, and sub-optical physical defects. Historicalchallenges in throughput and charge control have beenminimized by new developments that dramaticallyaccentuate e-beam inspection’s value. Using the e-beaminspection system in conjunction with optical inspec-tors in a well-planned strategy can optimize both theCoO and the yield learning rate.

Figure 7. Balancing e-beam and optical inspection during the device

life cycle.

F E A T U R E S

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R&D Ramp Productioncircle RS#010


Defect ReductionF E A T U R E S

Surfscan SP1TBI vs. Surfscan 6420:a Performance Comparison

by Dale Guidoux, KLA-Tencor

As the semiconductor industry continues to shrink critical design rule dimensions, the need for increased performance fromlaser-based surface defect inspection tools has intensified. Prior to 0.25 µm geometries, unpatterned wafer inspection usesfocused primarily on Particle per Wafer Pass (PWP) measurements. KLA-Tencor’s Surfscan 6420 became an industrystandard, based on its particle sensitivity performance on rough films, particularly metal layers. With the implementationof 0.18 µm and 0.13 µm process nodes, there is a need to detect and classify more defect types than just particles. Theunique axi-symmetric collection optics and brightfield channels of the Surfscan SP1TBI, coupled with normal incident angleillumination and oblique angle illumination provide superior defect sensitivity and Real Time Defect Classification(RTDC). The tool can be used to differentiate crystal orginated particles or pits (COPs) from particles, classify EPI stack-ing faults, mounds and dimples, and detect CMP microscratches, chatter marks and slurry residue.

An additional benefit of the axi-symmetriccollection optics on the Surfscan SP1TBI isuniform detection of scratches, regardless oforientation. Systems that use non-symmetriccollectors can miss important defects such asslip lines and scratches in certain orientations.

An increasingly important issue in designrules less than 0.18 µm are the presence ofCOPs on silicon wafers. The Surfscan SP1TBI

is able to detect and classify these COPsseparately from surface particles by compar-ing the defect signal from the wide anglecollector with the narrow angle collectorsignal. Previous generations of Surfscanswere not able to differentiate COPs fromparticles. The ability to classify COPs hastwo advantages. First, certain device perfor-mance can be affected by the presence ofCOPs. IC manufacturers must add epitaxiallayers to overcome this problem. Secondly,when performing tool contamination moni-toring with test wafers, it is important tomeasure just the particles added during aprocess step, and the presence of COP defectsin the total count can give false indicationsof the actual particle trend.

Surface Nanotopography (SNT) is the newest productfeature on the Surfscan SP1TBI. It provides the abilityto measure surface features with nanometer height vari-ations across a lateral surface dimension in the 0.5 mmto 20 mm range. A primary application for this feature

P-Well

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Nitride

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CVD Oxide

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Figure 1. A small deviation in the underlying silicon topography can

lead to leakage or breakthrough, and ultimately device failure. Surface

height variations can also lead to depth of focus lithography problems

in advanced <0.18 µm processes.


F E A T U R E S

is to control non-uniform film thickness variation inshallow trench isolation (STI) CMP.

Even with all of the new defect classification capabilitieson the SP1, sensitivity to particles on rough films stillremains a primary requirement of unpatterned waferinspection tools, and the performance of the SurfscanSP1 is commensurate with the requirements of 0.13 µmprocesses. The graph in Figure 2 shows that the SP1

has superior sensitivity compared to theSurfscan 6420 for all examples tested. (Note:The sensitivities shown in Figure 2 areobtained from random customer samples.The performance can be better, depend-ing on the surface quality of the film.)The oblique angle incident illumination,coupled with S, P or Circular polarizationand the high efficiency ellipsoid collectorare key to optimizing sensitivity on roughfilms. This same collector is also effectiveat capturing surface haze data over a widespatial frequency range. Haze measure-ments have proven useful in monitoringfilm uniformity and surface roughness.

A case study comparing defect capture onthe Surfscan SP1TBI versus the Surfscan6420 on electro-chemical deposition (ECD)

copper was performed at a customer site. At equivalentthresholds of 0.25 µm, the SP1 captured more than twiceas many defects (Figure 3). The defects that weremissed by the Surfscan 6420 were reviewed on a CRSlaser confocal review station. The size of the additionaldefects captured by the Surfscan SP1TBI were not allclose to the detection threshold, but rather distributedacross a wide size spectrum as exhibited in Figure 4.

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Figure 2. SP1 sensitivity compared to 6420 on various films.

Figure 3. The Surfscan SP1TBI captured more than twice as many defects as the Surfscan 6420.

Surfscan SP1TBI

0.25 µm threshold(1938 defects)

Surfscan 64200.25 µm threshold

(754 defects)


correlation R2 value of 0.979 on a typical oxide layercompared to the Surfscan 6420 count. No changes weremade to the existing Surfscan 6420 recipe.

In summary, the Surfscan SP1TBI has better sensitivityand higher throughput (up to 125 wafers per hour), isable to capture a wider variety of defect types and per-form real time defect classification on many defect types.It has proven matching between tools and demonstratedcorrelation to the previous generation Surfscan 6420series. It has already achieved a large acceptance at allthe top IC, equipment and wafer manufacturers world-wide and has become identified as the tool of choice forboth 200 mm and 300 mm installations.

This means the SP1 captures more defects (and defecttypes) than the Surfscan 6420 at equivalent sensitivities.

Another defect type captured by the Surfscan SP1 usingthe brightfield channel are the “copper swirl” marks shownin Figure 5. As can be seen in the microview close-up,these swirl marks have significant topography contours.

When adopting new tool sets, it is always advantageousto be able to correlate existing baseline data sets withthe new tool data. Correlation studies performedbetween the SP1 and the 6420 show good correlationwith the existing 6420 installed base. For example, arecipe was created on the SP1TBI that exhibited a count

F E A T U R E S

Figure 4. Two types of defects that the Surfscan 6420 missed but the Surfscan SP1TBI captured easily: a 0.51 µm high spike and a 1.10 µm particle.

0.51 µm spike, 0302 µm LSE on SP1 1.10 µm particle

Figure 5. Copper swirl marks are another defect type detected using the brighfield channel of the Surfscan SP1TBI.

5A: Brightfield map of ECD Cu wafer with swirl marks. 5B: Swirl marks captured by SP1TBI.

A B

circle RS#013

17Spring 2000 Yield Management Solutions

Lithography Defects:Reducing and Managing Yield Killers through Photo Cell Monitoring

by Ingrid Peterson, Gay Thompson, Tony DiBiase and Scott Ashkenaz, KLA-Tencor CorporationRebecca Howland Pinto, Ph.D., Consultant

Defectivity challenges in the lithography moduleRecent results have shown that lithography defects previously thought to becosmetic can affect yield by as much as 15 percent.1 Stains and minor colorvariations can be translated into blocked contacts, bridging, missing or extrapattern defects, and CD variations during subsequent steps in the process. Asa result, managing defectivity during photolithography is as crucial to thecontribution of the photo cell to yield as are proper design, control of criticaldimension (CD) and overlay, film parameters and electrical parameters.

Many leading semiconductor manufacturers have found that the most effectivemethodology for controlling defectivity in the lithography module is to supplement after-develop inspection (ADI) with macro and micro photo cellmonitoring (PCM) using test wafers. The traditional approach has been toinspect product wafers in-line after the resist has been developed, using a highnumerical-aperture, brightfield micro inspection system together with abrightfield/darkfield macro inspection system. While this approach is highlyeffective for capturing micro defects (such as developer spots, resist lifting andcollapse, uncleared patterns, developer nozzle impact patterns, resist-developerresidue and amine contamination) and macro defects (such as missing photo-resist, focus spots, gross overlay errors and scratches) some compelling studieshave shown that several of these defect types have a low capture rate on productwafers. The low capture rate is primarily due to interference from defects fromprevious layers, or underlying grain or color variation that makes detection ofa defect, that is itself represented as a minor color change, challenging. Theresulting delay in detecting a tool or process problem can have serious financialconsequences, especially for back-end-of-the-line (BEOL) layers, where prior-level “noise” is highest. Consequently, lithography process excursions may notbe evident until electrical testing several weeks later.2

A photo cell monitor, sometimes called an excursion monitor,2 is a resist-on-silicon or resist-on-oxide-on-silicon patterned test wafer fully processedthrough the lithography cluster. It may use the same reticles as the productwafer, or use a reticle specifically designed for photo cell monitoring. Macroand micro defectivity are measured on the PCM wafer, the defects are classifiedusing automatic defect classification (ADC) and the critical dimensions (CDs)

SSttoorryyCover

of the resist are measured using scan-ning electron microscopy (SEM).3

Statistical process control (SPC)charts use the categorized defectivityand metrology data to monitor theperformance of the lithography clusterand identify excursions and trends.

The advantage to using a PCMmethodology is that the wafer has

line optical and SEM review stations,and PMC-Net analysis for aid intracing the source of the defects andmanaging the data flow. Finally, theSample Planner™ program can helpdevelop a custom sampling plan forthe fab’s specific needs.

The equipment set and methodologydescribed in this paper have arisenfrom collective expertise and casestudies from many fabs, with the aimof minimizing the contribution of thelithography module to yield loss.This is accomplished through efficientcapture and classification of criticaldefect types which in turn enablequick response to defect excursions,and best return on investment of thedefectivity equipment set, while im-proving the overall equipment effec-tiveness of the lithography clusters.

Financial impact of a PCM programMotorola estimated recently thatreplacing manual macro inspectionwith automated macro inspectionwould prevent more than $4M scrapper year, with a differential average netyearly equipment cost of ownershipof $0.4M.4 This estimate was basedon assuming a scrap rate from thelithography module of 0.01 percentand 5000 wafer starts/week. In a pilot study they found that thegreatest benefit was obtained from100 percent inspection of output froma new photo cell, which producedsporadic failures due to multiple coatand develop stations, and new soft-ware issues. The magnitude and qualityof this financial benefit can be appliedto macro PCM as well as to macro ADI.

The use of PCM has been shown tobe effective in managing lithographydefectivity. It provides a high signal-to-noise ratio and early detection ofproblems which might not other-wise be recognized, or might be rec-ognized only at test, once yield hasbeen impacted, and after many lotsof wafers may have been affected.Yield impacts of 15 percent havebeen seen where defects were nototherwise under effective control.

18 Summer 2000 Yield Management Solutions

only one resist film, which dramati-cally reduces the noise introducedinto the inspection by underlyinglayers, which inevitably havedefects, grain, and film-thicknessvariations — especially in the back-end layers. The topography of aPCM wafer is also much simplerthan that of a product wafer. As aresult the PCM wafer can provide avery sensitive monitor for yield-lim-iting excursions caused by eitherequipment- or process-induceddefects. Furthermore, the experienceof KLA-Tencor’s Yield ManagementConsulting (YMC) group has shownthat roughly 90 percent of defecttypes seen on product wafers at ADIcan be detected by PCM (Figure 1).

Using KLA-Tencor’s 21XX microand 2401 macro inspection systems,the PCM methodology provides themost efficient and effective inspec-tion strategy for detecting processexcursions in the lithography module(Figure 2). The complete equipmentset would include reticle requalifica-tion using STARlight SL3UV, unpat-terned wafer inspection to qualifyand monitor the health of the toolsusing SP1TBI, automatic defect classi-fication using IMPACT ADC on off-

Figure 1. PCM defects can accurately repre-

sent defects on product wafers, and find them

earlier in the process. On the left are three

examples of defects found on PCM wafers that

may cause defects of the types shown on the

right, detected on product wafers after etch.

Figure 2. Poor spin quality can be observed visually and captured using automated micro inspec-

tion and/or automated macro inspection. In most instances the lowest cost of ownership system

that can detect the defect will provide the most benefit. In this case an intelligent sampling strate-

gy would allow the high-speed macro inspection system to capture this defect first – making the

micro inspection unnecessary.

C O V E R S T O R Y

PCM Defect Defect After Etch

21XX micro wafer inspection system 2401 macro wafer inspection system

topography, subtle color variation,and/or small physical extent. All ofthese characteristics mean that thesignal for optical detection is small.Thus, reducing the denominator inthe signal-to-noise ratio by remov-ing the additional challenge ofdetection on a product wafer raisesthe capture probability of defectshaving these characteristics.

Micro PCM Defect TypesDeveloper spots (Figures 3 and 4) areobserved on developer equipment fromevery vendor, and are one category oflithography-related defects whosecapture rate benefits from using aphoto-cell monitor wafer. Oftenclassified as missing pattern or extrapattern during in-line monitoringafter-etch, and commonly detectedon the perimeter of the wafer, thesedefects can be caused by splash-backafter the develop cycle. Possible causesinclude poor exhaust in the develop-er cup, developer cup design, or thetype of developer nozzle. This defecttype is not seen by traditional develop

track particle monitors using baresilicon wafers since its mechanism isdependent upon the surface tensionbetween resist and developer. Thesurface properties of the resist-coatedPCM wafer, however, are favorablefor detecting this defect type.5

Developer residue ( Figures 3 and 4) isa defect type found on PCM wafersthat monitor via and contact pattern.Because the defects are very low con-trast and have color variation similar tothat of developer spots, they are hardto find on production wafers duringADI due to noise from underlyinglayers. Their spatial distribution isdistinctive. Very dense, radial, andtypically following the pattern on thewafer, the spatial distribution ofdeveloper residue provides animportant clue to the source of thistype of defect. Developer residues cancause blocked contacts or blocked viaopenings on the product wafer,which can lead to significant yield loss(Figures 6 and 7). Probable causesinclude developer CO2 or resist-

19

The yield impact has significantcost, both through lost material, andthrough lost fab manufacturingcapacity. In the case of multi-prod-uct ASIC and foundry fabs, the risein defectivity may have significantimpact on the fab’s ability to satisfya customer with a small number ofwafers of a particular product.

PCM methodology fordefect reductionDefectivity control in the lithogra-phy module relies on three steps: 1)optimization for detection of photoproblems; 2) establishment of theprocess performance baseline; and 3)improvement of the baseline.Introducing the PCM approach tocomplement ADI informationaddresses each step.

Photo defects are difficult to detecton product wafers because the noisefrom the topography, grain and colorof the underlying layers confounds thedetection of current-layer defects, asmentioned previously. In particular,many lithography defects have low

Spring 2000 Yield Management Solutions

• Comets• Striations• Spins• Microbubbles• Lifting• No resist

• Missing• Focus error• Gross misalign• Aperture blade error• No exposure• Hot spots

• Missing• Wrong width• Miscentering

• Scumming• Developer spots• Residue• Resist collapse• Satellite spots• No develop• Deformed contacts

SurfacePrep

ResistSpin

HardBake

Edge BeadRemoval

Develop Post ExposureBake

SoftBake Align and

Expose

Figure 3: A wide variety of defect types can arise in the lithography cell.

C O V E R S T O R Y


Figure 4. Detecting these common defect types before the wafers leave the lithography cell allows simpler and faster identification of the source of

the defects, and results in fewer wafers scrapped or dispositioned for re-work.

C O V E R S T O R Y

Defect Typical Cause Example RecommendedInspection System

Comet • Dried resist on dispense nozzle

Missing and extra • Contamination or perturbation on pattern, CD error wafer surface 2401

• Contamination in resist

Lifting • Changes in surface tension conditions

Missing and extra • Inadequate soft bakepattern 2401

• Missed PEB

• Over/under priming

Microbubble • Resist dispense rate

Broken leads for • ARC/resist interfacial interaction betweensmaller design rules substrate, primer and coating 21XX

• Air leak in the resist pump

• Mis-adjusted suck back

Developer Spot • Splash-back after the develop cycle

Missing or extra • Poor exhaust in the developer cup,pattern after etch developer cup design, or developer

21XX

nozzle type

Developer Residue • Developer-CO2 or resist-developerinteractionBlocked contacts

after etch • Ph shock 21XX

• Non-optimized develop/rinse conditions

Closed or Deformed • Residue on the contact hole, unoptimizedContact develop program 21XX

Satellite Spot • Resist-developer interaction

Blocked contact orextra pattern after

21XX

etch

Developer Nozzle • By-product of develop and resist Residue chemistries

Bridge between • Contamination of developer nozzle 21XXlines

Develop ProcessRelated Defects

Defe

ct D

ensi

ty (

Defe

cts/

cm2 )

Time

Cup 3-2 Cup 3-3

Develop ProcessRelated Defects

Contact PCM

Poly PCM

21Spring 2000 Yield Management Solutions

are typically near the center of thewafer or out near the edge, and aredue to exhaust imbalance, EBR pres-sure control problems, or spurts.

EBR width errors come from improp-er setup of the EBR nozzle or opticalEBR exposure. These can result in areduction of usable wafer area (if toolarge) or contamination from flakedresist (if too small).

Hot spots or focus spots are regionswhere the stepper does not focusproperly. These may be due to back-side particles which remain on thewafer or are transferred to the step-per chuck. With today’s highnumerical-aperture lenses, the sus-ceptibility to hot spots is increasing.

Several of the developer errors listedas micro PCM defects may also man-ifest themselves at a size detectableby macro inspection.

Inspection equipment setApart from the PCM wafers them-selves, the inspection equipment setfor defect reduction in the lithographymodule using a PCM approach isidentical to that used for ADI. Abrightfield inspection system havinga high numerical aperture, such asKLA-Tencor’s 21XX, is optimized forcapturing low-contrast micro defectslike developer spots, residues andmicrobubbles. Defects having char-acteristic spatial distributions, suchas comets, striations, spin defects,scratches, etc. require a macroinspection system like KLA-Tencor’s2401.

developer interaction; developer pre-cipitates, rinse deficiencies, or resistand developer surfactant bonding.

Microbubbles (Figures 3 and 4) areexamples of defects whose size (<< 0.5 µm) makes them difficult todetect at ADI. This defect, whichcan cause broken leads for deviceshaving critical dimensions less than0.35 µm, is readily detectable usingPCM wafers with high sensitivityinspection. Probable causes includeresist dispense rate, ARC/resistinterfacial interaction, and interactionbetween substrate, primer and coating.

While the resist process is typicallyvery clean, an example of a resist-related defect that can be foundthrough PCM is amine contaminationof the deep ultra-violet (DUV) resist.The contamination can degrade theprofile of the resist.

Macro PCM Defect TypesWhile many lithography processdefects are readily detected usingmicro inspection, some may also bedetectable using macro inspection, atsubstantially higher throughput.Many errors in resist coating, exposure,develop, and rinse result in defectswhich cover a relatively large area.

Resist coating errors can come from anumber of causes, from poor surface

prep to problems with the resist dis-pense. These defects can cover largeportions of a wafer, but may also beas small as 50 µm. Because they arerelatively large, and tend to occur inclusters, they can have significantyield impact.

Resist film defects such as comets maycome from contamination in the resist.A well-defined head points towardthe center of the wafer, and a wake ofresist thickness variation flares outtoward the wafer edge. The head willcause a hard defect, while the tail mayresult in significant CD variations.

Edge Bead Removal (EBR) splashbackcomes from solvent which is aspirat-ed and deposits back on the wafersurface during spin, resulting inspots of cleared resist. These spots

Figure 5. In production, IMPACT ADC classified the Satellite and E2 Nozzle defects with better

than 95 percent accuracy and purity, while Klarity Defect observed their spatial signatures. The trend

chart shows that both problems were fixed, and excursions in both defect types were monitored.9

Figure 6. Using a PCM wafer based on the actual contact reticle instead of a lines-and-spaces

PCM wafer provided much improved correlation to the observed defect density on the product.

C O V E R S T O R Y

Excursions resolved using Klarity DefectIMPACT classified defectsKlarity observed signatures

The way these two systems are usedtogether is primarily based on defecttype, but also on minimizing cost ofownership. The 2401 is more sensi-tive to low-level hot spots, and itshigher throughput and lower pricemake it more cost-effective than the21XX for detecting large-area errorssuch as bad spin, comets, striations,edge-bead removal errors, etc.(Figure 2.) The 21XX is essential fordetecting small, localized defects.While the best strategy for imple-menting the tools depends upon indi-vidual circumstances including thecomplexity of the lithography processand operation of the fab, typically the21XX and 2401 would be used to scaneach PCM wafer every shift duringdevelopment, and daily during pro-duction. The 2401 would typicallybe used first to filter macro issues.The wafers would then be inspectedfor micro defects by the 21XX. Bothmicro and macro PCM inspectionare used for each path through thetrack and resist combination, sinceeach may fail independently.

After the defects are detected, auto-matic defect classification is used toseparate the defects into types. Oncedefects are classified, SPC can beapplied to track by defect type or bygrouping killer versus non-killerdefects. The kill ratio of individualdefect types would be determinedfrom short loop PCM experimentssince the capture rate for many of thelithography-related yield-limitingdefects is low for after-developinspection on product wafers.

Optical ADC should be performedin conjunction with SEM reviewsince some defect types cannot bedistinguished optically, but onlythrough SEM review.

After-develop inspection comple-ments the lithography defect reductionprogram by capturing topography-related process-integration defects.Micro ADI might be employed for 2or 3 wafers per lot, while macro ADIwould be used on 50 percent to 100percent of the wafers in each lot.


C O V E R S T O R Y

Defect Type: Isolated Closed Contacts

SEM Imageof Closed Contact

Optical Imageof Closed Contact

Defect Description:• Killer Defect

• Posible cause: micro-bubbles in the developer

• Can be eliminated by optimizing develop program, and/or eliminating bubbles in the developer puddle Low-Magnification

SEM ImageHigh-Magnification

SEM Image

Defect Type: Resist residueEDX Analysis ResultsOptical Images

SEM Images

Defect Description:• Defect can be caused by nozzle

residue

• Can be reduced by optimizingdevelop program (dispense speedand time, DI water rinse speed)

• Can be a killer defect if it lands on top of contact

0.00-0.20

0.20-0.50

0.50-1.00

1.00-1.50

1.50-2.00

2.00-3.00

3.00-5.00

5.00-8.00

8.00-10.00

10.00-9999.00

7

9

6

0 5

SEM Images of Area of Missing PatternOptical Review

Defect Type: Area of Missing Pattern

Defect Description:

Figure 7. Defect types in the lithography cell associated with missing contacts after etch were

uncovered using the contact PCM technique. These defect types included: (a) isolated closed con-

tacts; (b) resist residue; and (c) areas of missing pattern.

23

Case study 1: AMD SDCAMD SDC discovered the value ofusing a photo cell monitor for a crit-ical lithography process having sixlevels of metal. They found by fail-ure analysis that they had a problemwith missing contacts and vias, butneither their in-line inspectionresults after etch or after developdetected an excursion.6 When theyfirst implemented a PCM methodol-ogy they used a lines-and-spaces ret-icle that mimicked the poly step.They still found poor correlationbetween the contact failures andtheir inspection results.7

The breakthrough came when theycreated a new PCM using the con-tact reticle itself. This contact PCMincreased their sensitivity to subtle,low-topography defects by reducingthe noise contributed to the measure-ment by the underlying layers of theproduct wafers. Furthermore, somedefect types depend upon the amountof unexposed photoresist on the waferand its interaction with the developer.These defect types are usually notdetected reliably using a lines andspaces reticle (Figure 6). Using thePMC based on the actual contact reti-cle enabled the mystery to be solved.

Three defect types in the photo cellwere found to be associated with themissing contacts after etch: isolatedclosed contacts, resist residue andareas of missing pattern (Figure 7).The low noise of the contact PCMalso allowed AMD to detect arepeater on the contact reticle, whichthey were unable to detect with anyinspections using product wafers.7

The missing contact and via prob-lems were found to have four differ-ent sources:

1) randomly isolated missing con-tacts and vias due to a developer program optimization issue;

2) randomly isolated missing con-tacts caused by a residue fallingon the open contact and via afterdevelop, which blocked the etch;

3) large areas of missing contacts andvias caused by large residues andbubbles in the develop process;

4) the repeater mentioned above.

Although 1) and 2) were indistin-guishable under optical review, sub-sequent SEM review clarified thatthe sources of these defect types werevery different.

Case Study 2: IBMIBM began to experiment withPCM methodologies when they weredissatisfied with the correlationbetween product inspections and yieldin the photolithography module. Aftersix months of PCM operation, theyfound that all process excursionswere detected, and response time tothe excursions had improved signifi-cantly.2 The defect types that wereidentified successfully using PCMincluded starburst defects, hexam-ethyl-disilazane (HMDS) flaking,focus spots, printed defects, and doseand resist-thickness variations. Thesedefect types are described and illus-trated in Reference 2. Each of themcauses yield-limiting defects down theline. Furthermore, the PCM approachallowed the engineers to identifyequipment problems quickly, reduc-ing the rework and scrap costs. Insome cases, the source of the defectswas found months before it may havebeen found using traditional methods.

Case Study 3: NEC UKNEC were interested in using auto-mated macro inspection and a PCMwafer to monitor their stepper.8 Theycreated a diffraction-grating reticlewith 0.3 µm lines and spaces, andperformed a focus-exposure matrixwith focus offsets and leveling offsets.They inspected the wafers on the 2401and used the results to estimate theprocess windows. The 2401 detecteda slight defocus process excursion, anda slight field tilt process excursion.(See article on page 35.)

Summary Photo cell monitoring using a testwafer with a single layer of patterned

Summer 2000 Yield Management Solutions

photoresist can be cost-effective andcan provide defect capture in manycases superior to that of after-developinspection.

The superior defect capture using aPCM wafer instead of product arisesfrom its single-layer design, whichremoves the noise contributed by thetopography, grain and color varia-tion of underlying layers. This is aparticularly important strategywhen the defects are low-contrast,which is typical for many of the lith-ography-related defect types.

The complementary strategy of linemonitoring using micro and macroADI on production wafers makes itpossible to (1) catch excursions ofcritical defects including topographyrelated process integration defectsnot seen on the PCM wafer; (2) makequick go/no-go determinations ofthe health of the production lot andprocess tool module; and (3) disposi-tion product wafers more effectively.

As part of a complete defect reductionprogram in the lithography module,the use of a photo cell monitor formicro and macro process tool moni-toring can provide significantimprovement in defect detection,better process tool health plans andfaster response time to process excur-sions. These benefits translate directlyinto significant savings in rework andscrap costs, and raise the contributionof the lithography module to deviceyield. Numerous fabs have demon-strated significant improvements inlithography defectivity by establishingdefect management through PCM.

References1. Ingrid Peterson, “Defect Reduction

Methodology in the Li thographyModule,” Proceedings from the XIIIAnnual Meeting of the SPIE Mi-crolithography Conference, March,1999, pp 520-528.

2. Eric H. Bokelberg and Michael E.Pariseau, “Tracking the performanceof photolithographic processes withexcursion monitoring,” MICRO, Jan-uary 1998.

C O V E R S T O R Y

24

3. John Al lgair, Gong Chen, SteveMarples, David Goodstein, JohnMiller and Frank Santos, “Feature In-tegrity Monitoring for Process ControlUsing a CD SEM,” presented atSPIE’s 25th Annual International Sym-posium on Microlithography, Febru-ary, 2000.

4. Arnold Yanof, Vincent Plachecki,Frank Fischer, Marcelo Cusacovich,Chris Nelson and Mark Merrill, “Im-plementation of Automated MacroAfter Develop Inspection in a Pro-duc t i on L i t hog raphy P roce s s , ” presented at SPIE’s 25th Annual In te rna t iona l Sympos ium on Microlithography, February, 2000.

5. Ingrid. B. Peterson, “Importance ofDefect Reduction in the LithographyModule,” Yield Management Solu-tions, Autumn 1998.

6. Christina Cheung, Robert Chiu, KhoiPhan, Ingrid Peterson, Andy Phillips,Kevin Kan, “Contact Photo Cell Monitor(PCM) for an Advanced BEOL Litho-graphy Process,” in Proceedings of theSEMICON/West Yield ManagementSolutions Seminar, July, 1999.

7. Private communication. 8. Iain Rutherford, Brian Haile, and Tony

DiBiase, “Production QC and ToolMonitoring Using and Automated PostDevelop Macro Inspection System,” tobe published in Proceedings of theSEMICON/Europa Yield Manage-ment Solutions Seminar, April, 2000.

9. Frank Poag, Douglas Paradis, Ma-hesh Reddy and Jon Button, “DefectYield Management using the KLA-Tencor Intelligent Line Monitor,” inProceedings of the SEMICON/Southwest Yield Management Solu-tions Seminar, October, 1999.

Summer 2000 Yield Management Solutions

Figure 8. Defocus process excursions were identified by the 2401 by performing a focus-exposure matrix using a PCM wafer, after a problem with

the stepper was suspected.

About the AuthorsDr. Ingrid B. Peterson is currentlySolutions Development Manager forLithography and Parametric ModuleSolutions at KLA-Tencor. She joinedKLA-Tencor in 1995 and has heldpositions as Applications DevelopmentManager for Reticle InspectionAnalysis products and as a consultantfor KLA-Tencor’s Yield ManagementConsulting Group. Prior to joiningKLA-Tencor, Ingrid worked as a staffprocess engineer in photolithography,was a staff research scientist at the MaxPlanck Institute for Solid State Physicsin Stuttgart, Germany and was anadjunct assistant professor in thePhysics Department at the Universityof California Los Angeles. Ingridearned a Ph. D. in Physics from theUniversity of California at SantaBarbara.

Gay Thompson is currently FieldMarketing Manager for Defect ModuleSolutions at KLA-Tencor. She joinedKLA-Tencor in 1996 and has heldpositions in New Production Intro-duction and Product Marketing forKLA-Tencor’s wafer inspection prod-ucts. Prior to joining KLA-Tencor,Gay worked as a program manger inthe U.S. Air Force, managing thedevelopment, production and launchof satellite systems. Gay earned aB.S.E.E. from MIT and a M.S.E. fromthe University of Texas at Austin.

Tony DiBiase is a director in the YieldManagement Consulting division of

C O V E R S T O R Y

Focus Offset ResultsWafer No. +ve Offset Detected -ve Offset Detected

1 0.05 N -0.05 N0.1 N -0.1 N

2 0.15 N -0.15 N0.2 N -0.2 N

3 0.25 N -0.25 N0.3 N -0.3 Y

4 0.35 N -0.35 Y0.4 Y -0.4 Y

5 0.45 Y -0.45 Y0.5 Y -0.5 Y

6 0.55 Y -0.55 Y0.6 Y -0.6 Y

7 0.65 Y -0.65 Y0.7 Y -0.7 Y

KLA-Tencor. Since 1980, Tony hasheld various positions in maskmaking,process integration, metrology, litho-graphy development, and maskmakingat National Semiconductor, Synertek,and Synergy Semiconductor. He has aB.S. in Chemistry from the Universityof Cincinnati.

Scott Ashkenaz is KLA-Tencor's VicePresident of Strategic Marketing forPatterning and Parametric ProcessModule Control Solutions (PMCS),which provides lithographic andparametric alignment among KLA-Tencor's products to improve waferfab productivity and capability. Priorto joining KLA in 1985, Scott wasthe Mask Lithography Manager forAustrian Microsystems, and respon-sible for AMI's advanced mask devel-opment program. He attended theBachelor's and Master's programs inPhotographic Science and Engineeringat Rochester Institute of Technology.

A former director of marketing withKLA-Tencor, Rebecca HowlandPinto is an independent consultantin technical marketing. A frequentcontributor to Yield ManagementSolutions, Ms. Pinto has publishednumerous articles and lecturedworldwide during her 10 years in theindustry. She has a Ph.D. in appliedphysics from Stanford University,and an A.B. in physics fromDartmouth College.

circle RS#046

1Summer 2000 Yield Management Solutions

KLA-Tencor Trade Show Calendar

July 10-14 SEMICON/West, San Jose and San Francisco, California

August 2-4 CleanRooms/DataStor Asia, Singapore

September 13-14 BACUS, Monterey, California

September 13-15 SEMICON/Taiwan, Taipei, Taiwan

September 18-20 UCPSS, Ostend, Belgium

September 19-21 Diskcon, San Jose, California

October 3-5 ITC, Atlantic City, New Jersey

December 6-8 SEMICON/Japan, Makuhari, Japan

New look . . . new perspective. Visit www.kla-tencor.com

Coming soon to a monitor near you.

Spring 2000 Yield Management Solutions24

Yield ManagementSeminar

A valuable venue for innovative ideasKLA-Tencor’s Yield Management Seminars (YMS) focus on value-added, integrated processmodule control solutions for defect reduction, process parametric control and yield manage-ment. Key topics include navigating the transition to the 0.13 µm technology node, with specialemphasis on copper/low κ interconnect, sub-wavelength lithography, and the 300 mm wafer.

To reserve your space at the upcoming YMS, contact Tavis Szeto by email [email protected].

Date: Tuesday, July 11, 2000Time: 9:00 am – 6:30 pmLocation: The Argent Hotel, San Francisco

For information on future YMS, please complete and return the enclosed business reply card.

Call for future papersPapers should focus on using KLA-Tencor tools and solutions to enhance yield throughincreased productivity and performance. If you are interested in presenting a paper at oneof our upcoming yield management seminars, please submit a one page abstract to: Tavis Szeto by fax at (408) 875-4144 or email at [email protected].

YMS at a GlanceDATE LOCATION

July 11 San Francisco, CaliforniaAugust 3 SingaporeAugust 9 Hsinchu, TaiwanOctober 18 Austin, Texas

Lithography


S P E C I A L F O C U S

Application of Automatic DefectClassification in Photolithography

by Gary Stinson, Microchip Technology Inc. and Bo Magluyan, KLA-Tencor Corporation

This paper presents two applications of Automatic Defect Classification (ADC) to monitor and control defect density inphotolithography processing. These techniques can also apply to any process module. Many defect types are only generatedwhen wafer pattern is present, while other yield impacting defects are detected only on monitor wafers due to a low signal-to-noise ratio on product wafers. The use of ADC in both cases to find root cause solutions is a powerful tool enablingquick time to results and reduced yield risk in the manufacture of integrated circuits.

results generated from such a study is directly depen-dent on the accuracy and purity of the classification ofthe defect.

Microchip’s ADC program, consisting of KLA-Tencor’sIMPACT ADC, 2135 inspection system, and KlarityData Analysis is used extensively in this engineering role.

Case 1: Problem descriptionYield trends for a new device were trending belowexpectations. One of the primary failure modes for thedevice was high standby current. Failure analysisrevealed a trench from metal to substrate causing thehigh standby current failure (Figure 1).

ADC is a powerful technique that has truly come into its own in recent years.Envisioned as a logical progression of defectinspection and review, the ADC concept hasbeen faced with serious technical challengesthat have taken time to overcome. Its pri-mary focus is to replace the manual reviewof defects detected by the inspection sys-tems. Classification accuracy, speed, andcost are all significant factors relating to thejustification of ADC, especially for fabs thatalready have manual classification systemsin place. In this paper another perspectiveconcerning the justification of ADC overmanual review is presented.

Identifying a defect and finding the piece ofequipment or process module that is gener-ating the defect is only the first part ofimproving yields. Eliminating the rootcause is always a difficult task that oftenrequires designed experiments to identifythe defect mechanism. When designedexperiments are used to solve a defect issue,the output response is the number of thedefect type of interest. Depending on thecomplexity of the process, many wafers mayneed to be inspected and reviewed to deter-mine the statistical validity of the changesmade. Additionally, the confidence level of

Figure 1. SEM image of device failure.



The spatial signature of the defect showed a higherdensity in the center of the wafer. Analysis of multipledie failing for the same bin found that there was a ten-dency for the defect to occur around specific types ofstructures. The source of the defect appeared to bebetween the second poly silicon level and first metaldeposition. The crack would travel along the edge ofthe poly2 until it found relief.

To investigate further, a newly installed KLA-Tencor2135 with IMPACT ADC was brought on-line. Initialinspections prior to Metal1 deposition detected thedefect, which appeared to be a stress-relieving crack inthe dielectric. This was allowing the remaining etchprocesses to trench into the silicon substrate causingthe current leakage. Since the dielectric was identicalto previous technologies, which were not experiencingthe problem, it was suspected that the defect had to bepatterned on the wafer in the contact photo step andsubsequently etched through to the substrate.Inspection of wafers after the contact photo step detect-ed the stress crack in the resist as suspected. SEMimages showed that the contacts were not distorted,but lifted from the wafer intact (Figure 2).

Figure 2. SEM image of resist crack.

The sequence of events in the investigative process,from the failure analysis results to locating the defectin the resist took a relatively short period of time.Solving the problem without significantly changing acritical photo process appeared to be a much more dif-ficult task.

ADC on product wafersAfter the defect was found patterned in the photoresist,the process module was shut down until a solutioncould be found. Photo engineering evaluated all litho-cells qualified for the process to ensure that specifica-tions were being adhered to. All systems were func-tioning normally and in control. After the setup para-meters were verified, monitor wafers were processedwith individual photo process steps and film stressmeasurements were made. Although the stress mea-surements were tensile, consistent with the formationof these types of cracks, the data failed to indicate apart of the process causing the defects (Figure 3).

While these experiments were being conducted, anADC classifier based on the initial wafer inspectiondata was being developed. This rudimentary classifierwas constructed from only two wafers from one lot, butsince the defect features were unique, the accuracy andpurity were high.

ADC was used to generate results for the next designedexperiment, which focused on various modifications ofthe process. Data from the ADC bin for resist crackswas able to show that the number of cracks werereduced on each of the non-standard splits, but werenot eliminated entirely (Figure 4).

If manual review utilizing defect sampling were used,it is possible that split #5 could have given a false goodresult. Not only did ADC return information morequickly, but the data was also more accurate.

Since the first tests reduced the number of cracks butdid not eliminate them entirely, the root cause was stillto be determined. Several process splits were generated,varying the resist thickness and coat procedures. Again,ADC was used to review all the defects detected. Thistime the data showed the stress cracks to be eliminatedon all splits except the standard process. The standard

Process Stress (mPa Tensile)

Bare Si BPSG

Prime/Coat 16.4 12.9

Prime/Coat/Soft Bake 15.1 4.6

Prime/Coat/SB/PE Bake 13.5 10.2

Prime/Coat/SB/PEB/Develop 18.4 18

Prime/Coat/SB/PEB/Dev/Expose 14.3 12.3

Figure 3. Film stress data.



process used a high spin speed for an extended period oftime to accomplish both the cast (step used to get theproper thickness) and dry (step used to allow solvents toevaporate). The ADC data showed conclusively that byslowing down the dry step or by increasing the resistthickness, the defect was eliminated entirely (Figure 5).

The quickest and best solution was to leave the resistthickness unchanged and implement the changes to thedry step. Within hours, production was resumed with anADC wafer inspection implemented. After the processchange, the ADC classifier detected no additional cracks.

Inspections continued until yield data could be gatheredusing the new process. A dramatic yield improvementin the form of reduced variation confirmed the dataalready available from the ADC classifier (Figure 6).

Case 2: Problem descriptionThe second case applies to an incident of contaminatedphotoresist. A simple EPROM device has historicallybeen used as a defect monitor since it has relativelyhigh circuit density and significantly larger die thanthe majority of other microcontroller products. Yield

trends on this device had not been meeting expectedgoals. Several failure analysis attempts to identify thecause pointed to 0.5 µm to 1.0 µm Poly2 bridgingbetween adjacent memory cells, but visual and laserscattering inspections were not able to find the defect

Num

ber

of P

arts

Pas

sed

Lot Number

Resist Crack Eliminated

Split Description Wafer Cracks# Found

1 Standard Resist Thickness 7 0

with Split Cast/Dry Steps 12 0

14 0

21 0

25 0

2 Thicker Resist with 1 0

Extended Dry Step 8 0

15 11

10 0

22 0


Split Cast/Dry/Step 9 0

17 0

18 0

23 0


Modified Prime Step 4 0

5 0

10 0

24 0

5 Standard Process 11 6

13 3

20 3


without PEB 19 3

Split Description Wafer Cracks# Found


2 12

3 20

4 46

5 21

2 Standard Process with 18 7

Modified Prime 20 7

21 11


without ARC 23 7

24 18

25 7

4 ARC after Soft Bake 14 5

17 3

5 ARC after SB, 10 2

rinsed before PEB 13 3

6 Standard Process with 6 8

extended Prime 8 10

9 2

Figure 4. ADC results of first experiment.

Figure 5. ADC results of second experiment.

Figure 6. Parts Passed trend chart shows case 1 yield improvement.


in-line. A sharp downturn in yield for this device andothers relating to the same defect mechanism raised thepriority for eliminating the defect.

A KLA-Tencor 2135 inspection system was broughton-line and quickly detected the defect. Resist precipi-tates that were not being developed away were pro-truding from the resist lines causing the blocked polyetch (Figure 7).

The defect density was very high indicating that some-thing had gone wrong with the resist quality. All prod-uct lines using this resist were shut down until theproblem could be solved.

The Photo Group’s efforts to find the source of thedefect focused on several possible causes. Photoresisthandling and storage techniques were verified to be inspec. Particle tests for contaminated batch also provedto be within the manufacturing tolerances. Yield datavs process dates were analyzed showing the downturnto loosely correlate with a change in resist filter type.Since the precipitates were larger than the filter rating,and the particle counts of the resist were in spec, therehad to be more to the problem than the filter issue.

ADC on monitor wafersWhile photo engineering was investigating the resist,an ADC classifier was developed using the initial datathat detected the defects in the resist. Overall setup ofthe classifier took only a few hours and appeared very

promising. The first experiment was to put the old filtertype back on line to see if it would get the problemunder control so that production could continue.Product wafers were processed and inspected using theADC classifier to measure effectiveness. Although therewas a decrease in defect density, it was not significantenough to resume production. More tests were attemptedwith a new bottle of resist, hand dispensed resist, newresist lines, new resist pump, etc. The defect densityand defect size were reduced with each test as the resistdelivery system was purged of the contamination.Production was resumed and the inspection with ADCwas used to monitor the defectivity level.

As the precipitates became smaller, it became obviousthat background nuisance defects in the underlyingpoly silicon were causing confusion. A better solutionhad to be found to monitor for additional excursions.The product inspection was replaced with a daily pat-terned resist monitor. The use of monitor wafersbrought about new types of defects not seen on prod-uct, but since the poly silicon was not present, theaccuracy and purity of the classifier were muchimproved. Monitoring the defect level of the resistADC bin was successful in measuring additionalimprovements and monitoring for excursions.

Additional tests indicated that an interaction wasoccurring between the resist and the pumping system,causing the precipitates to form downstream of the fil-ter. Since no other resist in use was showing the prob-lem, the root cause solution was determined to be aresist change. Qualification of a new resist can take aconsiderable amount of time especially for a criticallayer like Poly2. Using the ADC classifier, a mainte-nance procedure was identified to control the defectivi-ty until a new resist could be qualified. This procedurewas incorporated in the scheduled quarterly PM andinvolved changing the pump, filter, and chemicallycleaning the delivery lines. By having a cleaned pumpready at all times, the time required to perform theprocedure did not significantly increase downtime.

As the monitor wafer procedure was fine-tuned, itbecame possible to control the defectivity by using theraw counts from the inspection. The defect mechanismproved to follow a predictable failure cycle that wascontrollable through a scheduled maintenance proce-dure. Defect images captured using the ADC systemwere still useful to verify the defect type, but the con-trol charts were changed to total counts for simplicity.


Figure 7. Resist precipitate.

Device yield for all products using the resist increasedby a step function in response to the actions taken. Theresist monitors were changed from daily to weekly asconfidence in the maintenance procedures increased(Figure 8).

SummaryIn this paper two examples of the use of ADC to findroot-cause solutions for yield limiting defect excursionshave been presented . The first utilized ADC on prod-uct wafer splits since the defect was generated only onwafers with topography. The second example showedthat ADC’s capability can be extended beyond theinspection noise level inherent in product inspectionsby using monitor wafers. By using ADC, useful infor-mation from the wafer inspection data was generatedfaster and with improved signal to noise than if manualreview were used. This technique demonstrates thenatural extension of ADC from the production-moni-toring arena into complex engineering studies to elimi-nate defects and improve yields.

Num

ber

of P

arts

Pas

sed

Lot Number

Resist Defect Eliminated

Figure 8. Parts Passed trend chart shows case 2 yield improvement.


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Presented at 10th Annual IEEE/SEMI Advanced Semiconductor ManufacturingConference and Workshop (ASMC), September 8-10, 1999, Boston, MA.

circle RS#015


Production QC and Tool MonitoringUsing an Automated Macro ADIDefect Inspection System

by Iain Rutherford, Brian Haile and Tony DiBiase, KLA-Tencor Corporation

This paper was presented at KLA-Tencor’s Yield Management Solutions Seminar during SEMICON/Europa in April 2000.

The major weakness of traditional, manual after-develop inspection (ADI) lies in the variability of the results. Defect capture rates are variable due to differences in the ability and experience of the inspection operators. Subsequent analysis ofdefects can also be inconsistent as some operators might flag a defect while others might pass it thinking it unimportant.Manual inspection is also one of the most tedious and unpopular jobs in the fab among the operators.

The ability to drive yield improvementfrom manual inspection results can be verypoor. Data from manual inspections can bevague and subjective, making it difficult toarchive or correlate with yield and paramet-ric results. The bottom line is that manualADI misses macro defects and costs money.

A solution to these issues is an automated,optical macro defect inspection system such as KLA-Tencor’s 2401. This systemwas installed for evaluation at NEC inLivingston, Scotland, and this paper reportsthe results from the evaluation at that site.The study was conducted in two parts:First, a comparison of manual versus auto-mated inspection using the 2401 for ADI,and second, an investigation of the potentialof the 2401 for evaluating and monitoringcertain aspects of stepper performance.

The 2401 works by simultaneously scan-ning and capturing darkfield and bright-field images of a wafer. The inspected fieldis compared with two fields adjacent to itand any discrepancies between the two fieldsare flagged as a potential defect. The systemhas an 80 wafer-per-hour throughput andcan capture defects greater than 50 µm. Ifneeded, wafers can be reviewed using avariety of software tools on the machine.

Manual vs. automated ADIOver 5500 wafers were involved in the first part of theevaluation, and most of these (5019) were randomlyselected for after-develop inspection. Some wafers withknown problems were chosen (225), and some originatedfrom engineering (322). The wafers were inspected man-ually, then taken to the 2401 for automated inspection.

Eight layers from one particular product were chosen.Lots were then randomly sampled from these layers.The layers represented a typical mix of front-end andback-end layers, both critical and non-critical.

Figure 1 demonstrates the overall sensitivity of the2401 compared with manual inspection. While manualinspection found that 3 percent of lots had issues worth

LithographyS P E C I A L F O C U S

Figure 1. With 213 lots inspected at random, 6 lots failed visual inspection

while 97 lots failed the 2401 inspection, demonstrating a 10X difference

in capture rate when replacing manual with automated macro inspection.

97%: Passed

3%: Failed

Visual Inspection Results

54%: Passed

46%: Failed

2401 Inspection Results


investigating further, the 2401 found that nearly 50percent of lots had defect issues of interest to the NECengineers. These results correspond to a 10-fold differ-ence in capture rate between the automated inspectorand the manual inspection procedure at NEC.

Examining these results as a function of defect type,Figure 2 illuminates the important fact that the top threedefect types — leveling, hot spots, and accelerationerrors — are related to the stepper (acceleration errorsare caused by movement or vibration of the stepper stageduring exposure). Figure 2 also reinforces the differencein capture rate between the 2401 and manual inspection.

Of the 13 ADI defect types that were part of this eval-uation, the 2401 was able to capture 10 of them with a“good” rating, and two of the remaining three with a“fair” rating. These qualitative results are tallied inFigure 3. The 2401 failed to capture whole-wafer focusdefects, but the next version of software is expected toremedy this omission. The two defect types receiving“fair” ratings are also whole-wafer defect types: no coatand no exposure/develop. The ability of the 2401 tocapture these defect types is also expected to improvewith the version 2.2 software release.

In contrast, only 4 of the 13 defect types received a“good” capture rating using manual inspection. Fivereceived a “fair” rating, two received a “poor,” and tworeceived an “unknown.”

The heart of the yield benefits for the 2401 over manualinspection is given in Figure 4. Of the lots that werechosen at random for inspection, 12 percent were sentfor rework. Five percent of the lots were flagged by bothmanual inspection and the 2401. These lots fell into the“rework/no save” category. However, another 7 percent of

the lots were only flagged by the 2401 and fell into the“rework/save” category as yield loss would have resultedand the 2401 enabled them to be reworked and rescued.

The most common defect type seen during the evaluationwas leveling problems. In particular, nearly 60 percentof metal 2 lots were found with leveling issues. Anyproblems with the stepper focus or leveling at metallayers can cause catastrophic electromigration failuresout in the field. In the case of metal 2, these defects werenot caught by manual inspection but the 2401 wasable to capture them reliably. Further investigationsuggested a solution to NEC for the problem.

Leve

ling

Hot

Spo

t

Acce

l

Scra

tch

Met

al D

epIs

sue

ILD

Issu

e

Cont

amin

atio

n

Poor

Coa

t

Com

ets

Lift

ing

Resi

st

WW

Foc

us

0

5

10

15

20

25

30

35

VI Fails

2401 Fails

p p

Num

ber

Lots

Figure 2. A breakdown of the detected defect types shows that step-

per problems such as leveling, hot spots and acceleration errors domi-

nated. This chart also emphasizes the dif ference in capture rate

between the 2401 and manual inspection.

Defect Type 2401 Capability VI CapabilityHot Spot Good FairLeveling Good Poor

Acceleration Good FairScratch Good Fair

Contamination Good GoodComet Good FairParticle Good Poor

Lifting Resist Good FairPoor Coat Good GoodNo Coat* Fair Unknown

No Exposure/Develop* Fair UnknownFilm Thickness Variation Good Good

Whole Wafer Focus* n/a Good

p

*WWD software version 2.2 will implement capture

Figure 3. Qualitative ratings of defect capture by type for the 2401

and manual inspection fur ther demonstrates the benefits of automated

macro inspection.

88%: No Rework

5%: Rework/No Save

7%: Rework/Save

Figure 4. While 12 percent of randomly inspected wafers were

reworked, only 5 percent were detected by visual inspection. The

2401 detected these wafers but also detected a further 7 percent that

could be reworked successfully.



Of second highest importance — on 21 percent of thelots — were hot spots. A particularly challenging layerfor manual inspection was a high-aspect ratio contactlayer called “hole.” NEC found it impossible to see anyhot spots or other focus-related defects at this layerusing manual inspection. It was proven that the 2401was able to capture these defect types at “hole”.

The third most important defect type was accelerationerrors. For one of the poly layers, ten lots were reportedto have acceleration errors. Four of them were found bymanual inspection, while nine out of the ten werefound by the 2401.

Two other defect types of note included no coat/expo-sure/develop defects and CVD stripe defects. The nocoat/exposure/develop defects were created intentional-ly to test the 2401, because NEC did not see any nat-ural examples during the evaluation though this defecttype was known to occur occasionally. The CVD stripedefect was found on several lots that had been put onhold by the operators and had been categorized as lift-ing resist. NEC found that adjusting the recipe on the2401 enabled them to either flag the defect or screen itout while still capturing photo related defects.

Stepper monitoringThe second part of the 2401 evaluation investigatedapplying the automated system for stepper monitoring.

The goal was to set up a quick, sensitive process forlooking at focus-exposure matrices, focus problems andleveling problems. A diffraction grating reticle wascreated with 0.3 µm lines and gaps, and then printedon unpatterned, resist-coated wafers using a KrF, deepUV stepper. This diffraction grating was used to reducethe process window of the photo process and bring itclose to the process window of the stepper itself. A focus-exposure matrix wafer was created (Exposure:centre 31mJ/cm2, step 2mJ/cm2 Focus: centre 0.0 µm,step 0.1 µm). The focus-exposure matrix produces ahistogram that indicates the optimum focus and opti-mum exposure for the process. Changes in the focus orexposure conditions would produce a change in thishistogram. Refinement of the field size used and focusand exposure steps should produce an effective and sensitive check for the stepper.

For the focus offset check, wafers were created with fouroffset fields, and each field had increasing positive andnegative focus offsets (Figure 5). The wafers were theninspected and the focus process window estimated. The2401 was able to detect a 0.4 µm positive offset and a0.3 µm negative offset. This equates to a detectableprocess window of 0.7 µm. KrF steppers typically haveinherent process windows of 0.6 to 1.0 µm. This wouldindicate that the 2401 can be used to detect any focus-offset excursions outside the stepper’s optimum processwindow.

Figure 5. Four focus-offset fields were created per wafer, and demonstrated that the 2401 could detect a process window of 0.7 µm, making it suit-

able for monitoring the stepper for focus-offset excursions.



The investigation of leveling offsets was similar. Waferswere created with four offset fields, this time withincreasing tilts on both the “X” and “Y” axes (Figure6). Again the offsets showed up clearly using the 2401.In the “X” axis, the 2401 detected tilt offsets of 20µrad and greater, while in the “Y” the 2401 detectedoffsets of 35 µrad and greater. By calculating the effec-tive focus offset at the edge of the titled fields thedetectable process window is in the order of ±0.35 µmoffset at the edge of a 22 mm field. This is comparableto the focus offset detectable process window and againsuggests that the 2401 can be used to detect tilt excur-sions outside of the stepper’s own process window.

Return on investmentAt the conclusion of the evaluation, the return oninvestment was calculated by comparing manual versusautomated after-develop macro inspection. The calcula-tions were based on data from the eight layers evaluated,which were designed to represent the whole process. Itshould be noted that the product studied was a stablemain runner. The yield kill rate of each defect type wasconsidered using historical rework data and comparedwith the rework rate that resulted from using the2401. The model did not include any of the savingsthat would be gained through using fewer operators orby taking into account the shorter time to detection ofdefect incidents. Furthermore, the opportunities for

savings are expected to be greater on shrinking tech-nologies having higher wafer and die costs. Even usingthese conservative assumptions and a low average sellingprice product, potential savings of over $66,000 permonth were calculated from using the 2401.

SummaryThe KLA-Tencor 2401 was installed in less than 10days. Twelve operators and three engineers were trainedon the system and provided positive feedback about itsease of use and production integration. The 2401 provedto be 10 times more sensitive than manual inspection,with 12 out of 13 critical defect types captured reliably.The thirteenth type is expected to be captured as soonas the next software version is installed. This systemdemonstrated potential for a very simple focus-exposurematrix utility and promising capability for monitoringsteppers for focus and tilt excursions. The return oninvestment is quite aggressive even for a low averageselling price product. Finally, NEC was able to reducescrap and reduce excursion detection time, whichtranslates to better yield and profitability.


Figure 6. Four tilt -offset fields were created per wafer, and demonstrated that the 2401 could detect a process window of 20 - 35 µrads, depending

on the direction of the grating. This sensitivity suggests that the 2401 would be suitable for monitoring the stepper for tilt excursions.

circle RS#034

A WHOLE NEW WORLD iSupport IN CUSTOMER SUPPORTA WHOLE NEW WORLD iSupport IN CUSTOMER SUPPORT

W O R L D W I D E S U P P O R T O P E R AT I O N Sw w w. k l a - t e n c o r. c o m circle RS#033


&AQiSupport™ — the Most Advanced, On-line Customer Support ProgramAn Interview with Beth McAllister, Senior Director ofMarketing, Worldwide Support Operations.

S E C T I O N S

Q What is iSupport and why isit important to our semiconductorindustry customers?

A iSupport is a first-of-its-kind supportoffering providing a comprehensive,fast, secure and cost effective on-linesupport solution for KLA-Tencor tools.With iSupport, most assistance thatdoesn’t require parts replacement canbe quickly and completely resolved on-line. This is accomplished by installinga diagnostic server (iDM) to monitorour tools in the customer’s fab. Thediagnostic server is connected to KLA-Tencor’s secure On-line Support Centerwhere authorized support personnelprovide immediate help at the first signof an equipment problem. The iSupportProgram extends the availability of KLA-Tencor’s current on-site support teamwith secure on-line support.

The ability to provide rapid on-lineassistance to our customers, to correctequipment problems faster and moreefficiently, and to provide real-timeequipment performance and processdata results in higher tool productivity,improving Cost of Ownership andasset utilization. In addition, iSupportaccelerates the ramp for new tools andnew fabs by expediting resolution of

start-up issues, reducing steep learningcurves and providing hands-on assis-tance for new users.

Q How does iSupport Work?

A The most recent KLA-Tencor toolsare specifically designed for iSupport.The KLA-Tencor diagnostic server isinstalled in the customer’s fab and con-nected to KLA-Tencor tools through thefab network. The iDM provides continu-ous monitoring of connected tools forautomated fault detection and alert,data storage and analysis for reportingand trending, and secure and safeaccess to our On-Line Support Center(OSC). The security features built intoiSupport ensure every possible safe-guard has been taken; and the cus-tomer is in complete control of thesecure information at all times. At thefirst notification of an equipment prob-lem or at the customer’s request forassistance directly from the tool, theOSC’s technical and applications engi-neers log onto their central server andthe iDM to access the KLA-Tencor toolon the customer’s fab network. TheOSC desktop mimics the tool keyboardand display monitors on the tool,enabling the OSC engineers to accesslog files, error messages, recipe para-

meters and sensor data, just as if theywere actually in the fab. From there,the engineers can assess system perfor-mance, execute diagnostics and assistwith recipe setups.

Q Why iSupport?

A The need for e-diagnostics capabil-ity has recently become a focus ofsemiconductor manufacturers. KLA-Tencor, however, realized almost twoyears ago that with technology becom-ing increasingly complex and morecapital intensive, customers wouldneed cost-effective, around-the-clock,expert support at every location tomaximize the return on their investment.After benchmarking several industriesfor best-in-class support, KLA-Tencor initiated iSupport and is now the firstcompany to bring a fast, comprehen-sive, secure, on-line solution to thesemiconductor industry. iSupport ismuch broader than e-diagnostics, pro-viding continuous tool monitoring andreporting, as well as automated earlydetection of system problems at thecustomer site.

For more information, please visitour Internet site: www.kla-tencor.com


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The 0.13 µm semiconductor manufacturing generation, shipping as early as 2001, will have transistor gate structures assmall as 100 nm, creating a demand for sub-10 nm gate linewidth control. Linewidth variation consists of cross-chip,cross-wafer, cross-lot, and run-to-run components. In this work, we explore spatial dependencies across the lithographic fielddue to reticle error and across the wafer due to wafer and chuck nanotopography. Both sources of spatial variation can causecollapse of the lithographic focus window near the limits of resolution, resulting in CD excursions for gate structures inhigh-performance microprocessors. Our work supports the contention that photolithography-induced defects may become theprimary source of yield loss for the 0.13 µm generation and beyond.


Collapse of the Deep-UV and 193 nmLithographic Focus Window

Yield Impact of Cross-Field and Cross-Wafer CD Spatial Uniformity

Kevin Monahan, Pat Lord, Waiman Ng, Hubert Altendorfer, George Kren, and Scott AshkenazKLA-Tencor Corporation

© 1999 IEEE. Reprinted, with permission, from the Proceedings of the 1999 IEEE Symposium on Semiconductor Manufacturing; 1999; pgs 115-118.

As an extension of previous work on temporalvariation1, we are currently exploring spatialdependencies across the lithographic fielddue to reticle and lens error and across thewafer due to wafer nanotopography andchuck flatness. The new study uses data froma comprehensive set of measurement tech-nologies, including reticle and wafer CDSEM metrology, phase-shift focus metrology,cross-wafer interferometry, differential inter-ference contrast metrology, and macro defectinspection. We have found that, as in the caseof temporal variation, spatial variation cancause collapse of the common CD-defocuswindow near the limits of lithographic res-olution, particularly for the gate and contactstructures in high-performance devices.

There are many sources of spatial variationthat contribute to process window collapse.

These include overlay error, reticle error, lens error, andfocus errors. To predict yield, we treat each of them asdefects with a specific “kill potential”. One example isthe recent use of logistic regression to correlate overlayerror with the probability of device failure2. In such aunified defect scenario, yield may be expressed as aproduct of survival probabilities given by

where lambda is the defect kill potential for defects oftype i, n is the number of defects per die of type i, andN is the total number of defect types. In the case ofparametric defects, the kill potentials may be functionsof measured parameters such as overlay and criticaldimension (CD) or unknown parameters, such as expo-sure variation and local defocus, which are observedindirectly in the form of CD excursions. Generally, we

Y = ∏(1 – λi) ni

i=1

N


improve the accuracy of the lithographic yield modelby identifying those defects with the highest killpotential, or even those that pose a quantifiable eco-nomic risk by affecting bin yield3.

Lithographic defocus is likely to be an indirect sourceof CD defects with high kill potential, particularly asexposure wavelengths decrease from 248 nm to 193 nm,157 nm, and even 13 nm. This is primarily due to thereduction of the Raleigh focus window with shorterwavelength. CD and defocus are highly interactive, asshown in the example of Figure 2. Reticle CD errors oroverlay errors that force reduction of the overall CDerror budget will have a negative effect on the allow-able range of defocus.

Results and discussionA comprehensive “systems approach” was used to ana-lyze complex spatial uniformity data from reticles andwafers. At least five state-of-the-art methodologieswere applied to the problem:

• Lithographic reticle and optical characterizationusing reticle and wafer CD SEM metrology

• Phase-shift focus measurement using optical overlaymetrology and model-based analysis

• Wafer thickness metrology using wafer-scale trans-mission interferometry

• Wafer surface nanotopography using differentialinterference contrast metrology

• Cost-effective screening using darkfield and bright-field macro inspection technology

Our results show that the sources of CD error due tolithographic defocus can be de-confounded using thiscomprehensive approach. Reticle CD error, for example,can be stripped out using CD SEM measurements.

Confounded lens, wafer, and chuck components can beseparated using a phase-shift focus monitor, combinedwith double-sided, wafer-scale interferometry and single-sided, differential interference contrast metrology.

Reticle and Wafer CD SEM MetrologyFocus errors create spatial CD non-uniformity. Thesecan be due to the reticle, the projection optics, and thewafer/chuck surface upon which the pattern is printed.CD SEMs can be used to map cross-field and cross-wafererrors, creating model-based CD uniformity maps andgenerating feedback to the stepper/track systems forcorrection of systematic spatial variation. Examples ofcross-field CD error, measured using a specially adapted

2480

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Figure 1. Collapse of the 0.5λ/(NA)2 Raleigh focus window as litho-

graphic exposure wavelength is decreased. Values for the numerical

apertures are assumed to be 0.7, 0.7, 0.7, and 0.25, respectively.

The EUV wavelength is 13 nm.

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140150

Figure 2. CD-defocus response surface (equation below) for isolated

lines in negative resist (raw data not shown). Underexposure was used

to get 130 nm gate structures (90 percent exposure dose, E) at the

expense of low focus latitude and high sensitivity to exposure variation

under conditions of defocus (D). The outer and inner boxes show the

collapse of the focus window as the CD tolerance is tightened by

50 percent.

y(E,D) = (b0 = b1D + b2D2) + —(b3 + b4D + b5D2)


1E


CD SEM, are shown in Figure 3 (reticle) and Figure 4(wafer). In this case, the total CD variation on the waferis due to reticle error, lens error, and nanotopographyof the chucked wafer. Since the reticle and wafer CDsare measured in the same SEM, the reticle error isremoved from the wafer data without heterogeneoustool matching.

Registration-Based Phase-Shift Focus MetrologyData from a phase-shift focus monitor characterizesfocal plane deviations within the field and from field tofield across the wafer. A monitor reticle with asymmet-rically phase-shifted overlay targets is used in conjunc-

tion with a high-speed overlay tool to generate artificialregistration errors that are a linear function of litho-graphic defocus. Fitting the data to a model enablesthe quantitative assessment of lens tilt, field curvature,astigmatism, scan errors, wafer/chuck flatness, lensheating, barometric effects, and other lithographicfocus anomalies. The cross-field mapping capability ofthe phase-shift focus monitor is shown in Figure 5.Figure 6 shows the same capability across a wafer. Thetotal range is ±200 nm, including top surface nanoto-pography, wafer thickness variation, and chuck non-uniformity.

Figure 3. Cross-field CD SEM data on a reticle, showing radial

dependence of the CD values in nanometers.

Figure 4. Cross-field CD SEM data on a wafer showing apparent

“tilt” in the DUV optics. Reticle CD error has been removed. Scale is

in nanometers.

Figure 5. Cross-field response surface generated with data from a

phase-shift focus monitor. The root-cause of CD error is often traced to

cross-field defocus effects arising from wafer/chuck nanotopography.

Figure 6. Cross-wafer phase-shift focus data includes top surface

nanotopography, wafer thickness variation, and chuck non-uniformity.

Range is ±200 nm.



Cross-Wafer Transmission InterferometryCross-wafer interferometry can be used to separatethickness variation and surface nanotopography fromchuck-induced deformation. In this case, monochro-matic light is projected through the wafer and interfer-ence from the top and bottom surfaces of the wafer isused to determine thickness. Data for a 300 mm waferpolished on both sides is shown in Figure 7. The totalrange is ±200 nm. Measured in this way, the thicknessdata is confounded with top surface nanotopography.

In general, nanotopography with spatial periods below5 mm (the slit-width of a scanner) and amplitudes inthe hundred-nanometer range can create significantfocusing errors in scanning lithography. A 193 nmscanner with 0.7-N.A. optics will have a theoreticaldepth-of-focus of about ±200 nm for dense lines, andless for isolated features.

Nanotopography at high spatial frequencies can exceedthe dynamic range of a scanner’s in-situ focusing sub-systems. If the focus errors are large, the resulting CDvariations can create severe device yield and speed bin-ning excursions, particularly in high-performancemicroprocessors.

Differential Interference-Contrast (DIC)MetrologyDifferential interference-contrast metrology uses thephase response of light reflected from the top surface ofthe wafer. Along with micro-tilt sensing, it can be usedto separate top surface nanotopography from waferthickness variation. In our case, the DIC metrology is

implemented on a high-speed, unpatterned-filminspection tool. A high-resolution profilometer is usedfor height calibration. As shown in Figure 8, DICmetrology responds to the higher spatial frequenciesthat could be missed by cross-wafer transmission inter-ferometry. The total range of the top surface nanotopog-raphy is ±30 nm, much of which is due to “polishingchatter” arising from a process excursion that couldhave gone unnoticed without the DIC monitor. Insome cases, we have observed top surface nanotopogra-phy with ranges below ±3 nm. This level of wafer sur-face quality is costly, but it may become critical forchemical-mechanical planarization (CMP) used inadvanced shallow-trench isolation (STI) technologies.

Whole-Wafer Macro-Defect InspectionGross defocus on patterned wafers is generally visibleas a “hot spot” during macro-defect inspection. Hotspots can sometimes be seen in brightfield illumina-tion, but they are much more visible in darkfield illu-mination due to scattering from pattern defects. Hotspots often result from extreme nanotopography causedby particles on the backside of a wafer, a problem thatcould become worse as the industry makes the transi-tion to double-sided polishing on 300 mm wafers.These gross focus excursions can be detected usinghigh-speed, macro-defect inspection tools as monitors.

Figure 7. Cross-wafer interferometry isolates top surface nanotopography

and thickness variation from chuck non-uniformity. Range is ±200 nm

on 300 mm wafer.

Figure 8. Dif ferential interference metrology isolates top surface

nanotopography. Range is ±30 nm.



Since backside particles produce pattern defects overrelatively large areas, the 50-micrometer sensitivity of amacro inspector is more than sufficient to detect thisform of wafer contamination. A typical darkfield imageof a hot spot is shown in Figure 9.

SummaryWavelength reductions and increases in numericalaperture have extended the life of optical lithography,but the improvements in resolution come at the cost of reduced depth-of-focus, as shown by the Raleighequation below:

DOF = 0.5

where λ is the exposure wavelength and NA is thenumerical aperture of the optics.

The wavelength reduction strategy for extending opti-cal lithography will have the following consequences:

• Reticle error will become a larger part of the CDerror budget, forcing narrower lithographic processwindows for focus and exposure.

• Focus windows will dwindle as the CD error bud-gets shrink and theoretical depth-of-focus drops inproportion to exposure wavelength.

• The need for monitors may increase as spatial CDvariation and nanotopography effects detract fromthe focus window and impact yield.

• The kill potential of both direct (CD) and indirect(defocus) parametric defects will need to be quanti-fied more accurately using robust statistical methods4.

AcknowledgementsWe are in debt to Ken Schroeder, Robert Lee, Jan Waluk, andmany others at KLA-Tencor for their encouragement and contributions to this work.

References1. K. M. Monahan and P. Lord, “Lithographic focus stabi-

lization for model-based gate CD control systems”, Proc.ISSM, Tokyo, October 7-9, 1998, pp. 347-350.

2. M. E. Preil, J. McCormak, “A new approach to correlat-ing overlay and yield”, Proc. SPIE, Vol. 3677, 1999.

3. K. M. Monahan, P. Lord, C. Hayzelden, and W. Ng, “Anapplication of model-based, lithographic process controlfor cost-effective IC manufacturing at 0.13 micron and be-yond”, Proc. SPIE, Vol. 3677, p. 435 (1999).

4. R. Martin, X. Chen, and I. Goldberger, “Measuring faboverlay programs”, Proc. SPIE, Vol. 3677, p. 64 (1999).

Figure 9. Whole-wafer, darkfield macro inspection data showing

focus “hot spot” in the upper left quadrant.

λNA2


44 Summer 2000 Yield Management SolutionsSummer 2000 Yield Management Solutions

The manufacturing environment that existsin today’s high volume ASIC productionfabs presents multiple logistic challenges tothe photolithography sector. In such fabs, itis common to have hundreds of indepen-dent devices running concurrently. This, inturn, corresponds to having thousands oreven tens of thousands of reticles active atany one time. Typically, each individualreticle will require independent recipes forstepper exposure, and the subsequent mis-registration and critical dimension metrolo-gy steps. In such an environment, recipecreation and management become verylarge and critical tasks.

In order to maximize tool utilization andminimize cycle time impact, recipe setuptime must be minimal. Furthermore, inorder to ensure the robustness and stabilityof a large number of recipes, the number ofpersonnel involved in recipe creation and maintenance should be mini-mized. To meet these requirements, therecipe management system must be fast,simple to use, and capable of easy replica-

tion and/or distribution of recipes to multiple processtools within the fab. In an ideal case, the system shouldbe capable of creating recipes off-line from the produc-tion tool without requiring a wafer, and be able to dis-tribute recipes to process tools via network connections.

Historically, metrology tools have not been capable ofmeeting this ideal case, mainly due to restrictionsplaced on metrology equipment vendors by their cus-tomers. With limited real estate available in scribelines, chip manufacturers have pushed metrology ven-dors to design flexible pattern recognition systems thatdo not require a specific alignment target to be placedin the scribe. As a result, most metrology systems on themarket today require that recipe setup be performed onthe tool using a production wafer in order to acquirethe necessary pattern recognition and measurement sitetemplates with the proper illumination and other setupconditions.

The limitations described above can be overcome to alarge degree by using a system that allows for storageof “master” templates for pattern recognition and mea-surement site setup. Furthermore, by using some fore-thought, a standard pattern recognition structure canbe designed for use by multiple types of metrology

Tool cost of ownership and manufacturing productivity continue to be key factors in equipment selection discussions. Productsthat differentiate themselves by maximizing tool utilization and minimizing engineering resources make the best economicimpact in a time of increasing fab capital costs. This paper will demonstrate the use of a single off-line recipe databasemanager (RDM) in conjunction with multiple optical misregistration measurement tools for the purpose of misregistrationrecipe creation and management in a high volume ASIC manufacturing line.


Enhancing Overlay MetrologyProductivity and Stability Using an Off-line Recipe Database Manager

by Stephen J. DeMoora, Stephanie Hilbun, George P. Beck III, Kristi L. Bushmana, Russell D. Fields, Texas Instruments Incorporated Robert M. Peters, Todd E. Calvert, KLA-Tencor Corporation


systems (overlay, CD SEM, film thickness, etc.), whileminimizing the scribe line space used. By using standardstructures, and taking advantage of process similaritiesacross multiple devices, a system can be developed thatallows for nearly 100 percent off-line, waferless recipecreation. The strategy for using such a system to handlerecipe creation and management for overlay metrologysystems, along with the associated productivity andrecipe stability improvements will be discussed for theremainder of this paper.

Recipe and element management strategyFor the work presented in this paper, a KLA-TencorRecipe Database Manager (RDM) was used in conjunc-tion with multiple KLA-Tencor overlay metrology sys-tems installed in Texas Instruments’ DMOS 5 produc-tion facility. The RDM consists of a server with a data-base for storing recipes and recipe elements withclients which allow for the creation, editing, and distri-bution of recipes. The server is linked to each of theoverlay systems via network connection to allow foreasy recipe distribution. The RDM database employs alibrary structure that allows for recipe elements to beeasily manipulated and also allows multiple recipes toshare the same element. Inside the RDM database, thestandard recipes are broken down into a series of fourseparate recipe elements. (Table 1.)

The first goal is to develop a strategy that minimizesthe total number of elements required to support allrecipe creation for the fab. Figure 1a describes an ASICfab scenario with two distinct product families. Theproduct families are differentiated by unique manufac-turing process flows. Within a single product family,there are several different devices that run on the same

process flow. Outside of using a different reticle set andthe associated wafermap layout, each device will see theexact same process steps, and thus should appear opticallyidentical.

By standardizing pattern recognition and miss-registra-tion targets, one can take advantage of the similaritieswithin the process flow. As Figure 1b illustrates, at aspecific process level, the same single alignment andsingle test element can be used in the recipe for everydevice under the same process flow. All that needs tobe changed is the vector location of the pattern recog-nition target and each misregistration target withrespect to the center of the field.

Figure 1b also illustrates that for a single device, thesame wafermap element can be used at each processlevel within that device. RDM parameters generallycontain information that is global to the manufacturingfacility, such as wafer size, notch orientation, etc. Thusonly a handful of specific parameter elements (typicallyless than 5, possibly as few as 1) are necessary to coverall recipes running within the fab.

The test case outlined in Figure 2 demonstrates theeffectiveness of the above strategy. For the test casespecified (three process flows, each with 20 layers, andeach having 100 devices running under the flow), 6000recipes are necessary. However, these 6000 recipes canall be created using as few as 421 distinct elements.

Productivity improvementMinimizing the number of recipe elements using thestrategy defined in the previous section results in sig-nificant productivity improvements for the fab. When


Process Flow X Process Flow Y

Device Device ••• Device Device Device ••• DeviceX1 X2 X3 Y1 Y2 Y3

Level 1x Level 1x Level 1x Level 1y Level 1y Level 1y



• • • • • •• • • • • •• • • • • •

Level Nx Level Nx ••• Level Nx Level Ny Level Ny ••• Level Ny

Figure 1a. ASIC fab example of multiple product families.

Parameters Wafer MapRun time options Wafer orientationWafer selection Grid layout and offsetData output options Step pitch

Alignment TestsPattern recognition image Misregistration target imagePattern recognition location* Measurement options

Measurement locations*

Table 1: RDM recipe element structure and content.

*Denotes a parameter that is associated with the element, but is physically linkedto the recipe, not the element.


a new process flow is introduced into the fab, therecipes for the initial device will need to be written onthe tool itself with a wafer present, as alignment andtest elements will not yet exist in the database.However, as these initial recipes are created, they areimported into the database. Once in the database, thealignment and test elements can then be used as the“master” elements to create recipes for each successivedevice running under the same process flow. All suc-cessive recipes in the process flow can thus be writtenoff-line and waferless.

The productivity benefits from this process are realizedon three separate fronts. First, using the databaselibrary of elements, recipe creation time is significantlyreduced. Waferless recipes in RDM can be created in

approximately five minutes as opposed to approximately30 minutes when written on the tool. This time savings,along with the relatively small number of elementsthat need to be maintained, allows for reduction in thenumber of personnel required to handle recipe creationand maintenance. For example, implementing RDMhas allowed DMOS 5 to reduce the number of peopleresponsible for new recipe creation and maintenancefrom less than 10 down to 1.

Second, since waferless recipe creation is now possible, asignificant amount of tool time previously used for setupis now made available for production use. Figure 3 shows

Process Flow X Process Flow Y

Device Device ••• Device Device Device ••• DeviceX1 X2 X3 Y1 Y2 Y3




• • • • • •• • • • • •• • • • • •

Level Nx Level Nx ••• Level Nx Level Ny Level Ny •••Level Ny

Map_Dev Map_Dev_X1 _Y1Map_Dev Map_Dev

_X2 _Y2Map_Dev Map_Dev_X1 _Y1

Align_FlwX_Lev_1Test_FlwX_Lev_1



Align_FlwX_Lev_NTest_FlwX_Lev_N

•••

Align_FlwY_Lev_1Test_FlwY_Lev_1



Align_FlwY_Lev_NTest_FlwY_Lev_N

•••

Figure 1b. Strategy for selecting common recipe elements for dif ferent process flows and devices.

Process Flow X Process Flow Y Process Flow Z Tab Total

# Device 100 100 100 300# Layers 20 20 20 60

# Recipes (100)(20)=2000 (100)(20)=2000 (100)(20)=2000 6000

# Parameter Elements 1* 1* 1* 1# Wafermap Elements 100 100 100 300# Alignment Elements 20 20 20 60

# Test Elements 20 20 20 60

Total # Elements 141* 141* 141* 421

*The same parameter element may be used for the entire fab

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Eng. Util. due to non-recipesetup items

0.00%

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Figure 2. Element selection strategy vs. number of recipes. Figure 3. Average engineering utilization.


the engineering utilization as tracked by on-boardautomation log files for four KLA-Tencor overlay sys-tems used in Texas Instrument’s DMOS 5 wafer fab.Prior to April 1999, DMOS 5 was performing allrecipe setup directly on the overlay systems. Over May-June 1999, RDM was implemented, employing theelement strategy as defined in Section 2. By October1999, the average engineering utilization on the 4tools dropped to 2.35 percent from the initial Aprilvalue of 8.86 percent. Based on a 720-hour month,these percentages correspond to picking up almost 47hours of production availability per overlay machineper month as a result of implementing RDM.

The third productivity benefit is tied to manufacturingcycle time. If waferless setup is used for a new device,recipes can be created and distributed to the tools inthe fab in advance of lots being released into the line.As a result, lots sitting in queue waiting for overlayrecipes to be written do not add cycle time. While nohard data has been obtained to quantify the exact effectof using RDM on cycle time, the following estimatescan be made. To write a recipe on the tool takesapproximately 30 minutes. Furthermore, most oftenthe tool is not available, nor is there a person readilyavailable to write the recipe at the exact time when thelot arrives at the overlay process step. A conservativeestimate would add another 30 minutes of queue timeper level. If a typical high-end device requires overlaymeasurement at approximately 20 layers, this adds atleast 20 hours to the cycle time for that lot. In the caseof the prototype lot for a new device, cycle time is crit-ical for verifying design functionality. Therefore, a one-day cycle time improvement provides significant returnon investment to the fab.

Tool induced shift (TIS) stabilityAlong with the productivity improvements seen withRDM, recipe stability improvements should be seen aswell. By using a “master” element strategy, person-per-son and tool-tool variation in the alignment and mis-registration test setups can be minimized, if not com-pletely eliminated. One of the areas in which stabilityand consistency can be improved is tool induced shift,or TIS1. TIS tends to be sensitive to the illuminationand focus conditions present on the tool during mis-registration measurement setup2. Therefore, if multipletools and/or people are involved in recipe setup, it isextremely difficult to maintain consistent TIS resultsfor the same process level across multiple devices.

Theoretically, if a single test element is used at thesame process level for multiple devices under the sameprocess flow, then on a specific overlay tool, the TISvalues for that process level should be the same for eachdevice using that element. Some preliminary data hasbeen taken to verify this hypothesis. Recipes for twodevices running on the same process flow were set-upvia RDM using the same “master” test element. Theserecipes were also set up to measure and record the TISvalue on every production lot run with that recipe. Therecipes were released to standard production on allKLA-Tencor overlay tools in DMOS 5 and allowed torun and collect TIS data for one month. Figures 4a, 4band 5a, 5b summarize some of the results from thisexperiment.

Figures 4a and 4b show the TIS values for X and Ymeasurement orientations for a contact process level forboth devices across four overlay systems at DMOS 5.The values represent the mean of the TIS values fromall production lots run through each tool during the

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Figure 4b. Y-TIS values for contact level across four overlay tools.

Figure 4a. X-TIS values for contact level across four overlay.


one-month test period. On all four tools, the TIS valuesfor Device A and Device B match within 2.5 nm, andin all but one case, match to less than 1 nm.

Figures 5a and 5b summarize the TIS values for X andY measurement orientations for a combination of sixprocess levels for both devices on a single overlay system in DMOS 5. Again, the values represent themean of the TIS values from all production lots runthrough each tool during the one-month test period.For this case, at all process levels, the TIS values forDevice A and Device B match within 3 nm, and in allbut one case, match to less than 1 nm.

SummaryTo summarize, a KLA-Tencor Recipe DatabaseManager (RDM) system was used in conjunction withmultiple KLA-Tencor overlay metrology systems tosignificantly improve manufacturing productivity andrecipe stability in Texas Instruments’ DMOS 5 waferfab facility. The strategy employed to minimize thenumber of recipe elements required to create and main-tain all recipes in the fab was discussed. Through theimplementation of this strategy, a 6.5 percent improve-ment in tool availability, corresponding to almost 47hours per tool per month was realized in DMOS 5 overa time frame of six months. Associated improvementsin material cycle time were also discussed. Data wasalso presented to verify that using the RDM systemproduced recipes with highly consistent tool inducedshift (TIS) results, typically within 1 nm between recipesusing the same overlay test element. Future work willinclude a more in depth analysis of TIS stability, as wellas investigating further productivity improvementsthat may be attained by fully automating the recipecreation process by utilizing CAD output data and factory automation.

AcknowledgementsThe authors would like to acknowledge Mark Smith and Tim Zommermaand of KLA-Tencor, and Russ Funk ofRFSolutions for their assistance in collecting and analyzingthe automation logs from the overlay metrology systems.

The authors would like to acknowledge the management atTexas Instruments’ DMOS 4 and DMOS 5 production facilities and at KLA-Tencor for their support of the workpresented in this paper.

References1. Daniel J. Coleman, Patricia J. Larson, Alexander D. Lopa-

ta, William A. Muth, and Alexander Starikov, “On the Ac-curacy of Overlay Measurements: Tool and Mark Asym-metry Effects,” SPIE Vol. 1261, pp. 139-161, 1990

2. Moshe E. Preil, Bert Plambeck, Yoram Uziel, Hao Zhao,and Matthew W. Melvin, “Improving The Accuracy ofOverlay Measurements through Reduction in Tool andWafer Induced Shifts,” SPIE Vol. 3050, pp. 123-134,1998

Reprinted with permission from SPIE. Presented at SPIE ‘00 Microlithography.Vol. 3998-115.

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Figure 5a. X-TIS value for six dif ferent process levels on one tool.

Figure 5b. Y-TIS value for six dif ferent process levels on one tool.

circle RS#021

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That’s why we’re developing the new applications

you’ll need to control low-κ technologies, and

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Equally important to process control is tracking basictool performance once it is integrated into a productionline, which ensures that the expected precision is infact realized from the metrology tool on a daily basis4.

Even when the performance of an individual tool isverified, it is also necessary to ensure that multiplemetrology tools in the production line will deliver thesame results.

Matching multiple CD SEMs in one or more manufac-turing locations becomes even more important in largemanufacturing facilities. Many fabs have numerous CDSEMs that are operated by separate groups within thefacility, and production lots can be directed to variousareas with available SEM capacity. Additionally, processdevelopment facilities must transfer new devices andprocesses to production environments, which requiresthe measurement of established devices on different CDSEMs. In both cases, there is a strong requirement forall CD SEMs to consistently match to within a prede-termined specification.

Method: Setting up the match studyOnce basic tool performance has been established in themanufacturing facility, effective matching programsmust be relatively simple and not require specific per-sonnel. Realistic verification techniques require mini-mizing time and effort, whether on start up, integratingnew production layers, technology families or new CD

Matching Automated CD SEMs inMultiple Manufacturing Environments

by John Allgair and Dustin Ruehle, Motorola, John Miller and Richard Elliott, KLA-Tencor Corporation

As critical dimension (CD) design rules for semiconductor manufacturing become increasingly stringent, manufacturers ofautomated CD SEMs are developing systems with improved linewidth measurement repeatability and reproducibility 1. Theultimate technical performance of CD SEMs, however, is very much dependent on consistent and tight operational controls.This is especially true in multiple tool manufacturing environments where system matching is required to preserve properoperation.

The matching and repeatability of CDSEMs can be evaluated using a standarddaily monitor wafer that tracks the majorsystem components that impact performance.By using a method of statistical analysis onthe data, matching can be verified immedi-ately. This control procedure tracks toolstability, provides a common CD SEMlength reference, and enables the seamlessuse of multiple CD SEMs within a singlemanufacturing environment or betweenseparate manufacturing environments,without significantly increasing tool qualification time.

Shrinking linewidths and manufacturing challenges The latest production devices have criticaldimensions well below 0.25 µm, and futuregenerations are targeted to have transistorgate structures at or below 100 nm. Thevalue of tight dimensional control at thegate level is well understood, with the dollar value estimated to be as much as$7.50 in average selling price (ASP) pernanometer of difference in gate CD2.

An automated CD SEM can demonstratesufficient repeatability for effective processcontrol of these leading edge technologies3.



The eight layers used in this study are specified in thefollowing table:

All wafers were measured once on each tool, with themean value calculated from nine sites measured on eachwafer. In addition to these eight layers, a resist contactlayer with nominal features of 330 nm in diameter wasanalyzed to evaluate contact hole imaging capabilities.

Performing the matching testPrevious matching analysis methods have comparedmeasurements collected over an extended period oftime. Typically one or two wafers are used. The wafersare measured on each system every day for a period ofdays, and the differences between wafer means for eachday are compared to estimate system matching.6,7

The time and effort required to gather several days worthof measurements from each SEM using an extensivesampling plan is often prohibitive in a manufacturingenvironment. In addition, when evaluating matchingbetween facilities, the technique becomes completelyimpractical.

A more practical strategy for estimating system matchingis to apply past knowledge of within-system performanceto the matching analysis. This can alleviate the need torun tests on multiple tools over multiple days.

SEMs; or when re-qualifying systems after significantmaintenance activity. Fortunately, a short daily qualifi-cation procedure that monitors CD stability on a singlewafer is sufficient to ensure matching across all tools.

First, it is necessary to verify that each individual systemis operating to specification, and that the resolution ofeach SEM is within specification and the imaging ofeach system is comparable. Next, a common set of wafersto which all of the SEMs can be calibrated is needed.

In the following study, the standards were based on thepitch of a nested line structure on a series of etchedpoly wafers. Using the average pitch of a series of sitesfrom these wafers is a practical, easy-to-implement calibration option in the absence of a traceable lengthstandard for SEMs. Wafer-to-wafer variation in thepitch structure used for calibration was measured to beless than 1 nm. Comparison of these standard wafers toan early version of a proposed NIST CD SEM pitchstandard showed the absolute calibration to be off byless than 1 percent.

Using an etched wafer for calibration also has theadvantage that closely matched wafer standards can bekept in close proximity to each SEM to simplify dailytool qualification and stability monitoring. The waferscan be easily transferred between fabs, serving as aportable length standard to further check CD matchingbetween facilities. The wafers used in this study shouldhave a useful lifetime of 40 months if care is taken torotate measurement sites to avoid CD growth due torepeated measurements5. The six CD SEMs in thisstudy were located in four physically distinct bays intwo different manufacturing facilities. As a result, fourseparate calibration/tool qualification wafers were usedfor the calibration of the tools.

Measurements were taken on two KLA-Tencor 8100XPCD SEMs and four KLA-Tencor 8100 CD SEMs. Toensure operational consistency, all layers used in thisstudy were measured with a single beam setting of600eV landing energy, with a consistent beam currentsetting for each of the six tools.

The wafers used in the study were taken from a pro-duction device and represent a variety of layers, includ-ing resist and etched features. Matching performancewas evaluated on eight layers including one of the cali-bration wafers.

Type CD(nm) Feature TypeEtched Oxide 335 Dense Line

Resist on Nitride 325 Dense Line

Etched Nitride 380 Dense Line

Resist on Poly <250 Dense Line

Etched Poly <250 Dense Line

Resist on Metal 475 Dense Line

Etched Metal 475 Dense Line

Etched Oxide 280 Contact


In order to test for a statistically significant differencebetween two populations of data at the level of thematching specification, we need estimates of the majorsources of CD variation in the tools. The total measure-ment variation can be written as:

σT2 = σM

2 + σL2 + σD

2

where,

σM2 = the variation due to matching between systems

σL2 = the variation within a single system over time

(long-term component)

σD2 = the variation within a single system between

multiple measurements and wafer loading (dynamicprecision)

The combination of terms σM2 and σL

2 correspond to“reproducibility” while dynamic precision (σD

2) corre-sponds to “repeatability”8.

Within a single system, only the long-term anddynamic components are relevant. For this study, astandard tool acceptance test was used to quantify thedynamic precision of a single measurement on the sys-tem for each particular layer. To measure σD , a singlejob was run several times in succession with the waferfully unloaded from the system between each run. When

measuring the mean of the measurements on a particularwafer, the dynamic component of the variance of a wafermean is reduced by a factor of 1/√N when N points areaveraged to obtain a wafer mean. The subsequent estimatefor the variance in the estimate of the wafer mean, µ,measured on a single system is:

σµ2 = σD

2/√N + σL2.

With sufficient sampling per wafer (30 points perwafer for example), the contribution of the dynamicprecision term becomes negligible and we can focus onthe long-term variation as the major source of uncer-tainty in the wafer mean (Figure 1).

The uncertainty due to long term variation cannot,however, be reduced by increased sampling on a singlerun or by multiple runs in a short period of time.Multiple measurements are required over an extendedperiod of time. These measurements can be performedon the wafers to be matched or, alternatively, on a sepa-rate wafer used to track the CD stability of the tool.The second approach has the advantage that the longterm variation for each system can be monitored as partof the daily tool qualification. This is the approachadopted in this study.

Because many points are sampled on a wafer, the varia-tion in the estimation of a particular wafer mean shouldbe roughly equal to the long-term precision specificationof a single system. For example, for the 8100XP system,the long term specification is 5 nm 3σ, or about 1.7 nm1σ. Analysis of data obtained from the daily qualificationof the SEMs verifies that the systems do, indeed, operatewithin this long term specification.

With this understanding of the variance in the meanfor a single system, the most common test used for thecomparison of two populations were examined, the stu-dent’s t-test9. For two systems, we wish to test thehypothesis that the measurements do not differ by morethan the matching specification. (The null hypothesisis that the means do not differ by the predeterminedamount.) For this example, we will use the matchingspecification for the 8100XP of 5 nm, mean to mean (∆M).The test statistic for significant differences between wafermeans measured on two different systems, ∆µ is thus:

∆µ > σL*t + ∆M

or

∆µ > 1.7 * 1.96 + 5.0

SEM A SEM B

95% confidence interval for ∆

α/2 = 0.025

1.96σL 1.96σL


Figure 1. Typical distribution of CD measurements due to long-term

system variation of two SEMs. The means of these two distributions

can be considered significantly dif ferent when the overlap between

the distributions is smaller than a predetermined value. The width of

each distribution is determined by σL.


using the t-value appropriate for a 95 percent confidenceinterval10. Therefore differences in wafers means ∆µthat satisfy

∆µ > 8.3 nm

can be considered significantly different at the level ofthe 5 nm matching specification.

It is important to consider the application of this testvalue for the wafer means. Each individual pair of sys-tems is evaluated at each layer to this maximum mea-sured matching value. This ensures that no two systemsdiffer with statistical significance by more than 5 nm.

Understanding the resultsFigure 2 depicts the distribution of the pair-wise dif-ferences between the wafer means measured on six SEMsfor all eight layers. The graph shows that all layersmeasured pass the specification of 5 nm with a signifi-cance limit of 8.3 nm. The largest difference between

any pair of SEMs on any layer was less than 7 nm. Theaverage difference was ( 3 nm for all layers individually(Table 1).

Figure 3 shows the results of measurements on a resistcontact layer with nominal features of 330 nm indiameter. With this layer, a distinct difference betweenthe two populations of SEM was identified. Within thesubgroup of the four KLA-Tencor 8100 systems, themaximum delta between any two systems was 3.5 nm.Between the two 8100XP systems, the delta was 1.1nm. The difference between the two subgroups was 8nm. This difference is attributable to the improvedcontact hole imaging of the 8100XP.

To determine if the use of an etched wafer to establishCD SEM matching has an impact on the matching ofresist features, we looked at the correlation between the average pitch value for the dense line structuresmeasured on the two critical layers in this study andthe average feature size for these wafers by tool. Thiswas compared to the correlation between the averagepitch value on a calibration wafer measured on thetools. In both cases, for the etched polysilicon waferand the resist on polysilicon layer, excellent correlation(>90 percent) was found between the pitch value of theproduct wafer and the pitch value measured on the cal-ibration wafer. This is a clear indication that differencesin the wafer means for the two critical layers are notdominated by the choice of the calibration standard.

0 1 2 3 4 5 6 7nm

10

20

30

SEM# 3 6 2 5 4 1

3 0 1.5 1.9 2.8 3.7 3.9

6 0 0.4 1.3 2.2 2.4

2 0 0.9 1.8 2.0

5 0 0.9 1.1

4 0 0.2

1 0

1 2nm

335

340

345

350

355

360

365

370

3 4 5 6

SEM #


Figure 2. Histogram of tool-to-tool wafer mean dif ferences, all layers,

all possible pairs. Dif ferences are in nm. Total number of pairs for all

8 layers = 120. The number of dif ferences for each layer is given by

N(N-1)/2 where N is the number of tools.

Table 1. Pair wise SEM differences (nm) for resist on poly layer.

Figure 3. Average diameter by SEM for resist contact layer. Middle of

diamond indicates wafer mean, points indicate individual measure-

ments. A clear dif ference is evident between SEMs #4 and #5

(8100XP), and SEMs #1, 2, 3 and 6 (8100).


SummaryIt is possible to match multiple SEMs in more thanone manufacturing environment using a straightfor-ward, simple daily qualification procedure and a cali-bration standard based on the pitch of a nested linestructure. Using a simple statistical method to test thematching between all pairs of tools allows matchingcompliance to be established with a minimum amountof time and effort. In addition, a wide variety of pro-duction layers can be measured on CD SEMs withoutthe need to distinguish between the tools on which themeasurements were made.

All of these results demonstrate that it is possible toensure CD SEM system matching within a fab andbetween fabs by employing a simple daily method. Theprocess control gained offers clear benefits to ensure thereliable, repeatable performance of automated CDSEMs in a production environment.

References1. J. Allgair, et. al. “Towards a Unified Advanced CD SEM

Specification for Sub-0.18 um Technology,” in Pro-ceedings SPIE 3332, 1998, pp.138-149.

2. J. Sturtevant, et. al. “Implementation of a closed loop au-tomatic CD and overlay controller for sub 0.25 micronpatterning,” in Proceedings SPIE 3332, 1998.

3. K. Monahan, et. al. “Subnanometer-precision metrologyfor 100-nm gate linewidth control,” in Proceedings SPIE3332, 1998, pp.110-123.

4. J. Allgair, et. al. “SPC Tracking and Run Monitoring of aCD SEM,” in Proceedings SPIE 3332, 1998, pp.243-251.

5. Ibid.6. R.R. Bowley, et. al. “Matching analysis on seven man-

ufacturing CD SEMs,” in Proceedings SPIE 3331,1998, pp.94-99.

7. D. Erickson, et. al. “Statistical verification of multiple CDSEM matching,” in Proc. SPIE 3050, 1998, pp.93-100.

8. J. Allgair, et. al. “Towards a Unified Advanced CD SEMSpecification for Sub-0.18 um Technology,” in Pro-ceedings SPIE 3332, 1998, pp.138-149.

9. Box, Hunter & Hunter, “Statistics for Experimenters”,Wiley, 1978, p111.

10. Ibid., p630.circle RS#009

Mark Your Calendar for. . .

KLA-Tencor’s 7th Annual Data StorageTechnical Information Session and Reception

Wednesday, September 20th, 2000

6:30 p.m. — 10:00 p.m.

San Jose Hilton and Towers

Limited seating available.To reserve your space today,please contact Tavis Szeto [email protected]


Improving Process Control for 0.18 µm Technology and Beyond

by Bryan Choo, Trina Riley, Bernd Schulz, Bhanwar Singh, Advanced Micro Devices

Production fabs typically use critical dimension (CD) measurements as their primary means for process control in printinglines, spaces, and contacts in lithography and etch processes. However, as the industry moves to 0.18 µm manufacturing andbeyond, CD measurements alone are not providing enough information about the printed structures. As the geometry shrinks,slight changes in the shape and profile1,2 can significantly affect the electrical characteristics of the circuit even while main-taining the same CD value. An improved method uses information already collected by a CD SEM to automatically com-pare the stored image and linescan information of a correctly processed structure to that of the structure being measured.

Lithography and etch depend on CD mea-surements to provide feedback on whethercircuit structures have been printed correct-ly. Data collected from critical dimensionscanning electron microscopes (CD SEMs)provide information about the width oflines and spaces and the diameter of contactholes. Besides the sizing of the structures,factors such as the slope of the line and theexistence of notching or footing can signifi-cantly alter the performance of the chip,while remaining relatively undetected in thesimple linewidth measurement.

CD SEM scans contain far more informationthan just the CD value3, and this informa-tion can be used to better characterize thecircuit. A relatively straightforward schemeto utilize all of the data would be to com-pare the entire scan to previously captureddata. This would provide a correlation scorethat shows how the measured structurecompares to one measured previously. Thiscorrelation score can be used to better defineprocess windows and catch process problems.

For instance, by using this data it is possibleto distinguish between different profiles anddetermine if a process shift has occurred,even when the measured CD remains withinspecification. Without this information, the

process used may not be truly optimized, or a shift mayoccur that is not detected in a timely manner, resultingin the loss of yield and revenue.

In the following application, data was collected andimplemented in production on an interconnect lithogra-phy process. Before the correlation information wasavailable, it was very difficult to detect scumming with-in the LI trench, so it was a time consuming and laborintensive procedure to identify problem lots. The corre-lation scores, collected automatically and concurrentlywith the CD measurement, allowed tracking through theSPC chart and automatic flagging of problems while thelot was still in the photolithography module. The resultwas faster feedback control and thus less scrap material.

Setting up the automated methodThe correlation score technique was implemented in thepattern quality confirmation (pQC) software of theKLA-Tencor 8100XP CD SEM. This software allowsthe automated CD metrology program to collect CDmeasurements and correlation values simultaneously.The program uses the pattern recognition template togenerate an image correlation score and the micro-alignment template to generate a linescan correlationscore. An algorithm compares the stored image andlinescan (considered to be the ‘golden’ structure or stan-dard process) to the site being measured. The results arereported on screen and within the standard output file.



The scores show how closely the given site matches thereference. Figure 1 shows linescan comparisons takenfor a set of dense lines and spaces. In Figure 1a, the cir-cuit was printed correctly, resulting in a high correla-tion value of 0.86. The circuit in Figure 1b was mis-processed, leading to deviations from the referencelinescan and a low score of 0.35.

The software allows the user to decouple the referenceimage and linescan from the automation software, thusenabling each to be optimized separately. The pQCsoftware also allows focusing the linescan comparisonon a particular area of interest, such as between denselines for the detection of scumming.

The sample processIn this sample application, a focus-exposure matrix(FEM) was used to characterize a lithography processfor a damascene Metal 1 layer. The stepper focus andexposure were centered to target a CD of 0.375 µm fordense spaces, and for the desired process to hit this target within a range of ±0.025 µm. An automated CDprogram was set up to measure the wafer, providingcritical dimension, linescan correlation, and image correlation data.

The CD measurements indicated that only the extremeprocess parameters at the edges of the wafer were out-side the desired 0.350-0.400 µm window. In contrast,both the linescan (Figure 2) and image correlationscores detect significant changes in the dense trenchstructure being measured, even within the area of thewafer where the CDs are relatively constant. The lines-

can correlation contours are of particular interest. Inthe areas where the CD is obviously out of specification(less than 0.325 µm or larger than 0.425 µm), thelinescan correlation drops precipitously to about 0.4(Figure 4). In the area of the wafer where the CDs arewithin the specified window, the linescans are obviouslyhigher (roughly 0.6-0.8), but also show additionaldetail on which process conditions provide the best‘match’ to the ideal. The linescan contours, therefore,provide a wealth of useful information: they not onlycorrelate well with the CD contours, but also exhibitincreased sensitivity where the CD contours show littleresolution.

0

reference

512 1024 1536 2048

50

60

70

80

90

100

110

120

130

score = 0.86

0

reference

512 1024 1536 2048

50

60

70

80

90

100

110

120

130

score = 0.35

Figure 1a: Example of linescan correlation for a properly processed

circuit.

Figure 2: Plot of linescan correlation contours.


Figure 1b: Example of a linescan correlation for a poorly printed circuit.


for each box. Figure 3 shows an example of the alignedpQC and reference scans. This clarifies the informationon the size and shape of the circuit structure. The CDmeasurement still provides the linewidth or contacthole diameter, while the correlation score is nowfocused only on the shape of the edges.

Finally, for both the image and linescan algorithms,three different types of score parameters can now becalculated. In each particular application of the correla-tion scores, the most sensitive parameter should bedetermined in preliminary tests.

In our sample application, this advanced capabilitysuccessfully detected scumming during the CD mea-surement step, without the need for any additionalmeasurements on other tools or operator assistance. Toconduct the study, the photolithography cells weremonitored with photo track monitor wafers (PTM).Since part of the PTM process flow is a CD measure-ment step, a pQC site was inserted into the CD mea-surement program to collect correlation scores. A FEMwafer was analyzed for best image quality and used tosave the reference scan of the ‘golden’ structure.Knowing that scumming normally starts in densestructures, the left correlation box was placed so that itcaptured only the left edge of a dense trench and theright box was stretched over the trench to include theright edge. When the program was run, the scores forboth boxes (LCorr and RCorr respectively) were calcu-lated without the need for an additional scan.

Figures 4 and 5 show the lot average charts of the cor-relation scores for the left and the right boxes. Bothindicate numerous wafers with scumming problems,

It must be noted that although a linescan score of 0.7was set as the cutoff value for this process, each processlayer should be characterized separately. Once this min-imum correlation is determined, collecting these linescanvalues, in conjunction with the CD measurements,results in a better characterization of the process.

Advanced analysisThe new linescan correlation algorithm in the pQCsoftware allows the placement of two independentboxes (which are also independent in size, similar tothe measurement boxes for a CD site) in the regionwhere the most changes in the signal can be expected.This allows the comparison to focus on a particular areaof interest. Whereas the algorithm in the older softwareversions would be affected by any change in the CD(even if the signals from the line edges were very similar),the new software searches for an edge inside the boxand aligns the pQC scan to the same edge in the storedreference scan before it calculates the correlation score

0

20

30

40

50

60

70

RCorr

80

0

20

30

40

50

60

70

LCorr

80

Figure 3: Scan segments covered by the left and right correlation boxes.


170

75

80

85

90

95

110

4 7 10 13 16 19Wafer

22 25 28 31 34 37 40170

75

80

85

90

95

110

4 7 10 13 16 19Wafer

22 25 28 31 34 37 40

Figure 4. Lot average chart for left box corrlation. Figure 5. Lot chart for right box correction.

correlation values were able to differentiate between structureswith similar CDs and detect resistscumming. In fact, the additionalinformation gained from the corre-lation data provided a better char-acterization of a photolithographyprocess than the CD measurementsalone, resulting in significant sav-ings in time, cost, and materials.

AcknowledgementsThe authors would like to express theirappreciation for helpful discussionsand support from Luis Ortiz and JoergThuemmel of KLA-Tencor. The

authors would also like to thank Stu Brown, Chris Fischerand Renee Walker for their aid in running wafers and ana-lyzing data in Fab 25.

References1. J. M. McIntosh, B. C. Kane, J. B. Bindell, C. B. Vartuli,

“Approach to CD SEM metrology utilizing the full waveformsignal,” Metrology, Inspection, and Process Control for Mi-crolithography XII, Bhanwar Singh, Editor, Proceedings ofSPIE Vol. 3332, pg. 51-60, SPIE, Bellingham, WA,1998.

2. B. Banke, C. Archie, “Characteristics of accuracy forCD metrology,” Metrology, Inspection, and Process Con-trol for Microlithography XIII, Bhanwar Singh, Editor, Pro-ceedings of SPIE Vol. 3677, pg. 291-308, SPIE, Belling-ham, WA, 1999.

3. D. C. Joy, “Ultra-low Energy Imaging for Metrology,”Metrology, Inspection, and Process Control for Microlith-ography XII, Bhanwar Singh, Editor, Proceedings of SPIEVol. 3332, pg. 42-50, SPIE, Bellingham, WA, 1998.

4. D. G. J. Sutherland, A. Veldman, Z. A. Osborne, “Contracthole characterization by SEM waveform analysis,” Metrol-ogy, Inspection, and Process Control for MicrolithographyXIII, Bhanwar Singh, Editor, Proceedings of SPIE Vol.3677, pg. 309-314, SPIE, Bellingham, WA, 1999.

5. E. Solecky, R. Cornell, “CD SEM Edge Width Applicationsand Analysis,” Metrology, Inspection, and Process Controlfor Microlithography XIII, Bhanwar Singh, Editor, Pro-ceedings of SPIE Vol. 3677, pg. 315-323, SPIE, Belling-ham, WA, 1999.

6. D. M. Goodstein, B. Choo, B. Singh, “Correlation Flag-ging of i-Line Lithographic Process Drift,” KLA-Tencor CDSEM Users Group Meeting, Santa Clara, CA, 1999.

which were verified on images automatically capturedduring the measurement (Figures 6 and 7). The chartsalso show the final stabilization of the process after theproblem was fixed.

By using the new pQC feature, it was possible to get asignal for scumming when the problem had just begun.Interestingly, the defect count from the defect inspectiondid not raise a flag for scumming. So, without usingthis technique, the scumming might only have beenfound accidentally during a manual defect review. Thus,the correlation scores enabled the immediate detectionof the scumming problem in the PTM, which mighthave otherwise gone unnoticed until production lots wereaffected. In the sample application, the cause of theproblem was an erroneous PEB plate temperature setting.The resolution of the problem was then confirmed inthe correlation score data (Figures 4 and 5).

Broader applicationsThis technique can be applied to any linear measure-ment feature. For nonlinear features, such as contacts,the image based algorithm can be used. With the newsoftware, the reference image is independent from thepattern recognition template, so optimal magnificationof the region of interest can be obtained without anyimpact on automation robustness.

Correlation scores, which indicate the degree of match-ing between the measured circuit structure and a ‘gold-en’ or reference structure, provide valuable informationabout a process. They can, therefore, be utilized as aneffective process control monitor, without the need foradditional tools or process steps. Even in this sampleapplication, a basic and preliminary embodiment, the


Figure 6. Good sample. Figure 7. Sample with severe scumming.


circle RS#009

Feature dimension is a critical parameterfor lithography and etch processes in semi-conductor manufacturing. CD measure-ments are made for pass/fail purposes toensure that the data for a particular lot arewithin the process tolerances. These toler-ances are usually specified in terms of basicstatistics such as the lot mean and range.The data is also used to identify systematictrends in the process over time. If necessary,the lot CD measurements can be fed backmanually or automatically to adjust theprocess. The measurement samplingrequired to precisely estimate the mean CDof the lot is a function of the baselineprocess variations. For example, in a processthat has minimal wafer-to-wafer variation,the measurement of multiple wafers perproduction lot does not greatly improve theestimate of the lot mean CD.

Determining baseline variations requiresaccurate estimation of different variancecomponents such as lot-to-lot variation,wafer-to-wafer variation within a lot, field-to-field variation within a wafer, and site-to-site variation within a field7. It is com-mon practice to use a nested ANOVAmodel to compute these variations3,6.

Optimizing Yield By Detecting Lithographyand Etch CD Process Excursions

by Richard C. Elliott, Raman K. Nurani, Sung Jin Lee, Luis Ortiz, Moshe Preil, KLA-Tencor Corporation, J. George Shanthikumar, University of California at Berkeley, Trina Riley, Greg Goodwin, Advanced Micro Devices

Effectively detecting lithography and etch critical dimension (CD) process excursions while minimizing added cost can havea significant impact on semiconductor production yield. Finding this balance requires effective application-specific planningin order to identify excursions and find the optimal measurement scheme. There are many different yield-limiting excursionsignatures in photo and etch, and a given excursion signature at photo may turn into a different excursion signature at etchwith a different impact on yield and performance. Many current sampling plans and monitoring schemes miss these excursions.An improved procedure for effective detection of CD process excursions can have a significant impact on yield and revenue.

However, current ANOVA models do not provideaccurate estimates of these variations when systematicvariations are present in the data. A new GeneralizedANOVA model is more effective than the conventionalANOVA model for characterizing the baseline processvariations.

The full distribution of CD measurements can also beused to identify isolated process failures or “excursions.”While process excursions that are isolated to within fieldor within wafer may not greatly affect the mean CD ofan entire production lot, they can have a catastrophicimpact on the performance or yield of the semiconductordevices. Identifying these excursions is critical to ensuretimely correction of yield limiting lithography andetch process issues. This requires a precise estimation of the systematic and random components of the totalvariation (otherwise some of the random excursions canbe masked under the total variation).

The guiding principle to the approach outlined in thisarticle is to determine a sampling plan that effectivelydetects process excursions, while minimizing themetrology resources required to support the collectionof this data. These resources include not only the capitalcost of the CD measurement equipment, but also theengineering resources required to analyze and interpretthe data, and the lost production time which occurswhen metrology data erroneously indicates the occurrence

Lithography





of a CD excursion. The optimal sampling plan providesnot only the quantity of data needed to detect excursions,but also the quality of data needed to detect real excur-sions with a minimum of false alarms. The best samplingplans will also enable the user to effectively diagnosethe types of excursions when they do occur, and tofacilitate the best corrective action so that productioncan be maintained with a minimum of interruptions.

Analyzing the sources of variation and determining theprimary excursion types and frequencies in the processare thus key building blocks of an effective sampleplanning methodology. While statistical analysis andcost modeling are an important part of sample plan-ning, understanding the basic lithographic variationsin the process is equally important in determining theoptimal sampling plan.

There are three basic steps to determining an optimalprocess sampling plan: determining the baseline statis-tics of the CD process; identifying the different excur-sion types, as well as their magnitudes and frequencies;and the evaluation of alternate sampling strategies fordetecting process excursions.

Baseline statisticsTo evaluate the sampling plan, we collected productionCD data for over 600 lots (X wafers per lot, Y fieldsfrom a wafer and 2Z sites from each field) from polygate photolithography and etch steps of a 0.18 µmlogic product. The CD data were collected using theKLA-Tencor 8100 CD SEM measurement tools at theend of poly after-develop and after-etch steps. We ana-lyzed this data to characterize the baseline process andidentify excursions. We also collected wafer level yielddata in order to study if the identified wafer levelexcursions resulted in any yield impact.

Using the data, we computed the baseline distributionsand excursion statistics, separating the systematic andrandom baseline components of variation. Table 1depicts the results of our generalized ANOVA approachand those of the conventional nested ANOVA approach.The nested ANOVA does not separate the systematicand random components of variation, which can cloudresults.

For instance, some of the variance components from theconventional model will be reported as negative numbers.This happens whenever there are systematic variations,which results in the lowest order nested variance com-

ponent being larger than the sum of the lower plus thehigher order components. When this happens, fabstypically set the “negative” variance component equalto zero and make decisions accordingly. In this case, forexample, this could lead to sampling fewer fields on thewafer and eventually missing the field-to-field baselinevariation problems and excursions. In fact, true field-to-field variance obtained from the Generalized ANOVAmodel is indeed the most significant component of thetotal variation. Precise estimation of variation leads tobetter understanding of the process variations, andallows us more reliable capture of random excursions.The conventional model is at risk to underestimate thetotal variance components (Table 1).

Table 1: Baseline variance components (nm2).

The sampling plan for excursion monitoring is primarilydependent on the random variance component. Withoutseparation of the systematic and random components,sampling decisions will be made using the total varia-tion, which can be much higher than the random com-ponent. In the example in Table 1, the total variancefor the site-to-site component has the largest value,which might cause the user to allocate more metrologyresources to measuring multiple sites. In fact, the ran-dom variance components show that field-to-field vari-ation is larger, and thus between field measurementsare more important for excursion monitoring. In thiscase, failure to separate the random and systematiccomponents leads to a sampling plan that is not optimal.

CD excursion typesA lot is considered to have an excursion if its statisticsare significantly different from the baseline with 95percent confidence level. The Generalized ANOVAmodel identifies mean excursions as well as severaltypes of variance excursions, such as site-to-site withinfield variance excursions, field-to-field within wafervariance excursions, and wafer-to-wafer within lot variance excursions.

Generalized ANOVA ConventionalSystemic Random Total ANOVA

Site-to-Site 6.25 2.25 8.50 8.50

Field-to-Field 1.21 5.29 6.50 Neg.Var.

Wafer-to-Wafer 0.08 0.49 0.57 0.42

Lot-to-Lot 1.44 2.25 3.69 3.69


Most of the lot level mean excursions can be detected bymonitoring the lot mean of photo and etch CD processesin an SPC chart. Detection of variance excursionsrequires separation as well as precise estimation of sys-tematic and random variance components. Using ourbaseline analysis and excursion detection algorithms,we identified several types of excursions in the photoand etch CD data. Each excursion signature demon-strated how much the CD deviated from the baseline atsome of the representative fields and sites on a wafer.

After identifying the excursion types, it is necessary todetermine their frequency during photo and etch. Thedifference between photo and etch CD distributions isa function of the different etch biases for different typesof features, as well as the different patterns of spatialvariations in the etcher as opposed to the stepper andtrack processes.

In general, a photo CD variance excursion resulted inan etch CD variance excursion, even if the signature ofthe excursion changed from photo to etch. In fact,about 55 percent of the photo field-to-field varianceexcursions in our study became field-to-field varianceexcursions after etch. This usually occurs when there isno feed forward control from photo to etch. Moreover,after applying regular etch bias to a given excursionwafer, the photo CD excursion signature turns into adifferent CD excursion signature after etch. Theseobservations indicate that it is very important tounderstand different types of excursions at photo aswell as at etch in order to design an optimal feed forward/feedback model for CD control. It is alsoimportant to sample enough fields and sites within a field to detect these excursion signatures and to comprehend the correlation between photo and etchexcursion signatures.

The true purpose of measurement is to identify prob-lems and facilitate their rapid correction. Classifyingexcursions into types can dramatically reduce the engi-neering time and resources required to isolate the rootcause of a problem and initiate appropriate correctiveaction. Understanding the patterns of excursions canalso help drive process improvements and enable set-ting tighter tolerances to improve the performance andvalue of the finished parts.

After correlating the wafer level excursion to yield, weobserved that the field-to-field (or across wafer) varianceexcursions had significant impact on yield. In fact, 70percent of the time, these excursions resulted in low

yield. Figure 1 shows the normalized wafer level yieldof thirteen wafers that were subjected to field-to-fieldvariance excursion at photo and etch. (The correlationof within field excursions to yield requires analysis ofmore detailed die level yield and performance data, andthis study is currently ongoing.)

Sampling plansVarious sampling strategies are available to detectprocess excursions. Finding the optimal plan requiresfinding the best balance between missing excursionsand triggering false alarms; in other words maximizingyield while minimizing cost.

The key question is what is the optimal sampling planfor detecting excursions. This is evaluated based on thetrade-off between “lots exposed to these excursions”(which is proportional to β-risk) and “number of falsealarms” (which is proportional to α-risk).

If the sampling frequency increases, the number of lotsexposed to these excursions is reduced due to earlydetection. The trade-off is that there could be morefalse alarms when there are no excursions. Tighterprocess specs can also minimize β-risk, but again, thisimprovement is obtained at the cost of more falsealarms. The goal is to find a sampling plan with thelowest possible β-risk for a given level of α-risk. Weattempt to find the most effective sampling answer bylooking at what appropriate control charts to use and

Yiel

d Fa

ctor

Wafers with field-to-field variance excursion

Low Yield

Above Average Yield

1 2 3 4 5 6 7 8 9 10 11 12 13

Figure 1. Examples of yield impact of field-to-field variance excur-

sions on wafer yield. The yield factor illustrates whether the yield for

the wafer was above or below average (horizontal black line). There

is no significance to the sequence of the wafers; they were arranged

from lowest to highest yield simply for visualization purposes.



then obtaining the sampling plan. Figure 2 shows thatusing the lot average and lot range control charts is notadequate for quick detection of the CD excursions atphoto and etch. The addition of variance control chartsusing the exact same sampling plan greatly reduces thematerial at risk for a given fraction of false alarms.Simply using a better set of control charts provides afar more favorable control strategy.

Assuming that we use lot average and variance controlcharts, we examine if sampling Y fields per wafer and 2Zsites per field is better than sampling 2Y fields per waferand Z sites per field. The curves in Figure 3 demonstratethat sampling the same number of fields per wafer andtwice as many sites per fields produces better results.

Increasing the number of fields from Y to 2Y results insignificant reduction in material at risk (Figure 4). Infact, at a 3 percent false alarm rate, which is the normaloperating region, the material-at-risk can be cut almostin half. In this case, the number of measurementsrequired increases by a factor of two.

In this example, it is also more beneficial to allocate afixed number of measurements to more fields on fewerwafers than to measure more wafers with a smallernumber of fields. Figure 5 shows that sampling Xwafers per lot, 2Y fields per wafer, and 2Z sites perfield is better than sampling 2X wafers per lot, Y fieldsper wafer, and 2Z sites per field. These results were not

Frac

tion

of

Mat

eria

l-at

-Ris

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Lot Average and Lot Range

Lot Average and Variance Control Charts

Figure 2. Fraction of material at risk (proportional to β-risk) vs. fraction

of false alarms (proportional to α -risk) for the same sampling plan but

with dif ferent SPC control charting strategies.

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X Wafers, 2Y Fields, Z Sites

X Wafers, Y Fields, 2Z Sites

Figure 3. Fraction of material at risk vs. fraction of false alarms for

two dif ferent sampling plans with the same total number of measure-

ments but a dif ferent allocation of measurements between fields per

wafer and sites per field.

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X Wafers, 2Y Fields, 2Z Sites

X Wafers, Y Fields, 2Z Sites

Figure 4: Fraction of material at risk vs. fraction of false alarms for

two sample plans with a dif ferent total number of measurements.

Doubling the number of fields per wafer reduces the amount of material

at risk for any given fraction of false alarms.

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X Wafers, 2Y Fields, 2Z Sites

Figure 5. Fraction of material at risk vs. fraction of false alarms for two

different sampling plans with the same total number of measurements

but a dif ferent allocation of measurements between wafers per lot and

fields per wafer.



surprising given that Table 1 showed the field-to-fieldvariance, when properly computed, is larger than thewafer-to-wafer variance. (This improvement would notbe obvious using a conventional nested ANOVAmodel.)

After applying the learnings from these samplingstrategies to the 0.18 µm logic fab, the material at risk was reduced by roughly 28 percent at a constant 3 percent false alarm rate.

A mere 1 percent saving in material at risk can resultin significant financial returns. For example, if a fab has5000 wafer starts per week, 200 die per wafer, and a$100 selling price per die, then 1 percent material atrisk has a revenue potential of $1 million a week,which translates into $52 million a year. With a veryconservative yield benefit estimate of 10 percent, whichis the difference between the baseline and excursionyield, and a baseline yield of 50 percent, the net benefitfrom saving 1 percent material-at-risk could be $2.6million a year. In each case, the additional cost savingsneed to be weighed against the cost of any increase inmeasurements. In this case, the additional measure-ments required did not significantly increase the cost ofmetrology for the fab, so the change in sampling planswas clearly beneficial.

SummaryProperly characterizing baseline excursions and applyingoptimal sampling techniques allowed a notable increasein yield without a significant increase in cost. For thisparticular fab, the best answer was to double the numberof fields per wafer sampled, thereby realizing a signifi-cant reduction in material-at-risk.

In order to maximize yield and minimize false alarms,each fab needs to precisely estimate the baseline statis-tics, understand the different types of excursions, theirfrequency, their yield impact, and how they carry overfrom photo to etch. Moreover, a stochastic model thatcaptures all these dynamics and evaluates the risks/costsof different sampling strategies is needed to determinethe best-customized CD sampling plan-and realize sig-nificant financial gains.

AcknowledgementsThe authors would like to thank Steve Reeves, Paul Ackmann,Renee Walker of AMD, Gus Pinto, Gil Griffin, UmarWhitney, Pat Lord, Harikrishnan Rajagopal, DadiGudmundsson, Richard Quattrini of KLA-TencorCorporation, and Chayakrit Charoensiriwath of UC Berkeleyfor their support and assistance in executing this joint project.

References1. R. Carnes and M. Su, “Long term cost of ownership: Be-

yond purchase price,” in the proceedings of IEEE/SEMI In-ternational Semiconductor Manufacturing Science Sym-posium, pp. 39-43, 1991.

2. C. Derman and S. M. Ross, “Statistical Aspects of Qual-ity Control,” Academic Press, 1997.

3. S. A. Eastman, “Evaluating Automated Wafer MeasurementInstruments,” SEMATECH Technology Transfer report94112638A-XFR, 1995.

4. R. Elliott, R. K. Nurani, D. Gudmundsson, M. Preil, R. Na-songkhla, and J. G. Shanthikumar, “Critical dimensionsample planning for sub-0.25 micron processes,” in theproceedings of Advanced Semiconductor ManufacturingConference and Workshop, pp. 139-142, September1999.

5. S. Kudva, and R. Potter, “Cost analysis and risk assessmentfor metrology application,” in the proceedings of SPIE, vol.1673, pp. 2-13, 1992.

6. K. Monahan, R. Forcier, W. Ng, S. Kudallur, H. Sewell,H. Marchman and J. Schlesinger, “Application of statisti-cal metrology to reduce total uncertainty in the CD-mea-surement of across-chip linewidth variation,” in the pro-ceedings of SPIE, vol. 3050, pp. 1-14, 1997.

7. B. E. Stine, D. S. Boning and J. Chung, “Analysis and de-composition of spatial variation in integrated circuitprocesses and devices,” IEEE Transactions on Semicon-ductor Manufacturing, vol. 10, no. 1, February 1997.



circle RS#009


Traditionally there have been two distinctapproaches to process control. Statisticalprocess control (SPC) is a technique in whichthe process output is monitored, usually exsitu, in order to detect an out of controlprocess. SPC attempts to assign a causalityrelationship to an external disturbance. Aprocess is considered out of control if outputvariance can be attributed to an assignablecause1. However, many times the machinehas not reached an inoperable state. Theoperator simply compensates for the errorby manipulation of a process input variable.SPC does not define the control action nec-essary to return a process to an in controlstate. This decision is left to the operator orcontrol engineer. SPC has seen widespreadacceptance in discrete parts manufacturingwhere processes generally have highrepeatability and natural variability.

The other approach to process control isAPC. Sometimes referred to as engineeringprocess control (EPC), APC uses measure-ments of important process variables toincorporate a feedback loop into the controlstrategy. The feedback loop uses a mathe-matical relationship to adjust process inputsbased on the measure-ments in order to keepthe product on target. APC accomplishesthis by transferring variability in the outputvariable to an input control variable2.


Run-to-Run Control of Photolithography Processes

by W. Jarrett Campbell, Ph.D., KLA-Tencor Corporation

Run-to-run (R2R) control is rapidly becoming a key process control tool in the semiconductor industry. Due to the complexity and importance of the photolithography process, overlay and critical dimension are two common process parametersthat are controlled via advanced process control. As the device fabrication process is extremely sensitive to key photolithographyparameters, the benefits resulting from superior process control are significant.

Recently, a combination of SPC and APC has emergedto address processing issues in the semiconductor man-ufacturing industry. Known as run-to-run (R2R) con-trol, this approach combines techniques from both SPCand APC in an attempt to reduce output variability.From an SPC standpoint, R2R control extends tradi-tional process monitoring by monitoring controlactions for abnormality. APC practitioners can viewR2R control as a supervisory controller that manipu-lates the setpoints of underlying tool controllers. Theultimate goal of R2R control is that of batch controlfor a lot of wafers. By analyzing the results of previousbatches, the R2R controller should be able manipulatethe batch recipe in order to reduce output variability.

The motivation for R2R control is a lack of in situmeasurements of the product quality. Typically, insemiconductor manufacturing, the goal is to controlqualities such as film thickness or electrical propertiesthat are difficult, if not impossible to measure in real-time in the process environment. Most semiconductorproducts must be moved from the processing chamberto a metrology tool before an accurate measurement ofthe control variable value can be taken. Semiconductorprocessing tools generally have real-time controllers,typically PID loops, for controlled variables that can bemeasured in real-time. The variables are typicallyprocess inputs, such as chemical flow rates, or reactorstates like temperature or pressure. The manufacturingengineer must specify a recipe that contains the set-points of these inputs and states that will produce theproper output product. The job of the supervisory,


R2R controller is to adjust these recipes to reduce vari-ability in the output product.

R2R control is further necessitated by the non-station-ary nature of most semiconductor processes. While SPCis designed for stationary processes where output varia-tions are independent, R2R control is able to compen-sate for drifting processes where output variations arecorrelated. The variation correlation is typically causedby changes in the processing environment. For example,in a deposition process, the reactor walls may becomefouled by deposition as many products are processed.This slow drift in the reactor chamber state requiressmall changes to the batch recipe in order to ensure thatthe product outputs remain on target. Eventually, thereactor chamber will be cleaned to remove the walldeposition, causing a step disturbance in the process.Just as the R2R controller compensates for the driftingprocess, it will also compensate for the step disturbance toreturn the process to target after an environment change.

Many manufacturers have concentrated their efforts inR2R control on the photolithography process. Becauselithographic processes are perhaps the most criticaldevice fabrication steps, R2R control has the potentialto significantly impact the quality and maufacturabili-ty of semiconductor devices. Using advanced APC soft-ware such as KLA-Tencor’s Catalyst, several large semi-conductor manufacturers have applied R2R control totheir manufacturing processes in order to minimizevariations in both critical dimension (CD) and overlayregistration.

Overlay controlOne type of R2R control often employed in device fab-rication is overlay control. The purpose of overlay R2Rcontrol is to minimize the errors in registrationbetween subsequent masking layers. There are manytypes of overlay errors that may occur during manufac-turing. Some of these errors include translation, rota-tion, magnification, and shear. Examples of these over-lay errors on a wafer-scale are shown in Figure 1.

A typical means of controlling overlay errors is to setupa feedback loop between the overlay metrology tooland the masking tool via an APC software system. TheAPC system continually monitors overlay errors at eachmasking operation to detect slow drifts or suddenshifts. When a disturbance in overlay is detected by theAPC system, the software automatically updates thestage and reticle offset parameters on the masking tool

in order to eliminate the overlay errors. Figure 2 illus-trates a typical feedback system for overlay control.

When overlay R2R control is implemented, manymanufacturing benefits result. Semiconductor manu-acturers have reported increased Cpk, reduced rework,reduced send-ahead wafers, and decreased engineeringtime devoted to stepper matching. Advanced MicroDevices’ Fab 25 has reported that their implementationof overlay R2R control has decreased overlay-specificphotolithography rework by over 50 percent and threesigma translation errors were reduced by greater than20 percent. In addition, AMD has been able to elimi-nate test-wafer and send-ahead qual procedures foroverlay calibration because these procedures are nowhandled exclusively by the APC software.3

Grid Translation Grid Magnification

Grid Rotation Grid Shear/Orthogonally

Figure 1. Examples of overlay errors.

Figure 2. Overlay feedback system.



CD controlAnother key process parameter in photolithography isCD. Just as overlay can be controlled using a feedbacksystem, CD variations can be minimized using R2Rcontrol. However, CD control is not as easy as using afeedback system between the stepper and the CDmetrology tool. This is because there is an etch bias,shown in Figure 3, that results during the post-pho-tolithography etching process.

Instead, a combined feedforward-feedback control sys-tem must be built around the etch process to ensurethat the final inspection (FI) CD is at the appropriateprocess target.

First, the CD is measured after the developmentinspection (DI). This value is used in a feedforwardmanner to allow customization of the etch processrecipe on a lot-by-lot basis. In other words if variabilityin the DICD value for a lot is measured, it can bedirectly compensated for by manipulation of that lot’setch recipe.

In addition to feedforward control, feedback control isperformed by monitoring the FICD resulting from theetch process. The APC system can detect drifts or shiftsin etch bias caused by disturbances to the etch chamber.The feedback system can then change the etch recipeappropriately to eliminate any systematic disturbancesin the etch bias. Typically, the feedforward and feedbackinformation is combined using a mathematical modelof the etch process to determine an appropriate etchtime for each lot.

One difficulty of this CD control approach is thatdrifts in the upstream photolithography process can becompensated for after the fact, but cannot be correcteddirectly at their source. Imagine a scenario where stepperdrift has caused the DICD values after photolithographyto drift so far that even the feedforward control systemcannot properly compensate for incoming DICD varia-tion. An example would be a case where the etch timerequired is outside the allowed process window. Inorder to prevent such difficulties, a second feedbackloop, often called a cascade loop, can be implementedbetween the etcher and photolithography tools.

The purpose of the cascade loop is to ensure that etchtimes remain centered in the allowable process window.This is done by manipulating the DICD target of thephotolithography process. For example, if the etch toolshave drifted such that long etch times are required toachieve the desired FICD target, the photolithographyrecipe can be adjusted in order to target a new DICDvalue that will not require as much etch to achieve thesame DICD target. This feedback system is uniquefrom those previously discussed because the monitoredoutput of the control loop is actually the recipe settingsused in the etch process. The manipulated variable inthis control loop is the process target in the photolitho-graphy process.

Once a cascade loop is in place to set the DICD targets,it may also be desirable to add a third feedback controlloop around the photolithography process to ensurevariations in DICD are minimized. This third controlloop is a simple feedback loop between the CD metrol-ogy tool and the stepper. Although the feedforwardcontroller at the etch process can compensate for varia-tions in DICD, the etch controller will perform betterif the variations in incoming DICD are localized to asmall operating region. This allows more precise mod-eling of the etch process and results in better control ofFICD. Although it has been shown that several recipesettings including post-exposure bake time and devel-op time can affect changes in CD4, the most popularrecipe setting used to control DICD is the exposuredose. Dose is often chosen because the photolithogra-phy process tends to have a strong, linear relationshipbetween changes in exposure dose and changes inDICD.

Once these three control loops are put into place, acomprehensive control system is now available to mini-mize variations in CD across the patterning process.Figure 4 represents a schematic of such a control system.

Previous Layers

DI CD

FI CD

Etch Bias


Figure 3. CD bias induced by etch process.

SummaryR2R control is rapidly becoming a key process controltool in the semiconductor industry. Because of thecomplexity and importance of the photolithographyprocess, overlay and CD are two common process para-meters that are controlled via R2R control. AdvancedProcess Control (APC) software, such as KLA-Tencor’sCatalyst, provides a means of integrating R2R controlsolutions into today’s device fabrication facilities. Byusing such software, many of the top semiconductormanufacturers have been able to reduce the effort, cost,and time required in deploying APC in their produc-tion environments.

References1. Douglas C. Montgomery. Introduction to Statistical Qual-

ity Control. John Wiley & Sons, 2nd edition, 1991.2. Douglas C. Montgomery, J. Bert Keats, George C. Runger,

and William S. Messina. Integrating Statistical PprocessControl and Engineering Process Control. Journal of Qual-ity Technology, 26(2), April 1994.

3. Christopher A. Bode. Run-to-Run Control of PhotolithographyOverlay. Proceedings of SEMATECH AEC/APC Sympo-sium XI. October 1999.

4. Thomas F. Edgar, Stephanie W. Butler, W. Jarrett Camp-bell, Carlos Pfeiffer, Chris Bode, Sung Bo Hwang, andK.S. Balakrishnan. Automatic Control in Microelectron-ics Manufacturing: Practices, Challenges, and Possibilities.Automatica. Accepted for Publication.

5. Anthony J. Toprac and W. Jarrett Campbell. Run-to-Run Con-trol Using the APC Framework. Proceedings of SEMATECHAEC/APC Symposium X, October 1998.

6. Terry Caudell. APC: An Enabling Technology in the Sub-quarter Micron Era. Proceedings of AEC/APC WorkshopEurope. March 2000.


Because CDs are very closely tied to semiconductordevice performance, it is easy to imagine that the supe-rior process control achieved through implementationof R2R control can have significant impact on themanufacturing process. IC manufacturers have validatedthat implementation of R2R control of CD can resultin tremendous financial and manufacturing benefits. Inparticular, Advanced Micro Devices has reported thatR2R control of CD has lead to a greater than 8 percentincrease in overall device speed. This boost in perfor-mance allowed AMD to realize approximately $40 millionin increased revenue per year. On the manufacturing side,AMD also reported that photolithography rework forCD variation was reduced by over 90 percent and thatone sigma variation in FICD was reduced by 45 percent5.

Integrating APC into the fabOnce the R2R control systems are developed, theymust be implemented in software and integrated intothe manufacturing facilities. This integration effort isthe single largest roadblock preventing rapid deploy-ment of R2R control solutions throughout the semi-conductor industry. Advanced APC software, likeKLA-Tencor’s Catalyst*, eases the integration effort byproviding a software framework in which APC applica-tions can be developed and implemented into semicon-ductor manufacturing systems.

The benefits of applying R2R control are significant.One semiconductor manufacturer’s experience withR2R control is summarized in Table 1.


Table 1: Results from R2R Control Production Implementations6.

CD Overlay

Rework reduced 90% Rework reduced 50%

Std. dev. reduced 45% Std. dev. reduced 20%

Speed increased 8% Eliminated test quals

Revenue increased Eliminated need for$40 million per year manual tool matching

Figure 4: Comprehensive CD Control Strategy

* Note: Catalyst is the result of a three year, ten milliondollar NIST-sponsored joint research project betweenKLA-Tencor’s Control Solutions division, AdvancedMicro Devices, and Honeywell. The research projectestablished SEMATECH and SEMI standards for APCsoftware. Catalyst is the first commercial APC softwareto be based on these standards and it is SEMATECHCIM Framework compliant.



From December 1999 to March 2000,TSMC’s Fab 3 facility evaluated a 2139 betasystem versus the baseline 2138 system forthroughput and sensitivity. All layers were0.18 µm to 0.22 µm design rule logicdevices. A 2138 system already installed inthe fab was upgraded to a 2139 system.Negligible baseline shift between the toolsusing the same inspection recipe and waferwas observed. Data were collected to showthe robustness of job queuing, the sensitivityof the 0.16 µm pixel, the throughput usingthe new version 5.2 software, and therobustness of SAT recipes for production.Additionally, the sensitivity improvementobtained by optimized SAT recipes (usingAutoSAT software) relative to the baselinemean-range image processing method wasevaluated.

Throughput resultsAfter verifying that there was no baselineshift on Metal 4, Spacer, and Polysilicon 1etch levels, inspection equipment through-put and productivity was tested. Inspection

Enhancing Sensitivity and Throughputin Brightfield Inspection

by P.H. Wu, J.P. Wu,TSMC Fab 3; J. Liao, C. Chuang, K. Nafisi, M. Dishner, KLA-Tencor Corporation

This paper was presented at KLA-Tencor’s Yield Management Solutions Seminar during SEMICON/Europa in April 2000. It was edited for this publication by Mark Keefer, KLA-Tencor Corporation.

As integrated circuit feature sizes continue to shrink, and device cycle times are reduced, defect inspection technology mustcontinue to improve for device manufacturers to manage their yield. The introduction of the KLA-Tencor 2139 increasedsensitivity, defect capture and throughput on its 2100-series brightfield optical imaging inspector product line. Primarysensitivity improvements are achieved by decreasing the pixel size and by automating the recipe development of segmentedthresholding routines (AutoSAT). Productivity is enhanced by job queuing and faster edge die inspection (double detectionof edge die defects without re-swathing).

equipment productivity was increased in two ways.First, the multi-tasking feature of Windows NT soft-ware (KLA-Tencor 213x version 5.2) allows job queu-ing. While an inspection is in progress, the nextinspection lot and recipe can be prepared, reducing idletime on the inspector. The time savings can be quitesignificant, especially in a SMIF fab with pod load andunload times. Figure 1 shows the time savings achievedusing the job queuing feature for inspection of two lots(in the left and right cassettes), two wafers per lot.

Another throughput improvement in the 2139 is fastedge die inspection, referred to as the Mass MemoryEdge Die (MMED) feature. Prior to MMED, doubledetection of edge die defects required that the edge diebe re-swathed, which adds considerable time to theinspection (referred to as the TEO method, meaning“triple edge only”. First the wafer center is scanned, thenthe left side, then the right side). The MMED upgradeallows sufficient inspection data to be stored in thememory buffers so that the edge die do not require re-swathing. Figure 2 compares inspection time on 0.22 µmMetal 3 etch wafers from five different lots (using 0.39 µm pixel). The average inspection time using TEO is14 minutes 47 seconds; the average time using MMEDis 12 minutes 18 seconds, a 17 percent improvement.


review, making verification of real and false or nuisancedefects during inspection recipe development easier.

Inspection sensitivity is determined by resolution(small pixel size) as well as suppression of pattern andprocess variation noise. Segmented Auto Thresholding(SAT) is an image processing technology used to sup-press pattern and process noise. SAT segments thewafer image based on the gray level signature of thepattern and dynamically sets separate thresholds foreach segment, resulting in higher sensitivity than themean-range image processing method. An AutoSATroutine has been developed to simplify SAT recipe

Particle(open)

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Sensitivity resultsSmaller pixel sizes can increase defect detection sensi-tivity for process levels that are limited by inspectionresolution. The 2139 0.16 µm pixel was compared tothe 2138 0.25 µm pixel. The increased capture of the0.16 µm pixel on a 0.18 µm Polysilicon 1 etch level isshown in Figure 3. The defect counts are cumulativetotals of five wafers from five different lots.

Figure 4 shows SEM images of some of the defect typesdetected using the 0.16 µm pixel in die-to-die (random)mode on the 0.18 µm design rule Polysilicon 1 etchlevel. These defects were not caught using the 0.25 µmpixel. In conjunction with the smaller pixel, a higher-resolution camera provides sharper images for defect

F E A T U R E S

Figure 1. Breakdown of time savings achieved using the job queuing feature.

Load L.SMIF

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Figure 2. Comparison of inspection times for Metal 3 etch level.

Test 1 Test 3Test 2 Test 4 Test 5

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utes

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Figure 3. Poly etch defect capture comparison (0.16 µm and 0.25 µm

pixels).


Using AutoSAT, the 2139 also uniquely detected sev-eral defect types not detected by mean-range imageprocessing on this Metal 3 etch level.

SummaryThe productivity and sensitivity improvements of the2139 defect inspection system were evaluated. The job queuing feature improved tool utilization by over20 percent. Inspection time per wafer using the 0.39 µmpixel was reduced by about 17 percent using the fastedge die mode. The smaller 0.16 µm pixel sizeincreased defect capture relative to the 0.25 µm pixel,and additional sensitivity was achieved using theAutoSAT image processing algorithms. Additional data also showed that SAT reduced the level of nuisancedefects such as blister defects on Metal 3 and 4 etchlevels.

setup. AutoSAT recommends optimal segmentationschemes from a pre-defined selection of templates, thenautomatically optimizes the threshold for each scheme.The automation reduces recipe development time, andresults in more consistent recipes. Figure 5 comparesdefect detection sensitivity of AutoSAT and mean-rangeimage processing on a 0.22 µm logic device Metal 3etch level. The defect counts are cumulative totals ofnine wafers from nine different lots. Defect capture ofparticles in dense arrays and defocus defects in particu-lar were improved.

F E A T U R E S

Brig

htM

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alRe

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r

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e

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ct C

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453289

AutoSAT

Figure 5. Comparison of AutoSAT and mean-range image processing

methods on metal etch.

Figure 6. SEM images of 0.22 µm design rule Metal 3 etch defect

types uniquely caught by the AutoSAT recipeFigure 4. SEM images of 0.18 µm design rule Polysilicon 1 etch

defects detected using 0.16 µm pixel.

Oxide Hole Particle

Pattern W-Puddle

circle RS#047


cleaned and scanned on the Surfscan SP1TBI. The waferscans for each channel are shown in Figure 2. Using anoblique incident “C” polarized beam, the wide channelexhibited a much higher LPD count than the narrowchannel. Under review using a CRS confocal laserreview microscope, we confirmed that the higher counts


CMP Defect Detection and ProcessControl using the Surfscan SP1TBI

By Katia Devriendt, Paul Mertens, Wim Fyen, Karine Kenis, Marc Schaekers, IMEC, Dale Guidoux, Grant Sergeant, Stephane Robic, Rene Moirin, KLA-Tencor Corporation

The Chemical Mechanical Planarization (CMP) process is now widely used to provide global planarity of layers duringthe fabrication of integrated circuits. Successful yield management of CMP requires detection of all critical defects in thepresence of noise sources such as film thickness non-uniformity within a wafer or process variation within a lot. CMP defectscan be separated into two categories; residual slurry particles or other foreign material on the surface, and microscratches orpits in the surface. Both defect types are known to have a negative impact on device yield. In a joint study between IMECand KLA-Tencor, an experiment was performed to show how the Surfscan SP1TBI unpatterned wafer inspection system canbe used to monitor both types of critical defects. Electrical test patterns were generated on CMP wafers to study the correla-tion of device yield to defect types.

In our experiments, High Density Plasma(HDP) oxide layers were polished usingIMEC’s standard oxide CMP process. Aftercleaning on a scrubber using ammonia onthe brushes, the polished wafers wereinspected on a Surfscan SP1TBI. As seen inthe Surfscan SP1TBI optics layout (Figure 1),the tool has both a normal and obliqueincident beam and two collection channels,wide and narrow. The wide and narrowchannels were both calibrated to give simi-lar defect counts using Polystyrene Latex(PSL) spheres. On a standard CMP polishand clean, the wafers also exhibited similarLight Point Defect (LPD) counts in boththe wide and narrow collection channels.We suspect that the LPDs detected in bothchannels are primarily surface particles, aswe would expect particles to scatter intoboth collection channels, whereas micro-scratches or surface void defects shouldscatter preferentially into only one of thedetectors. To confirm this hypothesis, weadded or “spiked” the standard CMP slurrywith 1.5 µm diameter alumina particles.Another set of HDP oxide wafers were thenpolished with the contaminated slurry,

NormalIncidence

Beam

DarkFieldWidePMT

Dark FieldNarrow PMT

Wafer

ObliqueIncidence

Beam

SNT RadialDeflection

SNT TangentialNomaski DIC

LensCollector

EllipsoidalCollector

BrightfieldChannels

Figure 1. SP1TBI optics layout.


detected only in the wide channel were primarily micro-scratches (Figure 3). To further verify our hypothesis, wedeposited approximately 5000 PSL spheres to the wafercontaining microscratches. The LPD count increasedabout 5000 counts in both channels. To be sure thatthe effect witnessed is not just limited to the propertiesof PSL spheres, we also measured standard CMP pol-ished wafers that were dipped into a solution of slurryto add typical residual slurry particles. Similar amountsof LPDs were counted in both channels in this case aswell. In summary, the microscratch counts were detect-ed predominately in the wide collection channel,whereas surface particles were counted in both the widecollection channel and the narrow collection channel.

In the next phase of the experiment, “snake” and “fork”patterns were deposited on a polished oxide surface totest for intra-level defects represented by (a) shortsbetween the snake and fork lines and (b) discontinuityof the snake lines (Figures 4 and 5). Inter-level defectscharacterized as electrical breakdown of the polished

oxide between metal capacitor plates werealso tested. Two sets of wafers were polishedusing a standard slurry and two sets werepolished using a slurry contaminated or“spiked” with large silica particles greaterthan 1 µm to induce a larger percentage ofmicroscratches. One set of the standard slur-ry polished wafers received a scrubber cleanwith dilute ammonia and one set wascleaned with ammonia plus an HF wet etch.No significant difference in the density ofintra-level electrical shorts or discontinuitiesin the standard slurry was detected as com-pared to the density of defects in the conta-minated slurry for either cleaning condition.

The effect of cleaning chemistry on inter-level defects was more significant. For thestandard slurry polish and the contami-nated slurry polish with just a diluteammonia scrub, the results are acceptable.But, when applying an HF wet etch to acontaminated slurry polish (more scratchespresent), the results are catastrophic. TheHF etches the oxide surface scratch defectsand causes early electrical breakdownbetween the capacitor plates.

The study has shown that the SurfscanSP1TBI is an effective tool for monitoringCMP slurry residue and microscratchdefects that can lead to device yield problems.

Figure 2. Using an oblique incident beam and “C” polarization, the wide-channel

exhibited a much higher LPD count than the narrow channel.

Figure 3. Microscope review confirms the spiked slurry (right) exhibits a higher number

of microscratches.

microscratchparticle

Al

Al Al

Si

oxide

particle

microscratch

a

b

Figure 5. Electrical breakdown

characteristics of polished oxide

(inter-level defects between metal

capacitor plates).

F E A T U R E S

CMP condition:- HDP oxide- slurry:

fumed SiO2 (ILD-1300)with 1.5 µm aluminaparticles

- cleaning: scrubber only

SP1TBI recipe:- Oblique C-UU Full- LSE-diam:

min 0.15 µmmax 1.0 µm

Figure 4. Inter-metal defects on

metal meander-fork structures

deposited on a polished oxide

surface (0.4 µm line/0.4 µm

spacing). (a) shorts between

meander-forks (b) discontinuity

of meander lines.

Wide-channel

circle RS#013

Narrow-channel


Process ParametricsF E A T U R E S

Analysis of Phosphorous Auto-dopingin P-Type Silicon using Corona OxideSilicon Techniques

By Brian Letherer and Greg Horner, KLA-Tencor Corporation

Semiconductor fabrication facilities rely on the integrity of the silicon to manufacture submicron devices. Cross contaminationof P-type silicon to N-type carriers or vice versa in the near surface region of the silicon can be detrimental to device performance. Semiconductor processing typically includes numerous diffusion and pre-clean steps, any one of which mightauto-dope a P-type silicon substrate with phosphorous. In-line monitoring of these near-surface doping effects enhances the ability to diagnose auto-doping problems.

A non-contact Corona Oxide Silicon (COS)measurement technique has the ability todetect cross-contaminated P-type siliconwith phosphorous from wet clean benchesand diffusion furnaces. Results show COSflatband (Vfb) and oxide total charge (Qtot)measurements are sensitive to various levelsof intentional phosphorous contaminationimplanted into the silicon at pre-oxidation.Phosphorous at the silicon/oxide interfacecan pile up and create an electrically activethin “N” skin. Phosphorous from this thin“N” skin is shown to change the electricalcharacteristics of near surface region of thesilicon. The detection of unwanted phospho-rus with the use of COS in-line monitoringcan greatly reduce the response time whenauto-doping problems occur.

Contamination control has long been anintegral part of semiconductor manufacturing.Yield loss due to small amounts of contami-nation in silicon can cause catastrophic lossof product due to slight changes in electricalbehavior of silicon based devices. The sourceof contamination can be widespread, as well;there are a variety of potential sources in asilicon manufacturing facility. Isolating andeliminating these sources of contamination

can also be difficult and tedious. Phosphorous, in par-ticular, is used in many areas in a fab as a dopant andcan cause significant problems to the near-surface sili-con region, the primary region where a device operates.

Detection of contamination problems can be time con-suming and timely feedback of detection is also desiredto reduce the amount of product at risk. An in-linemetrology tool to monitor contamination is essential ina manufacturing environment. The COS, which iscommercially available, has the ability to monitor contamination and give timely feedback to ensure therisk of contamination is minimal.

The primary sources of phosphorous are generallyPOCL3 doping of polysilicon and phosphorousimplant. Bare silicon wafers, with high phosphorouscontent, (test or monitor) processed in wet sinks orhigh temperature diffusion can readily out-diffuse andwill auto-dope wafers with P-type silicon in the sameprocess step or in subsequent process steps. The sourceof the phosphorous contamination tends to be verylocalized, as only certain sections of a diffusion furnaceor wet-cleaning processes will be contaminated.Quartzware in diffusion furnaces and wafers that arerun continually in the diffusion furnace for thermalmass may retain phosphorous. On subsequent runsphosphorous will out-diffuse at temperatures above850°C and diffuse into exposed silicon substrates of


lesser doping concentration1. Wet cleaning processescan also accumulate impurities, such as phosphorous,from wafers that came from a heavily doped high tem-perature process, like diffusion POCl3 step. Phosphorousfrom the contaminated clean step will deposit on thesurface of the silicon and create an N-skin2. The phos-phorous is then activated in the near surface region ofthe silicon during successive high temperature processsteps.

Once phosphorous has entered the silicon it will accu-mulate at the near-surface region of the silicon duringsubsequent oxidation processes3. It has been shown thatphosphorous will induce a positive oxide charge innative oxide, prior to an oxidation. In this mechanismP5+ replaces Si4+ in the oxide4. The data obtained inthis study supports the hypothesis that very little phos-phorous is incorporated in the oxide during a conven-tional thermal oxidation.

Due to the nature of the low level of doping in thenear-surface region after oxidation, there are very fewcurrent methods available that can detect unwantedphosphorous in the near-surface region of the silicon.Many of the technologies employed require that a pat-terned device must be generated to electrically test foranomalies, such as CV. This requires extra processingand will not allow for timely feedback. COS technologyis an inline, non-contact monitoring tool that will provides timely feedback.

COS measurement techniqueA KLA-Tencor Quantox COS (Corona OxideSemiconductor) system was used for all of the electricalcharacterization work presented here. As in the CVtechnology, COS analysis requires that an electrical biasbe applied to the sample to measure the electricalproperties of the near surface silicon and oxide layer. Asmall amount of charge is precisely deposited on theoxide surface by ionizing moisture and CO2 above thewafer surface5. A sweep is produced in a step-wise fash-ion by depositing increments of surface charge to biasthe underlying silicon from inversion to accumulation.A vibrating Kelvin probe is then used to measure thesurface voltage (Vs) response of the deposited surfacecharge at each step of the sweep. A high-speed lightsource photogenerates carriers in the near surfaceregion and the resultant flood of carriers flattens theband bending in the silicon. The resultant surfacephoto voltage (SPV) is similarly measured during eachstep of the surface charge sweep and provides a mea-

surement of the silicon band-bending. From these twomethods (Vs and SPV), charge versus surface voltage(QV) and charge versus SPV curves can be generated asdisplayed in Figure 1. From these curves measurementssuch as flatband voltage (Vfb), total charge in the oxide(Qtot) and density of interface traps (Dit) can be extracted.Vfb is calculated when the SPV is 0 on the SPV versessurface voltage curve. Qtot is the amount of charge inthe oxide at flatband. Dit is derived from the QV curveusing the Burglund method.

COS also has the ability to measure near surface dopingin the silicon. This is accomplished by biasing the siliconinto strong inversion using onto a site. A guard ring isthen placed around the site with opposite signed chargeto place the silicon into accumulation. A known chargepulse is then applied to the central region into deepdepletion. The deep depletion transient response isanalyzed to extract both the doping level and the generation lifetime of the near-surface silicon.

ExperimentalIn this study, phosphorous was intentionally introducedinto the silicon to mimic a contamination problem.Bare P-type silicon eight inch wafers were used with a doping level of 1.5E15 #/cm3. The samples wereimplanted with various amounts of phosphorous rang-ing from a control wafer of no implant, to a wafer thatreceived 3E12 #/cm2 dose of phosphorous implantation.Oxidation was then done in a vertical furnace utilizinga standard CV oxidation process at 900°C, which didnot include the use of chlorine, to produce 950 Å of

Dit:from slope

Vfb:SPV=O

Tox:dQ/dVs

Vs (

Volt

s)

SPV

(Vol

ts)

Deposited Charge x1E-8 (C/cm2)

-0.6-10.0 -5.0 0 5.0 10.0

-0.4

-0.2

0

0.2

-4

-2

0

2

4

Figure 1. A diagram of a surface voltage vs. deposited charge curve

and a surface photo voltage vs. deposited charge curve as measured

by COS.

F E A T U R E S


oxide. Wafers were then etched back to varying oxidethicknesses, using an HF wet stripping process. Eachwafer was stripped back three separate times to obtainoxide thickness levels of 850, 750 and 300 Å. COSmeasurements were performed after the etch step, ateach thickness level.

The wafers were stripped back to determine the sensi-tivity levels of measurements to detect phosphorous onthin oxides. In general, higher measurement precisionis required to monitor thin oxide layers for potentialcontamination in the near-surface substrate. We showhere that the COS measurements retained excellentsensitivity as the oxide thickness decreased.

ResultsCV versus COS measurements have been well-docu-mented (5). Changes in flatband due to changes in thecharge in the oxide and underlying substrate show bet-ter correlation with COS compared to conventional CVmethods in previous studies.

Figure 2 shows the dependence of Vfb on implant dose.The 950 Å thermal oxides were repeatedly wet-etchedto provide measurements at several oxide thicknesses.The Vfb behavior is similar to the dependence ofthreshold voltage on implant dose, as outlined here.

Consider a thermal oxide with initial total oxide chargewhich is much lower than the contamination level thatmust be detected. We assume that the phosphorouscontamination is incorporated in the near-surfaceregion of the silicon, but not in the oxide (as in Figure3a; this assumption was verified experimentally withSIMS and COS analysis). In CV or COS testing, a neg-

ative charge density equal to Dphos must be applied tothe oxide surface to pull the underlying silicon to theflatband condition (Figure 3b). The resultant voltagescales linearly with Tox and Dphos (the probe-to-siliconworkfunction difference and 2nd order band bendingeffects are neglected in the following equations):

Note that while Vfb is an excellent indicator of N-skincontamination on relatively thick oxides (Tox>200 Å),the sensitivity drops steadily as the oxide thickness isdecreased (see, for instance, the 300 Å oxide in Figure 2).

The Quantox is also capable of measuring the totaloxide charge, Qtot, a parameter that contacting tech-niques such as conventional CV are not able to measure.The Qtot parameter is distinctly different from the Vfbmeasurement, since it’s sensitivity does not fall as Toxis reduced. Again assuming that the oxide total chargeis much less than the dose of contaminant, we find(neglecting 2nd order band bending effects):

The Qtot parameter is often used on thin gate oxides(down to 20 Å), where conventional Vfb measurementsprovide a poor signal-to-noise ratio. Figure 4 showsQtot acquired on the same set of phosphorous contami-nated samples. As before, the samples were repeatedlywet-etched to demonstrate the sensitivity of the tech-nique as a function of Tox.

V fb

(Vol

ts)

Phosphorous (#/cm2)0.00E+00-9

-8

-7

-6

-5

-4

-3

-2

-1

0

5.00E+11 1.00E+12 1.50E+12 2.00E+12 2.50E+12 3.00E+12 3.50E+12

950 Å

800 Å

700 Å

300 Å

Figure 2. Phosphorous implant dose vs. Vfb as measured using COS

techniques.

A B

EF

+++++

+++++

–––––

–––––

x

p-Si

n-skin

E

SiO2 SiO2

Figure 3. Simplified band diagrams for a) phosphorous N-skin, and b)

phosphorous N-skin pulled to the flatband condition by negative sur-

face charge. To first order, the surface charge density at the flatband

condition equals the phosphorous dose.

Qsurface flatband = DPhos

VFB =DPhos =

DPhos • Tox

Cox εox

Qsurface flatband = –Qtot = DPhos

F E A T U R E S


Dit does not show any significant increases upon differ-ing levels of phosphorous implantation, except in thecase at high dose of phosphorous in the 3E12 #/cm2

range, shown in Figure 5. This shows that thesilicon/silicon dioxide interface is not a factor in influ-encing Vfb and Qtot measurements. The oxidation atpost implant was able to pacify any damage that mayhave incurred at the silicon/silicon dioxide interfaceduring the implant. Upon higher doses at and above3E12 #/cm2, however, implantation damages to the silicon/silicon dioxide interface creates a significantjump in Dit for all oxide thicknesses. Dit is effected byimplant damage but not effected by phosphorous pileup at the silicon/silicon dioxide interface.

Secondary Ion Mass Spectroscopy (SIMS) was used onsister wafers with implant levels similar to the onesused in the study to show the doping profile. The depthof dopant for phosphorous after oxidation on thesewafers ranged from 600 to 1500 Å into the silicon.This shallow depth is due to the accumulation of phos-phorous in the near-surface region of the silicon. This

depth was too shallow to be measured by conventionaldoping techniques, including COS and CV. The pulseddoping measurements, a technique used by COS, werenot able to monitor the effects of the shallow phospho-rous contamination in dose levels explored in this study.

The changes in Vfb and Qtot due to phosphorousimplants in the doses used in this study were significant.These changes will severely alter the device electricalcharacteristics and parameters. This has been indepen-dently confirmed by extended flow experiments thatwere tested at metal 1 using a conventional parametrictest.

SummaryCOS measurement technology is an in-line non-contactmethod that provides timely feedback for monitoringpossible phosphorous contamination from various sources.Vfb maintains good sensitivity on samples with oxidethicknesses down to 300 Å, although the sensitivity isexpected to scale with Tox. Qtot measurements retainhigh sensitivity even on oxides with thicknesses of lessthen 300 Å. This is in contrast to the Vfb measurementsin Figure 2, where the measurement sensitivity decreasedas Tox was reduced. The Qtot, therefore, is the preferredmonitoring measurement for oxide thicknesses of lessthen 300 Å.

References1. “Silicon Processing, Vol. 1” S Wolf and R. N. Tauber, Lat-

tice Press, Sunset Beach CA (1986). 2. In line Charge-trapping Characterization of dielectrics for

sub-0.5 um CMOS Technologies, P. K. Roy, C. Cha-con, Y. Ma, G.S. Horner Mat. Res. Soc. Symp. Proc. Vol.473 (1997).

3. “Oxynitridation-Enhanced Diffusion of Phosphorus in<100> Silicon” N. K. Chen and C. Lee, Elect. Chem.Soc. Vol. 142, No. 6 (1995).

4. Phosphorous-induced positive charge in native oxide of sil-icon wafers, H. Shimizu, C. Munakta, Appl. Phys. Lett.,64 (26), pp. 3598-3599, 27 June 1994.

5. M.S. Fung and R.L. Verkuil, (Spring Electrochemical Meet-ing, abstract no. 169, (1988)).

6. Replacing C-V Monitoring with NON Contact COSCharge Analysis, K. Catmull, R. Cosway, B. Lethererand G. Horner, Mat. Res. Soc. Symp. Proc. Vol. 473(1997).


D tot

(#/

cm2 )

Phosphorous Implant (#/cm2)0.00E+00

0.00E+00

5.00E+11

1.00E+12

1.50E+12

2.00E+12

2.50E+12

5.00E+11 1.00E+12 1.50E+12 2.00E+12 2.50E+12 3.00E+12 3.50E+12

950 Å

800 Å

700 Å

300 Å

Figure 4. Phosphorous implant dose vs. Qtot using COS measurement

techniques.

D it (

#/Ev

cm

2 )

Phosphorous Implant (#/cm2)0.00E+00-9

-8

-7

-6

-5

-4

-3

-2

-1

0

5.00E+11 1.00E+12 1.50E+12 2.00E+12 2.50E+12 3.00E+12 3.50E+12

950 Å

800 Å

700 Å

300 Å

Figure 5. Phosphorous implant dose vs. Dit using COS measurement

techniques.

F E A T U R E S

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Product NewsiSupport™iSupport is a fast, comprehensive and secure on-line customer support offeringthat enables KLA-Tencor’s technical support and applications engineers toremotely access data from KLA-Tencor tools and operate them in real timeto diagnose and rapidly resolve problems when they occur—all via a secureon-line connection controlled by the customer at all times. iSupport is muchbroader than remote diagnostics, providing continuous, automated monitoring,problem detection and notification, equipment run-time and real-time per-formance reports and analysis, secure and safe remote diagnostics and problemresolution. With iSupport, any assistance that doesn’t require parts replacementcan be quickly and completely resolved on-line. This is accomplished byinstalling a diagnostic server to monitor KLA-Tencor tools in the customer’sfab. The diagnostic server is connected to KLA-Tencor’s On-line SupportCenter where authorized support personnel provide immediate help at thefirst sign of an equipment problem. The ability to provide rapid on-lineassistance to our customers, as well as real-time equipment performance andprocess data will result in higher KLA-Tencor tool productivity, improvingour customers’ Cost of Ownership and asset utilization. iSupport connectivityis designed into the most recent KLA-Tencor tools and will be engineeredinto all future KLA-Tencor product lines.

AIT III The AIT III is the newest member of KLA-Tencor’s production-proven AITfamily, and has the increased sensitivity needed to meet the production pat-tern tool monitoring requirements of the 0.13 micron technology node. Itfeatures improved low-angle illumination and low-angle optics, as well asnew noise suppression techniques, to deliver higher throughput darkfieldinspection. Customizable hard mask apertures enable optical filtering toenhance defect capture at specific process layers. These features, as well as anadditional smaller laser spot size and a collection channel for high angle scatter,improve defect detection on dense patterns as well as enhance defect captureof CMP microscratches and low profile (flat) pattern defects. The AIT III is300 mm capable and customers can upgrade their AIT II tools to AIT IIIperformance.

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