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Asian IBIS Summit 2005 1
Asian IBIS Summit 2005Asian IBIS Summit 2005
Simulation with IBIS in Tight Timing Budget Systems
SUI,SHIJUSUI,[email protected][email protected]
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Asian IBIS Summit 2005 2
Agenda
Basis of system timing analysis Simulation with IBIS in tight
timing budget
systems Analysis methods
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Timing Analysis Basis
Systematic timing analysis identifies Timing topology Setup and
hold time margins The risk of timing violations
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Common-Clock Synchronous System
Timing topology
H
o
l
d
D0
D1
D2
D0
D1
D2
ClockDriver
Driving Receiving
Tco
Flight Time
S
e
t
u
p
1
2
3
4
H
o
l
d
D0
D1
D2
D0
D1
D2
ClockDriver
Driving Receiving
Tco
Flight Time
S
e
t
u
p
1
2
3
4
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Timing Margins of CCS System
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Loose Timing Budget System Analysis
Definition Required inputs
Timing topology Component-level timing data Operating clock
frequency Approximated flight time and guard band
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Tight Timing Budget System Analysis
Definition Required inputs
Timing topology
Component-level timing data
Operating clock frequency
Simulation with component models is mandatory
More sophisticated numerical processing needed
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IBIS Models Do Good Job in Simulation
Available Effective
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Flight Time
Flight time vs. propagation delay Propagation delay The sum of
T-line delays in the path
Flight time The time it takes the data out from the driver to
settle at the
receivers input
For tight budget designs the flight time should be simulated
with cautions
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Flight Time Simulation
Questions Is delay1 flight time? What are delay2 and delay3
?
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Flight Time Simulation with IBIS
Cautions Check component datasheet and IBIS model
Avoid double counting C_comp and load
Receiver thresholds
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IBIS vs. Datasheet Consistency
Test loads should match[Model] output
Model_type 3-state
Polarity Inverting
Enable Active-Low
Vmeas =1.5v
Cref =50pf
Rref = 500
Vref = 0.000
In datasheet
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Tco Measurement
Din
Clock
OutputBuffer
InternalLogic
Tco
Clocktriggersat t = 0
Vmeas
TestLoad 0
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Avoid Double Counting
Avoid double counting output C_comp Avoid counting both test
load and load Method 1
Compensate from simulated flight time Method 2
Subtract their effect from Tco
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Negative Flight Time
Negative flight time happens whenTest load for Tco measurement
is heavier
than actual loadThe interconnect is short
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Include Corners in Simulation
Parts behave diversely Simulate including strong and weak
buffers
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Receiver Thresholds
Test example
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Receiver Thresholds
Use Vih and Vil as initial choice Use Vth when available IBIS
Ver 4.0
[Receiver Thresholds] sub-parameters Vth,Vth_min,Vth_max
Vinh_ac,Vinl_ac, Vinh_dc,Vinl_dc Tslew _ac
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Guard Band Time
Effects likely not included in your simulation Simultaneous
switching output Ver4.0 and earlier models do not include SSO in
data
tables Crosstalk Inter-symbol interference Power supply
noise
Guard band time ensures margins existence Obtained from
simulation or measurements
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Deal with Complex Topology
ExampleClock
DoutData
Din
Device1
Device2 Device3
Device4
OscDriver1 Driver2
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Deal with Complex Topology
Adding components in path Path delay deviations increase Timing
margins decrease Alternative analysis methods are needed to
put the simulated interconnection delays together
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Timing Analysis Methods
Worst case timing analysis Statistical timing analysis
Root Sum Square timing analysis Monte Carlo timing analysis
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Worst Case Timing
Path delay Maximum worst-case path delay
Minimum worst-case path delay
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Statistical Timing Analysis(1)
Root sum square timing analysisMaximum RSS path delay
Minimum RSS path delay
22pathpath )typmax(typ1)max1(typ delay RSSmax NtNttttt pppp
+++=
22pathpath )mintyp(min1)typ1(typ delay RSSmin NtNttttt pppp
++=
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Statistical Timing Analysis(2)
Monte Carlo timing analysis By random sampling delay values
determines the timing attribute probability distribution
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Conclusion
Cautions with simulation in tight timing budget system Check
component test load Avoid double counting
Receiver thresholds Simulated results analysis methods
Worst case RSS Monte Carlo
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References:
James E. Buchanan ,Signal and Power Integrity in Digital Systems
(TTL, CMOS, & BiCMOS), McGraw-Hill Inc., ISBN 0-07-008734-2
Stephen H. Hall, High speed Digital Systems Design, McGraw-Hill
Inc., ISBN: 0-471-36090-2
Todd Westerhoff ,Closing the loop between timing analysis and
signal integrity Cadence Design System
Simulation with IBIS in Tight Timing Budget SystemsAgendaTiming
Analysis BasisCommon-Clock Synchronous SystemTiming Margins of CCS
SystemLoose Timing Budget System AnalysisTight Timing Budget System
AnalysisIBIS Models Do Good Job in SimulationFlight TimeFlight Time
SimulationFlight Time Simulation with IBISIBIS vs. Datasheet
ConsistencyTco MeasurementAvoid Double CountingNegative Flight
TimeInclude Corners in SimulationReceiver ThresholdsReceiver
ThresholdsGuard Band TimeDeal with Complex TopologyDeal with
Complex TopologyTiming Analysis MethodsWorst Case TimingStatistical
Timing Analysis(1)Statistical Timing
Analysis(2)ConclusionReferences:
