1120 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 42, NO. 6, JUNE 1995

Subthreshold Characteristics of Fully Depleted Submicrometer SO1 MOSFET’ s

TOITLKIY c. Hsiao, Student Member, IEEE, and Jason C. S . Woo, Member, IEEE

Abstract-In this paper, an analytic current-voltage model in the subthreshold regime for submicrometer fully depleted (FD) silicon-on-insulator (SOI) MOSFET’s is presented. This model takes into account the dependence of the effective depleted charge on the drain bias and the voltage drop in the substrate region underneath the buried oxide. In addition to predicting accurate subthreshold current-voltage characteristics and subthreshold slope, this model can be used to predict important Short Channel Effects (SCE) such as the threshold voltage roll-off and Drain- Induced Barrier Lowering (DIBL). This model is verified by comparison to a two-dimensional device simulator, MEDICI. Good agreement is obtained for SO1 Channel lengths down to 0.25 pm.

I. INTRODUCTION

HE requirement of state-of-the-art VLSI technology is T to use deep-submicrometer MOS transistors to achieve higher packing density and faster speed, together with a low voltage supply, 1-1.5 V, to minimize the power consump- tion. MOS transistors fabricated on fully depleted Silicon-On- Insulator (SOI) substrates have been shown to be a promising technology. Some of its advantages over bulk MOSFET’s and its partially depleted counterparts include alleviated short channel effect [ 11-[3], and improved subthreshold character- istics [4], owing to the thick buried oxide. For low power application in deep submicrometer channel lengths, Drain- Induced Barrier Lowering (DIBL) becomes a serious problem. It can lead to high off-state leakage current, adding another component of power consumption. To address this issue, an analytic model of the subthreshold regime is necessary. Subthreshold characteristics were modeled in [5] with limited discussion on DIBL. A charge-sharing model was proposed to characterize the threshold voltage and the depletion charge associated with the gate [6], [7]. However, its dependence on the drain bias was not clearly considered. In this work, we report an analytic subthreshold current-voltage model, accounting for the dependence of the effective depleted charge under the gate control on the drain bias. As a result, DIBL effects can be predicted. Also incorporated is the voltage drop in the substrate region underneath the buried oxide. The results are compared to a two-dimensional simulator, MEDICI [8], over a wide range of channel lengths and film thicknesses. Good agreement is obtained for channel lengths down to 0.25

Manuscript received September 9, 1994; revised December 16, 1994. The review of this paper was arranged by Associate Editor C.-Y. Lu. This work was supported by the Semiconductor Research Cooperation (SRC).

The authors are with the University of Califomia, Los Angeles, Department of Electrical Engineering, Los Angeles, CA 90024 USA.

IEEE Log Number 9410584.

vGf vDS

T r p - Substrate

d VGb

Fig. 1. N-channel MOSFET transistor on a thin-film SOL

pm. Together with our modeling of the I-V characteristics in the linear and saturation regions [9], the potential of thin film SO1 for deep submicrometer CMOS can be properly evaluated.

11. PHYSICAL MODEL The SO1 MOSFET under investigation is a fully depleted

NMOS, as shown in Fig. 1, where Tof and Tot, are the thicknesses of the front and back oxide, respectively, and Tsi is the film thickness. The applied bias is V G ~ at the front gate and VGb at the back gate (substrate bias). The source node (Vs) is grounded as a voltage reference. Axes are chosen so that the x-axis is along the channel from source to drain, and the y-axis is from the front oxide to the buried oxide.

When the film is fully depleted, the front and back gates compete for the charge in the film body. In the film, the Poisson equation to be solved is

where NA is the film doping concentration, and E , is the silicon permittivity. An abrupt junction and uniform doping are assumed here so that the potentials in the film and the substrate vary quadratically with the distance. The total potential drop in the substrate, Vs&, is considered for completeness. This is a modification of the model proposed in [6]. We further assume

0018-9383/95$04.00 0 1995 IEEE

HSIAO AND WOO: SUBTHRESHOLD CHARACTERISTICS OF FULLY DEPLETED SUBMICROMETER SO1 MOSFET'S 1121

Vbi+VDS

vbi vGf \ vDS

I L s \ ILdI

Fig. 2. area controlled by the front-gate as in a trapezoidal region.

Schematic representation of the effective depleted charge per unit

that no charge exists in the oxides so that the potential drops linearly in both oxide regions.

For a fully depleted film, the depletion charge is shared by the source, front gate, and the drain junctions. Practically, it is not possible to partition exactly how much charge is controlled by the gate, taking into account the drain bias. However, it is reasonable to use a model similar to Taylor's [lo] for the bulk MOSFET and calculate the effective depleted charge per unit area controlled by the front gate as the charge in the trapezoidal region showed in Fig. 2:

where Qb = -qNATsi is the fully depleted charge in the film,

(3)

(4)

and

E e f f l l E e f f 2 are the effective lateral electric fields at the front interface between channel and sourceldrain, which can be defined as

and

cox VGf - v , f ~ - $ s f o

Tof + f a y

+ by (8)

E e f f s and Eeff4 are associated with the back interface and can be obtained similarly. In calculating these electric fields, the first term is due to the depletion charge of the abrupt p-n junction [ 111, whereas the second and third terms are due to the fringing fields with fitting parameters fa and fo estimated as in [12]. V i B and V i B are the flat-band voltages of the front and back gates, and cox is the permittivity of Si02.

In (3) to (8), ?,bsfo and $,,bo are the front and back surface potentials under zero drain bias, which are constant along the source to drain. Under a nonzero drain bias, most of the nonuniformity in the surface potential drops rapidly in a small distance from drain end [13]. In the two bases of the trapezoid, the potential varies slightly, and is assumed to be constant, which is verified by MEDIC1 simulations. Taylor's charge sharing model explains that the increase of subthreshold current is inversely proportional to channel length. However, to take into account the potential banier lowering, which further increases the current exponentially, the front interface potential under drain bias is calculated as

cox vbi + VDS - VGf + v , f ~ T0.f

where Cof = to, I Tof is the front gate oxide capacitance, Cob = E,, Tob iS the buried oxide capacitance, and Csb iS Csi (= cs I Ts;) in series with Cob. When VDS increases, Q b ( e f f ) decreases, and $ s f drops accordingly.

The calculation of the voltage drop in the substrate is based on the continuity of the transverse electric field in the interface. At the film and buried-oxide interface, tsEsb(T&) = to,Esb(TL), where E,b(Tsi) is the electric field at the in- terface of the silicon film and buried oxide. Similarly, at the substrate and buried-oxide interface, we have EsELb = foxELub, where Esub is the electric field in the interface of buried oxide and substrate. E,b(T;) = ELub if the charge in the buried oxide is negligible. Consequently, we have E L b = Esb(T&). If the buried oxide-substrate interface is depleted, we can approximate Vsub by

Esb can be calculated from Gauss' theorem as

where

1122

~ ~ ( 1 0 1 6 ~ - 3 ) 15.3 11.98 9.95

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 6, JUNE 1995

8.58 11.86 9.95 8.03 6.08

400 E v

LL

8 j 300 2 s 200 P

W

!i

n

$ loo

F 0,

cn W a

12 10 Tef (.m) 12 15 20

Ts;(nm) 60 1 80 I 100 1 120 100

Tsi-120nm

D--o Ts=lOOnm Ts= 80nm Tsi- 60nm

I 0.2 0.4 0.6 0.8

30.31

44.63

54.18

- -

60.96 L(pm) - 0.30 73.08 67.91 63.33 59.22 64.96 63.33

0.50 83.42 80.04 76.97 74.16 77.96 76.97

0.75 88.80 86.45 84.30 82.30 84.96 84.30

1.00 91.55 89.75 88.09 86.55 88.59 88.09

75.54

83.34 -

CHANNEL LENGTH (pm) 87.37 - - Fig. 3. Threshold voltage roll-off, VT~(L = 1 p m ) - Vi-f(L). versus

channel length for different film thicknesses of an SO1 NMOS. (W = 10 pm, Tob = 400 nm, VDS = 0.1 v, VGb = 0 v, and v~f(L = 1 pm) = 0.4 v.)

Note that the potential distribution in the buried oxide was modeled more rigorously in [ 141 where the potential variation deviated from linearity near the film and buried oxide interface at x = L / 2. However, simulations also show that near x = 0 (source end) or x = L (drain end), the potential in the buried oxide drops linearly. Therefore, the derivation of Vsub

in (10) is a coarse approximation, but gives sufficient physical meaning for the substrate depletion effect (see discussion).

With (15) and (16), we arrive at an analytic expression for the subthreshold current as

111. SUBTHRESHOLD CURRENT AND SUBTHREsHOLD SWING

In the subthreshold region, the depletion charge is much larger than the inversion charge, and diffusion current is expected to be dominant. However, the drift current can still contribute to the total current flow. From the Boltzmann transport equation, we have

In (18), Csub is defined as €s/Ysub, if ysub is smaller than Tsi. If ysub is larger than Tsi. Csub = c s b . YSUb is the depletion width when $ s f = 1.5 4 ~ .

From (17), our model predicts the subthreshold swing is

where VT = y , & is the Fermi potential, and

which can be further shown to be

After integration, the current density is expressed as

where

where klow is the low field mobility [9], and $ s f explicitly includes DIBL as calculated in (9).

The subthreshold current is equal to the integration of the current density over the cross section of the effective channel depth y e f f [13], [15]. y e f f is related to the front surface transverse electric field as

Iv. RESULTS AND DISCUSSION

To investigate the threshold voltage roll-off for short channel SO1 NMOSFET's, we use (2) to calculate Q b ( e f f ) / Q b for different device parameters referenced to a threshold voltage of VTf = 0.4 V for 1.0 pm channel length. Here the threshold voltage is defined as the front gate bias when I D S / ( W k e f f ) = A. The results are shown in Table I. From Table I, we notice that:

HSIAO AND WOO: SUBTHRESHOLD CHARACTERISTICS OF FULLY DEPLETED SUBMICROMETER SO1 MOSFET'S

w U

O0.0 0.2 0.4 0.6 0.8 CHANNEL LENGTH (pm)

Fig. 4. Threshold voltage roll-off, V T ~ ( L = 1 p m ) - v~f(L). versus channel length for different drain biases of an SO1 NMOS. (W = lOpm, ~~f = 120 A, Ts, = 100 nm, Tob = 400 nm, N A = 9.95 x 10"%m-~, and VGb = 0 v.)

10-2

h : 10-4 n

!- z W

3 0

-

106

z d 10" 0

L =

0.5 1 .o 1.5 2.0 10-10

-0.5 0.0 GATE VOLTAGE V G ~ (V)

Fig. 5. Drain current versus front-gate bias in the subthreshold and linear regions for different channel lengths. (W = l o p m, Tof = 12 nm, Tsz = 100 nm, Tob = 400 nm, vDS = 0.1 V, v G ~ = o V, N A = 1 0 ' ~ c m - ~ , and L = 0.25/0.5pm.)

1) To achieve a fixed threshold voltage at L = l p m , the doping concentration is higher for thinner film or smaller gate oxide thickness. This implies that at the same doping level, VTf tends to be higher for small Ts; or T,f,

2) Short channel effect is more serious for thicker films because they are more bulk-like.

3) Devices with larger front gate oxide thickness have more degradation in threshold voltage roll-off because the front gate field supports less depletion charge from the film body.

Fig. 3 shows the threshold voltage roll-off versus channel length for different film thicknesses, based on the data of Table I. Fig. 4 exhibits the predicted V T ~ roll-off for different drain voltages, with V T ~ equal to 0.4 V when L = 1 pm and VDS = 0.1 v.

Figs. 5 to 7 show the drain current versus the front-gate bias ranging from subthreshold to linear regions for 0.25-pm

1 0 2

A

10-4 n

I- z -

; 106 3 0 z

10" 0

10-10 I I

I 0.0 0.5 1 .o 1.5 2.0 GATE VOLTAGE V G ~ (V)

1123

Fig. 6. Drain current versus front-gate bias in the subthreshold and linear regions for different film thicknesses. (W = 10pm. L = 0 . 2 5 ~ 1 ~ Tof = 12 nm, Tob = 400 nm, v ~ s = 0.1 v, VGb = 0 v, N A = 1017Cm-3, and Ts; = 50/100 nm.)

10-2

5 10-4

: 106

$ IO"

v) a I- z U 3 0

-

z 0

10-10

- MODEL

GATE VOLTAGE V G ~ (V)

Fig. 7. Drain current versus front-gate bias in the subthreshold and linear regions for different front-gate oxide thicknesses. (W = lOpm, L = 0.25pm, Tsl = 100 nm, Tob = 400 nm, VDS = 0.1 V, VGb = 0 V, N A = l O l ? ~ m - ~ , and Tof = 6/12 nm.)

channel length with different device parameters. These results are compared to MEDIC1 simulations and good agreement is shown. Using the model, the DIBL phenomenon in thin film SO1 MOSFET's is examined. We define VDIBL as the decrease in gate voltage required to reach the specified drain current level when the drain voltage is increased from a low drain bias (VDS = 0.1 V) to a higher drain bias (VDH) [16]. Typical results for two channel doping levels are shown in Figs. 8 and 9. The subthreshold swing versus channel length plots are shown in the inset.

From these figures, we find out that if we decrease the film doping, the depletion width at both the drain and source ends will increase significantly, causing less gate control over the channel charge and an increase in the subthreshold swing. Nevertheless, the effect of film thickness on S is not important for low drain bias because the barriers that the minority carriers have to surmount are nearly at the same level once the film is fully depleted. For short channel SOI, the degradation of S is due to the two dimensional nonuniformity of the electric

1124 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 6, JUNE 1995

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160

140

buried oxide. The bulk silicon substrate acts as a ground plane and diverts the electric fields downward. This phenomenon is opposite to the aforementioned effect of substrate depletion. However, thinner buried oxides can imply slightly higher source/drain junction capacitances, and possibly higher sub- threshold current swing. Its trade-off needs to be investigated

120

E 100 s -1 more carefully. ; 80 - >

60

40

20

V. CONCLUSION

Analytic output characteristics of fully depleted SO1 MOS- FET’s in the subthreshold regime have been modeled, taking

0 0.0 0.5 1 .o 1.5 2.0 into account the drain bias dependent depletion charge in the film and the voltage drop in the substrate. The model DRAIN VOLTAGE VDH (V)

Fig. 8. I ~ s / ( w / L , f f ) =

Drain-Induced-Barrier-Lowering, VDIBL, versus drain bias, VDH. A, W = 10pm. Tof = 7 nm, Ts; = 50 nm, Tob

= 350 nm, VGb = 0 v, and N A = 1017Cm-3.

DRAIN VOLTAGE VDH (V)

field in the gate oxide and increased charge sharing of the source and drain [17]. In our model, after the film is fully depleted, the change in the effective depletion charge due to an increase of the gate voltage is less than 1%. The increase in gate voltage will have almost no effect on Q b ( e f f ) as proposed in [4]. However, the effective channel length does depend on the gate bias and will contribute to the degradation of subthreshold swing.

Although the expressions for E e f f a and E e f f 4 were not explicit, the incorporation of the depletion region in the substrate does influence the charge partition in the SO1 film. If there is more depletion charge in the substrate, there will be a large potential drop. The increase of Vsub in turn brings down the effective lateral electric fields in the film and buried oxide interface. Consequently, the front gate further loses its control over the film depletion charge, resulting in more severe DIBL and threshold roll-off.

Our model also predicts that thinner buried oxide can potentially alleviate the short channel effect due to the increase of lateral electric fields at the interface of the source/drain and

has been compared to MEDICI simulation results with film thicknesses and channel lengths varying over a wide range. Good agreement is obtained. This model can be used to predict DIBL and subthreshold swing of SO1 MOSFET’s for circuit simulation in the submicrometer regime. With appropriate modification, all the models in this study are applicable to PMOS SO1 MOSFFiT’s as well.

REFERENCES

[ I ] J.-P. Colinge, “Thin-film SO1 technology: The solution to many submi- cron CMOS problems,”lEEE IEDM Tech. Dig., pp. 817-820, 1989.

[2] K. K. Young, “Short-channel effect in fully depleted SO1 MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, pp. 399-402, 1989.

[3] S. Veeraraghavan and J. G. Fossum, ‘Short-channel effect in SO1 MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, pp. 522-528, 1989.

[4] J.-P. Colinge, “Subthreshold slope of thin-film SO1 MOSFET’s,” IEEE Electron Device Lett., EDL-7, pp. 244-246, 1986.

[5] M. Matloubian, C. D. Chen, B.-y. Mao, R. Sundaresan, and G. P. Pollack, “Modeling of the subthreshold characteristics of SO1 MOS- ET’S with floating body,” IEEE Trans. Electron Devices, vol. 37, pp. 1985-1 993, 1990.

[6] H.-K. Lim and J. G. Fossum, “Threshold voltage of thin-film silicon- on-insulator (SOI) MOSFET’s,” IEEE Trans. Electron Devices, ED-30, pp. 1244-1251, 1983.

[7] S. Veeraraghavan and J. G. Fossum, “A physical short-channel model for the thin-film SO1 MOSFET applicable to device and circuit CAD,” IEEE Trans. Electron Devices, vol. 35, pp. 1866-1874, 1988.

[8] Technology Modeling Associates, Inc., “TMA MEDICI: Two- dimensional device simulation program.”

[9] T. C. Hsiao, N. A. Kistler, and J. C. S. Woo, “Modeling the I-V characteristics of fully depleted submicrometer SO1 MOSFET’s,” IEEE Electron Device Lett., vol. 15, pp. 4547, 1994.

[lo] G. W. Taylor, “Subthreshold conduction in MOSFET’s,” IEEE Trans. Electron Devices, ED-25, pp. 337-350, 1978.

[ I l l S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York Wiley, 1981

[12] D. Frohman-Bentchkowsky and A. S. Grove, “Conductance of MOS transistors in saturation,” IEEE Trans. Electron Devices, ED- 16, pp.

[13] T. A. Fjeldly and M. Shur, ‘Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, pp. 137-145, 1993.

[I41 H.-0. Joachim, Y. Yamaguchi, K. Ishikawa, Y. Inoue, and T. Nishimura, “Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SO1 MOSFET’s down to 0.1 pm gate length,” IEEE Trans. Electron Devices, vol. 40, pp. 1812-1817, 1993.

[I51 D. R. Poole and D. L. Kwong, “Analytical modeling of the subthreshold current in short-channel MOSFET’s,” IEEE Electron Device Lett., EDL- 7, pp. 340-343, 1986.

[I61 N. A. Kistler “Scaling of MOSFET’s in fully-depleted silicon-on- insulator for deep-submicrometer VLSI,” Ph.D dissertation, pp. 4041, 1994.

[17] J. G. Fossum, S. Krishnan, and P. C. Yeb “Performance limitations of deep-submicron fully depleted SO1 MOSFET’s,” SO1 Conj Proc., 1992.

108-113, 1969.

HSIAO AND WOO: SUBTHRESHOLD CHARACTERISTICS OF FULLY DEPLETED SUBMICROMETER SO1 MOSFET’S 1125

Tommy C. Hsiao (S’94) received the B.S. degree in electrical engineering from National Taiwan University in 1987 and the M.S. and Eng. degrees from the University of Califomia at Los Angeles in 1993 and 1994, respectively.

characterization of SO1 devices in submicrometer regimes, and the fabrication issues as well. His current work is focused on source/drain engineering structures to improve short channel effects, aimed at low power applications.

Jason C. S. Woo (S’83-M’87) received the B.A.Sc. degree (Hons.) in engineering science from the Uni- versity of Toronto, Ontario, Canada, in 1981, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1982 and

He is currently a Professor in the Department of Electrical Engineering at the University of Cal- ifomia, Los Angeles. His research interests are in the physics and technology of novel device and device modeling. He has worked on low temperature

devices for VLSI and space applications, SO1 BiCMOS and GeSi BiCMOSi. He has authored or co-authored over 50 papers in technical journals and refereed conference proceedings in these areas.

His research interests include modeling and 1987, respectively.