Sub-Family Reference ManualK22F Sub-Family Reference Manual , Rev. 3, 7/2014 2 Freescale Semiconductor, Inc

K22F Sub-Family Reference ManualSupports: MK22FN256VDC12, MK22FN256VLL12,

MK22FN256VMP12, MK22FN256VLH12

Document Number: K22P121M120SF8RMRev. 3, 7/2014

K22F Sub-Family Reference Manual , Rev. 3, 7/2014

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1About This Document

1.1 Overview.......................................................................................................................................................................47

1.1.1 Purpose.........................................................................................................................................................47

1.1.2 Audience......................................................................................................................................................47

1.2 Conventions..................................................................................................................................................................47

1.2.1 Numbering systems......................................................................................................................................47

1.2.2 Typographic notation...................................................................................................................................48

1.2.3 Special terms................................................................................................................................................48

Chapter 2Introduction

2.1 Overview.......................................................................................................................................................................49

2.2 Module Functional Categories......................................................................................................................................49

2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................50

2.2.2 System Modules...........................................................................................................................................51

2.2.3 Memories and Memory Interfaces...............................................................................................................52

2.2.4 Clocks...........................................................................................................................................................52

2.2.5 Security and Integrity modules....................................................................................................................52

2.2.6 Analog modules...........................................................................................................................................53

2.2.7 Timer modules.............................................................................................................................................53

2.2.8 Communication interfaces...........................................................................................................................54

2.2.9 Human-machine interfaces..........................................................................................................................55

2.3 Orderable part numbers.................................................................................................................................................55

Chapter 3Chip Configuration

3.1 Introduction...................................................................................................................................................................57


Freescale Semiconductor, Inc. 3


3.2 Core modules................................................................................................................................................................57

3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................57

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................59

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................65

3.2.4 FPU Configuration.......................................................................................................................................66

3.2.5 JTAG Controller Configuration...................................................................................................................66

3.3 System modules............................................................................................................................................................67

3.3.1 SIM Configuration.......................................................................................................................................67

3.3.2 System Mode Controller (SMC) Configuration...........................................................................................68

3.3.3 PMC Configuration......................................................................................................................................68

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................69

3.3.5 MCM Configuration....................................................................................................................................71

3.3.6 Crossbar-Light Switch Configuration..........................................................................................................71

3.3.7 Peripheral Bridge Configuration..................................................................................................................73

3.3.8 DMA request multiplexer configuration......................................................................................................74

3.3.9 DMA Controller Configuration...................................................................................................................77

3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................78

3.3.11 Watchdog Configuration..............................................................................................................................80

3.4 Clock modules..............................................................................................................................................................81

3.4.1 MCG Configuration.....................................................................................................................................81

3.4.2 OSC Configuration......................................................................................................................................82

3.4.3 RTC OSC configuration...............................................................................................................................83




3.5 Memories and memory interfaces.................................................................................................................................84

3.5.1 Flash Memory Configuration.......................................................................................................................84

3.5.2 Flash Memory Controller Configuration.....................................................................................................87

3.5.3 SRAM Configuration...................................................................................................................................87

3.5.4 System Register File Configuration.............................................................................................................89

3.5.5 VBAT Register File Configuration..............................................................................................................90

3.5.6 EzPort Configuration...................................................................................................................................90

3.6 Security.........................................................................................................................................................................91

3.6.1 CRC Configuration......................................................................................................................................92

3.6.2 RNG Configuration......................................................................................................................................92




3.7 Analog...........................................................................................................................................................................93

3.7.1 16-bit SAR ADC Configuration..................................................................................................................93

3.7.2 CMP Configuration......................................................................................................................................101

3.7.3 12-bit DAC Configuration...........................................................................................................................103

3.7.4 VREF Configuration....................................................................................................................................104

3.8 Timers...........................................................................................................................................................................105

3.8.1 PDB Configuration......................................................................................................................................105

3.8.2 FlexTimer Configuration.............................................................................................................................108

3.8.3 PIT Configuration........................................................................................................................................114

3.8.4 Low-power timer configuration...................................................................................................................115

3.8.5 RTC configuration.......................................................................................................................................117

3.9 Communication interfaces............................................................................................................................................118

3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................118

3.9.2 SPI configuration.........................................................................................................................................123

3.9.3 I2C Configuration........................................................................................................................................127

3.9.4 UART Configuration...................................................................................................................................128

3.9.5 LPUART configuration................................................................................................................................130

3.9.6 I2S configuration..........................................................................................................................................131

3.10 Human-machine interfaces...........................................................................................................................................134

3.10.1 GPIO configuration......................................................................................................................................134

Chapter 4Memory Map

4.1 Introduction...................................................................................................................................................................137

4.2 System memory map.....................................................................................................................................................137

4.2.1 Aliased bit-band regions..............................................................................................................................138

4.2.2 Flash Access Control Introduction...............................................................................................................140

4.3 Flash Memory Map.......................................................................................................................................................140

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................141

4.4 SRAM memory map.....................................................................................................................................................141




4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................141

4.5.1 Read-after-write sequence and required serialization of memory operations..............................................142

4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................142

4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................146

Chapter 5Clock Distribution

5.1 Introduction...................................................................................................................................................................147

5.2 Programming model......................................................................................................................................................147

5.3 High-Level device clocking diagram............................................................................................................................147

5.4 Clock definitions...........................................................................................................................................................148

5.4.1 Device clock summary.................................................................................................................................149

5.5 Internal clocking requirements.....................................................................................................................................152

5.5.1 Clock divider values after reset....................................................................................................................153

5.5.2 VLPR mode clocking...................................................................................................................................153

5.6 Clock Gating.................................................................................................................................................................154

5.7 Module clocks...............................................................................................................................................................154

5.7.1 PMC 1-kHz LPO clock................................................................................................................................156

5.7.2 IRC 48MHz clock........................................................................................................................................156

5.7.3 WDOG clocking..........................................................................................................................................157

5.7.4 Debug trace clock.........................................................................................................................................157

5.7.5 PORT digital filter clocking.........................................................................................................................158

5.7.6 LPTMR clocking..........................................................................................................................................158

5.7.7 RTC_CLKOUT and CLKOUT32K clocking..............................................................................................159

5.7.8 USB FS OTG Controller clocking...............................................................................................................160

5.7.9 UART clocking............................................................................................................................................161

5.7.10 LPUART0 clocking.....................................................................................................................................161

5.7.11 I2S/SAI clocking..........................................................................................................................................162




Chapter 6Reset and Boot

6.1 Introduction...................................................................................................................................................................165

6.2 Reset..............................................................................................................................................................................166

6.2.1 Power-on reset (POR)..................................................................................................................................166

6.2.2 System reset sources....................................................................................................................................166

6.2.3 MCU Resets.................................................................................................................................................170

6.2.4 Reset Pin .....................................................................................................................................................171

6.2.5 Debug resets.................................................................................................................................................172

6.3 Boot...............................................................................................................................................................................173

6.3.1 Boot sources.................................................................................................................................................173

6.3.2 Boot options.................................................................................................................................................173

6.3.3 FOPT boot options.......................................................................................................................................174

6.3.4 Boot sequence..............................................................................................................................................175

Chapter 7Power Management

7.1 Introduction...................................................................................................................................................................177

7.2 Clocking modes............................................................................................................................................................177

7.2.1 Partial Stop...................................................................................................................................................177

7.2.2 DMA Wakeup..............................................................................................................................................178

7.2.3 Compute Operation......................................................................................................................................179

7.2.4 Peripheral Doze............................................................................................................................................180

7.2.5 Clock Gating................................................................................................................................................181

7.3 Power Modes Description.............................................................................................................................................181

7.4 Entering and exiting power modes...............................................................................................................................183

7.5 Power mode transitions.................................................................................................................................................184

7.6 Power modes shutdown sequencing.............................................................................................................................185

7.7 Flash Program Restrictions...........................................................................................................................................186

7.8 Module Operation in Low Power Modes......................................................................................................................186




Chapter 8Security

8.1 Introduction...................................................................................................................................................................191

8.2 Flash Security...............................................................................................................................................................191

8.3 Security Interactions with other Modules.....................................................................................................................192

8.3.1 Security Interactions with EzPort................................................................................................................192

8.3.2 Security Interactions with Debug.................................................................................................................192

Chapter 9Debug

9.1 Introduction...................................................................................................................................................................193

9.1.1 References....................................................................................................................................................195

9.2 The Debug Port.............................................................................................................................................................195

9.2.1 JTAG-to-SWD change sequence.................................................................................................................196

9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................196

9.3 Debug Port Pin Descriptions.........................................................................................................................................197

9.4 System TAP connection................................................................................................................................................197

9.4.1 IR Codes.......................................................................................................................................................197

9.5 JTAG status and control registers.................................................................................................................................198

9.5.1 MDM-AP Control Register..........................................................................................................................199

9.5.2 MDM-AP Status Register............................................................................................................................201

9.6 Debug Resets................................................................................................................................................................202

9.7 AHB-AP........................................................................................................................................................................203

9.8 ITM...............................................................................................................................................................................203

9.9 Core Trace Connectivity...............................................................................................................................................204

9.10 TPIU..............................................................................................................................................................................204

9.11 DWT.............................................................................................................................................................................204

9.12 Debug in Low Power Modes........................................................................................................................................205

9.12.1 Debug Module State in Low Power Modes.................................................................................................205

9.13 Debug & Security.........................................................................................................................................................206




Chapter 10Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................207

10.2 Signal Multiplexing Integration....................................................................................................................................207

10.2.1 Port control and interrupt module features..................................................................................................208

10.2.2 Clock gating.................................................................................................................................................209

10.2.3 Signal multiplexing constraints....................................................................................................................209

10.3 Pinout............................................................................................................................................................................209

10.3.1 K22F Signal Multiplexing and Pin Assignments.........................................................................................209

10.3.2 K22F Pinouts................................................................................................................................................214

10.4 Module Signal Description Tables................................................................................................................................218

10.4.1 Core Modules...............................................................................................................................................218

10.4.2 System Modules...........................................................................................................................................219

10.4.3 Clock Modules.............................................................................................................................................219

10.4.4 Memories and Memory Interfaces...............................................................................................................220

10.4.5 Analog..........................................................................................................................................................220

10.4.6 Timer Modules.............................................................................................................................................221

10.4.7 Communication Interfaces...........................................................................................................................223

10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................225

Chapter 11Port Control and Interrupts (PORT)

11.1 Introduction...................................................................................................................................................................227

11.2 Overview.......................................................................................................................................................................227

11.2.1 Features........................................................................................................................................................227

11.2.2 Modes of operation......................................................................................................................................228

11.3 External signal description............................................................................................................................................229

11.4 Detailed signal description............................................................................................................................................229

11.5 Memory map and register definition.............................................................................................................................229

11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................236




11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................238

11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................239

11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................240

11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................240

11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................241

11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................241

11.6 Functional description...................................................................................................................................................242

11.6.1 Pin control....................................................................................................................................................242

11.6.2 Global pin control........................................................................................................................................243

11.6.3 External interrupts........................................................................................................................................243

11.6.4 Digital filter..................................................................................................................................................244

Chapter 12System Integration Module (SIM)

12.1 Introduction...................................................................................................................................................................247

12.1.1 Features........................................................................................................................................................247


12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................249

12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................251






12.2.8 System Device Identification Register (SIM_SDID)...................................................................................262

12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................264




12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................271




12.2.14 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................273

12.2.15 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................274

12.2.16 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................276

12.2.17 Unique Identification Register High (SIM_UIDH).....................................................................................277

12.2.18 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................277

12.2.19 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................278

12.2.20 Unique Identification Register Low (SIM_UIDL)......................................................................................278


Chapter 13Kinetis Flashloader

13.1 Chip-Specific Information............................................................................................................................................279

13.2 Introduction...................................................................................................................................................................279

13.3 Functional Description..................................................................................................................................................281

13.3.1 Memory Maps..............................................................................................................................................281

13.3.2 Kinetis Flashloader......................................................................................................................................281

13.3.3 Start-up Process............................................................................................................................................281

13.3.4 Clock Configuration.....................................................................................................................................282

13.3.5 Flashloader Protocol....................................................................................................................................283

13.3.6 Flashloader Packet Types.............................................................................................................................287

13.3.7 Flashloader Command API..........................................................................................................................294

13.3.8 Flashloader Exit state...................................................................................................................................307

13.4 Peripherals Supported...................................................................................................................................................308

13.4.1 I2C Peripheral..............................................................................................................................................308

13.4.2 SPI Peripheral..............................................................................................................................................310

13.4.3 UART Peripheral.........................................................................................................................................312

13.4.4 USB peripheral.............................................................................................................................................314

13.5 Get/SetProperty Command Properties..........................................................................................................................316

13.5.1 Property Definitions.....................................................................................................................................317

13.6 Kinetis Flashloader Status Error Codes........................................................................................................................319




Chapter 14Reset Control Module (RCM)

14.1 Introduction...................................................................................................................................................................321

14.2 Reset memory map and register descriptions...............................................................................................................321

14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................322

14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................323

14.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................325

14.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................326

14.2.5 Mode Register (RCM_MR).........................................................................................................................327

14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................328

14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................329

Chapter 15System Mode Controller (SMC)

15.1 Introduction...................................................................................................................................................................331

15.2 Modes of operation.......................................................................................................................................................331

15.3 Memory map and register descriptions.........................................................................................................................333

15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................334

15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................335

15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................337

15.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................338


15.4.1 Power mode transitions................................................................................................................................339

15.4.2 Power mode entry/exit sequencing..............................................................................................................342

15.4.3 Run modes....................................................................................................................................................344

15.4.4 Wait modes..................................................................................................................................................346

15.4.5 Stop modes...................................................................................................................................................347

15.4.6 Debug in low power modes.........................................................................................................................350

Chapter 16Power Management Controller (PMC)

16.1 Introduction...................................................................................................................................................................353




16.2 Features.........................................................................................................................................................................353

16.3 Low-voltage detect (LVD) system................................................................................................................................353

16.3.1 LVD reset operation.....................................................................................................................................354

16.3.2 LVD interrupt operation...............................................................................................................................354

16.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................354

16.4 I/O retention..................................................................................................................................................................355


16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................356

16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................357

16.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................358

Chapter 17Low-Leakage Wakeup Unit (LLWU)

17.1 Introduction...................................................................................................................................................................361

17.1.1 Features........................................................................................................................................................361


17.1.3 Block diagram..............................................................................................................................................363

17.2 LLWU signal descriptions............................................................................................................................................364

17.3 Memory map/register definition...................................................................................................................................364

17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................365




17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................369

17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................371



17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................376

17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................377





17.4.1 LLS mode.....................................................................................................................................................379

17.4.2 VLLS modes................................................................................................................................................379

17.4.3 Initialization.................................................................................................................................................379

Chapter 18Miscellaneous Control Module (MCM)

18.1 Introduction...................................................................................................................................................................381

18.1.1 Features........................................................................................................................................................381

18.2 Memory map/register descriptions...............................................................................................................................381

18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................382

18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................382

18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR).....................................................................383

18.2.4 Interrupt Status and Control Register (MCM_ISCR)..................................................................................384

18.2.5 Compute Operation Control Register (MCM_CPO)...................................................................................387


18.3.1 Interrupts......................................................................................................................................................388

Chapter 19Crossbar Switch Lite (AXBS-Lite)

19.1 Introduction...................................................................................................................................................................389

19.1.1 Features........................................................................................................................................................389

19.2 Memory Map / Register Definition...............................................................................................................................390


19.3.1 General operation.........................................................................................................................................390

19.3.2 Arbitration....................................................................................................................................................391

19.4 Initialization/application information...........................................................................................................................392

Chapter 20Peripheral Bridge (AIPS-Lite)

20.1 Introduction...................................................................................................................................................................395

20.1.1 Features........................................................................................................................................................395

20.1.2 General operation.........................................................................................................................................395





20.2.1 Access support.............................................................................................................................................396

Chapter 21Direct Memory Access Multiplexer (DMAMUX)

21.1 Introduction...................................................................................................................................................................397

21.1.1 Overview......................................................................................................................................................397

21.1.2 Features........................................................................................................................................................398




21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................400


21.4.1 DMA channels with periodic triggering capability......................................................................................401

21.4.2 DMA channels with no triggering capability...............................................................................................403

21.4.3 Always-enabled DMA sources....................................................................................................................403


21.5.1 Reset.............................................................................................................................................................405

21.5.2 Enabling and configuring sources................................................................................................................405

Chapter 22Enhanced Direct Memory Access (eDMA)

22.1 Introduction...................................................................................................................................................................409

22.1.1 eDMA system block diagram......................................................................................................................409

22.1.2 Block parts...................................................................................................................................................410

22.1.3 Features........................................................................................................................................................411



22.3.1 TCD memory...............................................................................................................................................413

22.3.2 TCD initialization........................................................................................................................................414

22.3.3 TCD structure...............................................................................................................................................414




22.3.4 Reserved memory and bit fields...................................................................................................................416

22.3.1 Control Register (DMA_CR).......................................................................................................................426

22.3.2 Error Status Register (DMA_ES)................................................................................................................429

22.3.3 Enable Request Register (DMA_ERQ).......................................................................................................431

22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................433

22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................435

22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................436

22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................437

22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................438

22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................439

22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................440

22.3.11 Clear Error Register (DMA_CERR)............................................................................................................441

22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................442

22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................443

22.3.14 Error Register (DMA_ERR)........................................................................................................................445

22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................448

22.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................451

22.3.17 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................453

22.3.18 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................454

22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................454

22.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................455

22.3.21 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................456

22.3.22 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................457

22.3.23 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................458

22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................459

22.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................460

22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................460




22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES)...........................................................................................................461

22.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO)............................................................................................................462

22.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........463

22.3.30 TCD Control and Status (DMA_TCDn_CSR)............................................................................................464

22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES)...........................................................................................................466

22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO)............................................................................................................467


22.4.1 eDMA basic data flow.................................................................................................................................468

22.4.2 Fault reporting and handling........................................................................................................................471

22.4.3 Channel preemption.....................................................................................................................................473

22.4.4 Performance.................................................................................................................................................473


22.5.1 eDMA initialization.....................................................................................................................................478

22.5.2 Programming errors.....................................................................................................................................480

22.5.3 Arbitration mode considerations..................................................................................................................480

22.5.4 Performing DMA transfers..........................................................................................................................481

22.5.5 Monitoring transfer descriptor status...........................................................................................................485

22.5.6 Channel Linking...........................................................................................................................................487

22.5.7 Dynamic programming................................................................................................................................488

Chapter 23External Watchdog Monitor (EWM)

23.1 Introduction...................................................................................................................................................................493

23.1.1 Features........................................................................................................................................................493

23.1.2 Modes of Operation.....................................................................................................................................494

23.1.3 Block Diagram.............................................................................................................................................495

23.2 EWM Signal Descriptions............................................................................................................................................496




23.3 Memory Map/Register Definition.................................................................................................................................496

23.3.1 Control Register (EWM_CTRL).................................................................................................................496

23.3.2 Service Register (EWM_SERV)..................................................................................................................497

23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................497

23.3.4 Compare High Register (EWM_CMPH).....................................................................................................498

23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................499


23.4.1 The EWM_out Signal..................................................................................................................................499

23.4.2 The EWM_in Signal....................................................................................................................................500

23.4.3 EWM Counter..............................................................................................................................................501

23.4.4 EWM Compare Registers............................................................................................................................501

23.4.5 EWM Refresh Mechanism...........................................................................................................................501

23.4.6 EWM Interrupt.............................................................................................................................................502

23.4.7 Counter clock prescaler................................................................................................................................502

Chapter 24Watchdog Timer (WDOG)

24.1 Introduction...................................................................................................................................................................503

24.2 Features.........................................................................................................................................................................503

24.3 Functional overview......................................................................................................................................................505

24.3.1 Unlocking and updating the watchdog.........................................................................................................506

24.3.2 Watchdog configuration time (WCT)..........................................................................................................507

24.3.3 Refreshing the watchdog..............................................................................................................................508

24.3.4 Windowed mode of operation......................................................................................................................508

24.3.5 Watchdog disabled mode of operation.........................................................................................................508

24.3.6 Debug modes of operation...........................................................................................................................509

24.4 Testing the watchdog....................................................................................................................................................509

24.4.1 Quick test.....................................................................................................................................................510

24.4.2 Byte test........................................................................................................................................................510

24.5 Backup reset generator..................................................................................................................................................511




24.6 Generated resets and interrupts.....................................................................................................................................512


24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................513

24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................515

24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................515

24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................516

24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................516

24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................517

24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................517

24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................517

24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................518

24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................518

24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................519

24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................519

24.8 Watchdog operation with 8-bit access..........................................................................................................................519

24.8.1 General guideline.........................................................................................................................................519

24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................520

24.9 Restrictions on watchdog operation..............................................................................................................................521

Chapter 25Multipurpose Clock Generator (MCG)

25.1 Introduction...................................................................................................................................................................523

25.1.1 Features........................................................................................................................................................523

25.1.2 Modes of Operation.....................................................................................................................................527

25.2 External Signal Description..........................................................................................................................................527

25.3 Memory Map/Register Definition.................................................................................................................................527

25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................528









25.3.7 MCG Status Register (MCG_S)..................................................................................................................535

25.3.8 MCG Status and Control Register (MCG_SC)............................................................................................536

25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................538

25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................538




25.4.1 MCG mode state diagram............................................................................................................................540

25.4.2 Low-power bit usage....................................................................................................................................545

25.4.3 MCG Internal Reference Clocks..................................................................................................................545

25.4.4 External Reference Clock............................................................................................................................546

25.4.5 MCG Fixed Frequency Clock .....................................................................................................................546

25.4.6 MCG PLL clock ..........................................................................................................................................547

25.4.7 MCG Auto TRIM (ATM)............................................................................................................................547

25.5 Initialization / Application information........................................................................................................................548

25.5.1 MCG module initialization sequence...........................................................................................................548

25.5.2 Using a 32.768 kHz reference......................................................................................................................551

25.5.3 MCG mode switching..................................................................................................................................551

Chapter 26Oscillator (OSC)

26.1 Introduction...................................................................................................................................................................561

26.2 Features and Modes......................................................................................................................................................561

26.3 Block Diagram..............................................................................................................................................................562

26.4 OSC Signal Descriptions..............................................................................................................................................562

26.5 External Crystal / Resonator Connections....................................................................................................................563

26.6 External Clock Connections.........................................................................................................................................564




26.7 Memory Map/Register Definitions...............................................................................................................................565

26.7.1 OSC Memory Map/Register Definition.......................................................................................................565


26.8.1 OSC module states.......................................................................................................................................567

26.8.2 OSC module modes.....................................................................................................................................569

26.8.3 Counter.........................................................................................................................................................571

26.8.4 Reference clock pin requirements................................................................................................................571

26.9 Reset..............................................................................................................................................................................571

26.10 Low power modes operation.........................................................................................................................................572

26.11 Interrupts.......................................................................................................................................................................572

Chapter 27RTC Oscillator (OSC32K)

27.1 Introduction...................................................................................................................................................................573

27.1.1 Features and Modes.....................................................................................................................................573

27.1.2 Block Diagram.............................................................................................................................................573

27.2 RTC Signal Descriptions..............................................................................................................................................574

27.2.1 EXTAL32 — Oscillator Input.....................................................................................................................574

27.2.2 XTAL32 — Oscillator Output.....................................................................................................................574

27.3 External Crystal Connections.......................................................................................................................................575

27.4 Memory Map/Register Descriptions.............................................................................................................................575


27.6 Reset Overview.............................................................................................................................................................576

27.7 Interrupts.......................................................................................................................................................................576

Chapter 28Flash Memory Controller (FMC)

28.1 Introduction...................................................................................................................................................................577

28.1.1 Overview......................................................................................................................................................577

28.1.2 Features........................................................................................................................................................577







28.4.1 Flash Access Protection Register (FMC_PFAPR).......................................................................................583

28.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)........................................................................................587

28.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)........................................................................................590

28.4.4 Cache Tag Storage (FMC_TAGVDW0Sn).................................................................................................592




28.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)..........................................................................595

28.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)..........................................................................596








28.5.1 Default configuration...................................................................................................................................599

28.5.2 Configuration options..................................................................................................................................600

28.5.3 Speculative reads..........................................................................................................................................600

28.6 Initialization and application information.....................................................................................................................601

Chapter 29Flash Memory Module (FTFA)

29.1 Introduction...................................................................................................................................................................603

29.1.1 Features........................................................................................................................................................604

29.1.2 Block Diagram.............................................................................................................................................604

29.1.3 Glossary.......................................................................................................................................................605

Documents

Sub-Family Reference ManualK22F Sub-Family Reference Manual , Rev. 3, 7/2014 2 Freescale Semiconductor, Inc