Corso di Laurea in Fisica

Study of Pixel Detectors in BCD(Bipolar-CMOS-DMOS)

Technology

Relatore interno: Prof. Valentino Liberali

Relatore esterno: Dott.Mauro Citterio

Correlatore: Prof. Attilio Andreazza

Tesi di laurea di:Stefano Passadore

Matr. n. 826558Codice PACS: 29.40.-n

Anno Accademico 2014 - 2015

Contents

Introduction 1

1 Technologies 31.1 Hybrid Pixel Detector . . . . . . . . . . . . . . . . . . . . . . 31.2 Bipolar-CMOS-DMOS (BCD) . . . . . . . . . . . . . . . . . . 4

2 BCD Test Chip 72.1 Bias Resistance and Sensor . . . . . . . . . . . . . . . . . . . 72.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3 Resistive Feedback . . . . . . . . . . . . . . . . . . . . . . . 102.4 Buffer and ESD PAD . . . . . . . . . . . . . . . . . . . . . . 112.5 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Frequency and Noise Analysis 153.1 MOM Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 153.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2.1 Frequency Response Module . . . . . . . . . . . . . . . 183.2.2 Frequency Response Phase . . . . . . . . . . . . . . . . 19

3.3 Amplifying Circuit . . . . . . . . . . . . . . . . . . . . . . . 213.3.1 Sensor + MOM AC coupling capacitor . . . . . . . . 223.3.2 MOM + Amplifier + Feedback . . . . . . . . . . . . . 233.3.3 Sensor + MOM AC-coupling capacitor + Amplifier +

Feedback . . . . . . . . . . . . . . . . . . . . . . . . . 253.3.4 Frequency Response Module . . . . . . . . . . . . . . . 253.3.5 Frequency Response Phase . . . . . . . . . . . . . . . . 283.3.6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.4 Buffer and ESD pad . . . . . . . . . . . . . . . . . . . . . . . 313.4.1 Frequency Response Module . . . . . . . . . . . . . . . 323.4.2 Frequency Response Phase . . . . . . . . . . . . . . . . 333.4.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.5 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . 34

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3.6 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 373.6.1 Parallel Noise . . . . . . . . . . . . . . . . . . . . . . . 403.6.2 Series Noise . . . . . . . . . . . . . . . . . . . . . . . . 403.6.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 41

4 The KC01 Chip 454.1 Chip and Bonding . . . . . . . . . . . . . . . . . . . . . . . . 45

4.1.1 Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.1.2 Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2 PCB and Measurement Setup . . . . . . . . . . . . . . . . . . 504.3 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Irradiation 635.1 Irradiation effects . . . . . . . . . . . . . . . . . . . . . . . . 63

5.1.1 Displacement . . . . . . . . . . . . . . . . . . . . . . . 635.1.2 Ionization . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2 Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655.2.1 Chip Bonding . . . . . . . . . . . . . . . . . . . . . . . 655.2.2 PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.3 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.3.1 Beam . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.3.2 During Irradiation . . . . . . . . . . . . . . . . . . . . 695.3.3 After Irradiation . . . . . . . . . . . . . . . . . . . . . 715.3.4 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6 Conclusions 75

Bibliography 77

ii

Introduction

This work describes the initial development of a new silicon detector for theupgrade of the ATLAS experiment at the Large Hadron Collider of CERN,the European Laboratory for Particle Physics. The ATLAS experiments is ageneral purpose detector designed to study pp collisions up to 14 TeV centerof mass energy. Currently, ATLAS supports an instantaneous luminosity of2.2 × 1034 cm−2s−1 with the mean number of interactions for bunch cross-ing of about 55 and runs with a trigger output rate of 100 kHz. The HighLuminosity LHC (HL-LHC) is a planned upgrade of LHC. It will start colli-sion around 2024 with an instantaneous luminosity of 5× 1034 cm−2s−1. Asthe luminosity increases from 2.2× 1034 cm−2s−1 to 5× 1034 cm−2s−1 about140 interactions per bunch crossing are expected. The current ATLAS InnerDetector can’t satisfy the performance requirements for these experimentalconditions. Moreover, at the end of the current LHC programme the ATLASdetector will run with components which are 15-20 years old. Therefore, it’snecessary to plan what is called the Phase-II upgrade of the ATLAS detector.

Nowadays, several studies are searching for the best technological solutionfor this upgrade, using silicon pixel detectors. The BCD (Bipolar-CMOS-DMOS) technology can be interesting for this application, but it has not beenstudied within radiation environment. It integrates a low-voltage CMOStechnology (1.8 V) on Double Diffusion (DMOS) structure which can supporthigh voltages (about 50 V). With this technology it’s possible to create a widedepletion region where electron-hole pairs generated by charged particlescan be separated and detected. At the same time it’s possible to designpart of the analyzing circuit inside the sensor area, thus simplifying theinterconnection to the readout electronics and reducing detector materialcompared to traditional technologies. At the end, our aim is the design of apixel detector which is fast and radiation hard. The BCD technology is usedmainly for automotive industries and our knowledge about its performancein radiation environment is extremely limited.

In my thesis I present results from the radiation tests on single MOS tran-sistors and computer simulations on a prototype of pixel detector designed

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in BCD technology. So, one of the task of my thesis was understanding ifthis technology is suitable to be used in radiation environment. The first testis the characterization of MOS transistors integrated on a chip (KC01) bySTMicroelectronics.

The test chip contains both PMOS and NMOS transistors with linear ge-ometry and Enclosed Layout Transistors (ELT) geometry and with differentsizes (in particular, different width-length ratio).

After a first characterization without any radiation, we tested the radia-tion hardness of these transistors after 32 MRad of total dose, using a protonbeam at Laboratori Nazionali del Sud (LNS). In both experiments (beforeand after radiation) I designed and realized the two different test systems,required by the different measurement setup used.

Moreover, we have designed a prototype of pixel detector (KC53A), usingthe same technology. In my thesis I present an analysis of pixel detector cir-cuit and simulations made with Cadence software, using STMicroelectronicslibraries. I performed a small-signal analysis of the circuit, to verify pixelelectronics speed, and a noise analysis.

At the end of these experiments and analysis we have concluded that lin-ear transistors in BCD technology can support hard radiations better thanELTs and the pixel detector design must be optimized and improved. Sincewe had to design the first prototype in a very short time, some parame-ters don’t satisfy the specifications required by ATLAS upgrade. Anyway,the results coming from these experiments and analysis are useful for theimprovements of next pixel detector designs.

2

Chapter 1

Technologies

The inner detector of the ATLAS experiment for the measurement of chargedparticles in the proximity of the pp interaction region contains a pixel detectormade of four barrel layers and three endcap layers. It’s necessary to usea pixel technology When LHC proton beams collides,every 25 ns, multipleproton interactions happen simultaneously: because of the high density ofparticles in proximity to the center where the particles collisions occur. Forthis reason we have to detect particles with the best possible resolution. Pixeldetectors are a good solution because of the pixel size: about 50 µm× 400 µm(50 µm × 250 µm for the innermost barrel layer). Generally a pixel detectoris made of a sensor (a diode reversely biased with an high voltage) whoseoutput is connected with the input of an analog/digital circuit which analyzesthe signal coming from the sensor. High reverse voltage bias is necessary tohave a large depleted zone where electric field can collect the charge generatedby a particle crossing the depleted zone. The larger the depleted zone is, thebigger the collected charge is (i.e., sensor efficiency is maximized).

1.1 Hybrid Pixel Detector

Common CMOS technology is usually used for design and build the readoutelectronics for silicon detectors. But, this technology works at low voltagedrop of bias (about some volts). On the other hand, a standard silicon sensoris produced with high purity, high resistivity silicon, which is biased with ahigh voltage drop (hundreds of volts). To achieve a measurable signal, in theorder of 10000 e−, it must be relatively thick. Since the sensor and readoutelectronics require different technologies, they are built on different wafers.After building separately these two parts, sensor and circuit are connectedin a second step using the “bump-bonding” technology. There are two differ-

3

ent bump-bonding techniques used for ATLAS: electroplated-solder bumping(using PbSn metal alloy) and evaporative-indium bumping. In the first one,the PbSn solder is deposed on the contact pads through electroplating. Inthe second one, the bumps are grown by depositing evaporated indium. Inboth methods, after putting the bumps on the wafers, sensor and circuit aremated and the bump shorts galvanically the sensor’s output to the CMOScircuit’s input. bump-bonding technology has some disadvantages: the mat-ing must be done with high precision, so the bump-bonding process takestoo much time and, at the end, this process is too economically expensive.Anyway, bump-bonding has the advantage to be a mature technology and,according to the experiments, to have a good resistance to hard radiation.

Figure 1.1: Bump-bonding structure (on the left) and foto (on the right).

Replacing the sensor in high purity silicon with a standard CMOS processmay provide an alternative cheap solution. In this case the thickness of thedepleted region where charge is detected is smaller, and the signal is only fewhundreds of electrons. But the CMOS technology allows to integrate in thesensor a first amplification stage, which compensate for the smaller initialsignal.

For connection to the readout chip capacitive coupling using a thin gluelayer is also an alternative option to bump bonding.

1.2 Bipolar-CMOS-DMOS (BCD)

The Bipolar-CMOS-DMOS is one of the High Voltage CMOS technologiesthat can be used to build this new type of sensor. The BCD technologyis the combination of Bipolar, CMOS and DMOS technologies; so it’s pos-sible to build low-voltage devices (CMOS) and high-voltage ones (Bipolarand DMOS) on the same wafer. This technology have some advantages like

4

shorter time of production and the possibility to obtain smaller pixels andso to have better resolution of particles’ track in the space.

Figure 1.2: The inter-rail cross section for a BCD technology.

Using BCD technology, the pixels’ structure is based on growing an epi-taxial silicon layer, on which we can have any analog/digital CMOS circuitcompletely surrounded by N-doped zone which isolate the internal epitaxiallayer from substrate. The voltage drop between N-doped isolation zone andsubstrate is called “External Voltage” and the voltage drop between N-dopedisolation zone and internal epitaxial layer is called “Internal Voltage”. TheFigure 1.2 can help to understand BCD structure in detail. Starting fromthe lowest layer we find a N-doped zone in the wafer called “Buried layer”.After that, an epitaxial layer is made grow on the wafer and two N-dopedisolations called “Niso” and “Nwell” are built on the Buried layer (the sec-ond above the first as show in the picture 1.2). We can observe that thereare PN-junctions between the three N-doped zones (Buried layer, Niso andNwell) and the substrate (lightly P-doped). The isolation is get biasing thesubstrate with the lowest voltage (–50 V) and the N-doped isolation zonewith the highest voltage (1.8 V). In this way, we have reversely biased therelative PN-junction. Most of the depleted zone is in the substrate, becausethe isolation zone has a bigger doping than substrate. At the end, whena charge go through this depleted zone, a lot of e−/h+ couples are createdand we can collect this charge in a very short time (thanks to the high dropvoltage between the isolation and the substrate). The structure illustrated inFigure 1.2 describes how to make an isolation between the internal epitaxial

5

layer and the substrate for any external voltage (until about 50 V). But,when considering the internal voltage, there are two different architecture.When the internal voltage is low (about 10 V), the Nwell isolation is ring,which surrounds laterally the epitaxial layer, and the Niso is a N-doped layerbuilt above the Buried Layer. Buried layer is used to isolate vertically theinternal epitaxial layer and the N-doped rings laterally.

On the other hand, when the internal voltage is bigger (until about 50 V),there is a breakdown risk. So, to avoid this risk we must change the shape ofNiso: a ring instead of a layer. So, isolated N/P-well, built in epitaxial layer,are surrounded by undoped epitaxial layer and haven’t any vertical contactwith Buried Layer any more (see Figure 1.2). Anyway, after choosing one oftwo architecture according voltage conditions, we can have a structure wherethe internal epitaxial layer and the substrate are isolated between them.

Concluding, it’s possible to say that BCD technology allows us to trans-fer part of the front-end circuit on the sensor wafer (as important as theconsideration before) and to reduce sensor dimensions.

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Chapter 2

BCD Test Chip

A pixel detector contains a semiconductor sensor, whose signal is preamplifiedby an analog circuit, and then the preamplified signal converted in digitaldomain [1]. For some delays in libreries delivery, the first design in BCDtechnology consists of the analog part circuit only, which contains a biasresistance used not to lose signal coming from the sensor, an amplifier toamplify sensor signal and a buffer to drive output load capacitance. Afterthe circuit description a small-signal analysis will be done with a simulationof the circuit and a layout image. The following sections are based on IvanPeric paper [1].

2.1 Bias Resistance and Sensor

V DDVDD

ibias Sensor

−50V

Vin

Sensor

BiasResistance

Vin

Figure 2.1: On the left, Schematic diagram of the sensor with bias circuit; on theright, small-signal circuit of sensor with bias resistance.

7

The sensor is a reversely biased diode. In this case the diode anode isthe substrate and the cathode is the N-doped isolation. With a 50 V reversevoltage, the depleted zone is big enough to collect a relatively large numberof e−/h+ pairs, generated by particles. Opposite charges are separated by theelectric field in the depleted zone; in particular, the electrons are collectedat the cathode. This is charge we want to detect and h+ charges are lostbecause the substrate is shorted to −50 V negative supply. If we short thediode anode to the positive supply (VDD), the negative charge is lost too.To avoid this, the positive supply is connected to the anode using a largeresistance. Such a resistance allows us to have a voltage drop large enoughto be detected and makes DC voltage of diode cathode be restored after timelarge enough to let collected charge flow into amplifying circuit. The usualpolysilicon resistive layer isn’t suitable because it would occupy a very largearea and, moreover, it would lead to a large parasitic capacitance [1]. Thechosen solution is a PMOS transistor, whose source is shorted to VDD andwhose N-well bulk and drain are shorted to N-well of N-doped isolation. Thegate voltage is generated by a PMOS diode placed outside the pixel. Usingthese connections, the PMOS source (P+ region) and the bulk (N-well) arethe terminals of a directly biased diode, which works as a bias resistor. Thisdevice conducts a small leakage current also, but this current is small andit can be neglected [1]. PMOS transistor dimensions must be such that biasresistance is as big as possible. In this design the width is 500 nm and thelength is 10 µm. As described before, the sensor is a reversely biased diode. Ina small-signal analysis this can be approximated with a capacitor. For circuitdesign purpose, it’s necessary to know the capacitance value of the sensor.The size of the sensor is 50 µm × 250 µm. Considering optical shrinking bya factor of 0.92 during mask fabrication, in the layout the dimensions are271, 73 µm × 54, 34 µm. A simulation has been done to obtain the sensorcapacitance. A diode sensor, whose dimensions are 271, 73 µm × 54, 34 µm,has been biased at −50 V and a small-signal current was injected. Using theequation

I = iωCV (2.1)

and knowing small-signal current value, we can obtain C value, observingthe V/ω plot. We have calculated C ≈ 500 fF.

2.2 Amplifier

As mentioned before, the charge collected in the sensor flows into the ampli-fier. The sensor cathode is connected to the amplifier input with a couplingcapacitance because amplifier input DC voltage is different than the N-well

8

Cf

Vamp

V DDVDD

Vin

Vbias

VNcasc

VPcasc

NWELL

Figure 2.2: Folded-Cascode Single-Ended Amplifier

bias potential. So, DC signals are stopped and AC signals are fed to theamplifier.

Our design uses a folded-cascode single-ended amplifier with PMOS inputdevice. A folded-cascode amplifier instead of a telescopic has some advan-tages and disadvantages. In fact, folded-cascode amplifier dissipates morepower (it use more current) than telescopic one, it has voltage gain two orthree times smaller, lower pole frequencies and higher noise than the other;however, a folded-cascode amplifier has less bias voltages to be set carefully(in particular, input DC voltage can be chosen in a large voltage range); so,output can be also shorted to the input [4]. The input device is a PMOStransistor. Although the mobility µ in NMOS device is larger than in PMOSones, a PMOS input device is better than NMOS, because in a folded-cascodeamplifier most of the noise comes from input stage and, considering both ther-mal and 1/f (flicker) noise, NMOS transistors exhibit bigger 1/f noise thanPMOS ones [4]. Moreover, according to the simulations, PMOS transistorsexhibit smaller channel length modulation and so a larger resistance for smallsignal. In the PMOS input configuration, a PMOS transistor is used as load

9

resistance. As amplifier gain G can be calculated by equation

G =Rout

Rin

(2.2)

where Rout is approximately equal to the resistance of the PMOS load. Afolded-cascode amplifier with a PMOS load as load has a gain larger than theNMOS one. Analyzing our amplifier, we can observe that in PMOS devicesthe P+ diffusions (source and drain) are capacitively coupled with the N-welland this coupling can generate unwanted crosstalk. The most problematicP+ diffusion is the drain of the output PMOS transistor, because it actsas a parasitic capacitive feedback and this remains charged after each inputsignal pulse [1]. A solution is discussed in Sect. 2.3. The effects of the othersP+ diffusions are negligible, because the source nodes are shorted to VDDsupply and the input device’s drain is kept at a nearly constant potential bythe cascode NMOS transistor. According to (2.2), to have bigger gain, it’spossible to increase Rout or to decrease Rin, which is given by

Rin =1

gmin

=Vgs − VTH

2ID(2.3)

ID must be large enough to achieve a small value of Rin. In our design, thecurrent flowing through the cascode branch is 2 µA, while the current flowingthrough input PMOS transistor is 8 µA. The increasing of the transistorwidth-length ration (W/L) is a possible solution to increase input PMOSdrain current. In the original design 10/0.6 ratio has been chosen, while alarger one has been used. In particular, 10 PMOS transistors in parallel havebeen used, each one with W = 500 nm and L = 180 nm. We have used 10transistors instead of one with a width 10 times larger to reduce mismatchon input transistor length channel. The PMOS cascode width-length ratiois 280 nm/360 nm, the NMOS cascode ratio is 280 nm/800 nm and the biasNMOS transistor size is 560 nm/360 nm. Gate potentials of every transistorsare set to have the drain current described above and to keep all transistorsin saturation conditions.

2.3 Resistive Feedback

In the previous section a parasitic capacitive feedback has been described andit can be a source of crosstalk. The ideal solution is a connection betweenoutput amplifier and input by a current generator, which discharges thefeedback capacitance. After an output voltage increase this generator willrestore the DC voltage. In the real circuit it’s possible to use a transistor

10

V DD

iDrain

VampV−

Vbias M1

M2

M3

V−

Rf

Vamp

Figure 2.3: Schematic diagram of feedback resistance (left); small-signal circuit offeedback resistance (right).

with a constant gate-source voltage. This solution allows us to bias theinput node at the correct DC value: without signal. The input DC voltageis nearly equal to the output voltage. So, when the output voltage increases,the transistor is in saturation and a nearly constant current flows throughthe transistor and the capacitive feedback is discharged, until output andinput voltages are equal within the thermal voltage (VT ∼ 26 mV). Thebias circuit generates a constant gate-source voltage used to bias the feedbacktransistor. The DC current of bias circuit flows into the amplifier’s outputnode and into cascode NMOS transistor. Nevertheless, this current ( iDrainin Figure 2.3) is smaller than the current coming from the cascode PMOSinto the folded-cascode amplifier. So the current coming from the bias circuitof the feedback transistor is negligible. The width-length ratio for all NMOStransistors is 500 nm/360 nm and for the PMOS ones it is 560 nm/360 nm.

2.4 Buffer and ESD PAD

After the amplifier, we have designed an output buffer, which is necessaryto drive the output pad capacitance. In the original design [1] the bufferoutput is connected to a comparator input. In our design the same output isconnected to a pad. In this way, the analog output signal coming from buffercan comunicate with the external board. In the first case the buffer mustdrive a load capacitance of some femtofarad; in the second case the buffermust drive 1 pF load capacitance. Every circuit has an output resistance andcapacitance which can be considered as RC circuit (low-pass filter). Addingload capacitor makes time constant τ to increase. But, the larger τ is, thesmaller the passing frequencies range is. The buffer is needed to avoid last

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signal information at high frequencies. The buffer is a source follower with aNMOS transistor as current source. The input device of this circuit is alsoa NMOS transistor, whose source is the output node and is shorted to thedrain of the other NMOS.

Vbias

Vamp

V DD

VBUFRPOLY

V DD

CPAD

Vout

Figure 2.4: Schematic diagram of the buffer and the ESD pad

The output pad device is required to connect the integrated circuit withthe external board. A pad is a rectangular metallic surface above a siliconsubstrate, where capacitive behavior comes from. To protect the internalnodes of the integrated circuit, against unexpected voltage peaks we haveconnected the pad node to the voltage supplies VDD (1.8 V) and GND (0 V)with reversely bias diodes. Indeed, electrostatic discharges can damage thechip and keeping output voltage in range 0 V−1.8 V. A series resistor witha small value is used to separate the output voltage to the internal node.Regarding transistors dimensions, NMOS current source has a width-lengthratio of 560 nm/360 nm. Instead, NMOS input device consists of 10 NMOStransistors in parallel with same dimensions of current source. Dimensionsbigness of NMOS input device will be justified in analysis chapter by makingsmall-signal output be more similar to input one as possible.

2.5 Current Injection

To test the main circuit described in the previous section in laboratory with-out any radiation source we need an input signal.

The device used for this task is a NMOS transistor (M1) driven by a sec-ond NMOS (M2), whose gate is connected to its drain and to the gate of theother one: Current Mirror configuration. The signal coming from the sensor

12

M1

i

M2

imirror

Vin

Figure 2.5: Schematic diagram of current generator

is a current pulse whose pulsewidth is nearly 10 ns. If the minimum collec-tion of charges in this period of time is nearly 600 e−, the driven transistorhas to generate a 10 nA current. It’s impossible to generate such a smallcurrent. A possible solution is to inject a higher current and to reduce theratio of mirrored and injected current. So, M2 width channel has to largerthan M1. In our design M2 width channel is 103 times larger than M1; somirrored current is 103 times smaller than injected one. So, if the mirroredcurrent is 10 nA, the injected one is nearly 1 µA, which could be generatedby a current generator. So, M2 is a NMOS transistor whose width is 300 nmand whose length is 400 nm. Instead, M1 length is the same of M2, but itswidth is 103 times larger. In particular, M1 is design with 103 transistors inparallel with the size equal to M2 (W (M1) = 103 W (M2)).

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14

Chapter 3

Frequency and Noise Analysis

The chapter presents a theoretical analysis of the frequency response and ofthe input noise of the circuit, and a comparison with simulation results. It’sworth pointing out that analysis can not agree totally with simulations, sincefor very high frequencies secondary effects dominate, which we neglect in ouranalysis. The simulations are done by Cadence Spectre using STMicroelec-tronics libraries.

3.1 MOM Capacitor

Figure 3.1: MOM capacitor picture.

The coupling capacitor is a MOM (Metal-Oxide-Metal) built on a P-well.This type of capacitor is made of two metal strips (the plates of capacitor)separated by a narrow oxide layer. The P-well, which is equivalent to the

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substrate in Figure 3.1, is biased to ground (0 V) for the reversely biasedPN-junction with N-doped isolation zone. This type of capacitor containsother two parasitic capacitors (see Figure 3.2). In fact, each plate is coupledalso to the P-well, giving one parasitic capacitor for each plate. Because ofthis, part of the current signal coming from the sensor is lost.

Vin

CMOM

Vout

CC

Cp Cp

Vin Vout

Figure 3.2: Schematic diagram of a MOM capacitor (left); small-signal circuit ofMOM capacitor (right).

For this design we have chosen to maximize the power (and energy) trans-fer. Using the maximum power transfer theorem, we obtain that the outputimpedance of sensor must be equal to input impedance of the amplifying cir-cuit; in particular, MOM capacitance (not considering the parasitics) mustbe equal to sensor capacitance (∼ 500 fF).

3.2 Amplifier

rp0gmin

Vinrn1 gm1

Vx

gm2 rn2

gm3 rp3

Cload

Vamp

Figure 3.3: Small-signal amplifier circuit output load capacitance

16

As described in the previous chapter, we use a folded-cascode amplifierwith an input PMOS transistor (Figure 2.2) In this type of amplifiers asmall-signal current coming from the input PMOS transistor is folded on theother branch and the signal is converted from current to voltage by meanof the output resistance. Actually, DC current generator isn’t ideal due tothe channel length modulation. In particular, a part of the signal currentgoes through the NMOS used as a DC current generator. The channel lengthmodulation occurs in every transistors of our circuit and it’s fairly relevantfor the results. Another second order effect, the body effect, can be neglectedin our analysis. The small-signal circuit is in Figure 3.3 is described by thefollowing equations.

I = −VinginIrp0 = Vx

rp0

Irn1 = Vxrn1

Irn2 = Vx−Voutrn2

Igm2 = gmnVxIrp3 = Vout

rp3

ICload= iωCloadVout

I = Irp0 + Irn1 + Igm2 + Irn2Igm2 + Irn2 = Irp3 + ICload

(3.1)

Signs in the equations are based on current directions shown in Figure3.3. By sostituting current values, we obtain:{

−Vingin = Vxrp0

+ Vxrn1

+ Voutrp3

+ iωCloadVoutgmnVx + Vx−Vout

rn2= Vout

rp3+ iωCloadVout

(3.2) −Vingin =(

1rp0

+ 1rn1

)Vx +

(1rp3

+ iωCload

)Vout(

gmn + 1rn2

)Vx =

(1rp3

+ 1rn2

+ iωCload

)Vout

−Vingin =(

1rp0

+ 1rn1

)Vx +

(1rp3

+ iωCload

)Vout

Vx =

(1

rp3+ 1

rn2+iωCload

)gmn+

1rn2

Vout

−Vingin =

(1

rp0+

1

rn1

) 1rp3

+ 1rn2

+ iωCload

gmn + 1rn2

Vout +

(1

rp3+ iωCload

)Vout

VoutVin

= − gin(1rp0

+ 1rn1

) 1rp3

+ 1rn2

+iωCload

gmn+1

rn2

+(

1rp3

+ iωCload

)17

VoutVin

= − gin(1

rp0+ 1

rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

+ iωCload

(1 +

1rp0

+ 1rn1

gmn+1

rn2

) (3.3)

3.2.1 Frequency Response Module

|H (ω)| =

∣∣∣∣VoutVin

∣∣∣∣=

gin√√√√((1

rp0+ 1

rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

)2

+ ω2C2load

(1 +

1rp0

+ 1rn1

gmn+1

rn2

)2

(3.4)

From (3.4), we can observe two different behaviors of frequency response.At low frequencies, all the terms containing ω are negligible:

|H (ω)| = gin(1

rp0+ 1

rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

(3.5)

At high frequencies the dominant terms are the part containing ω:

|H (ω)| = gin

ωCload

(1 +

1rp0

+ 1rn1

gmn+1

rn2

) (3.6)

It’s fair to say that we have the first (second) behavior, when the fre-quency is smaller (larger) than a critical frequency ωc (cut-off frequency),corresponding to a pole of this circuit. ωc can be calculated by matching thefrequency response at low frequencies with the frequency response for highfrequencies:

gin(1

rp0+ 1

rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

=gin

ωcCload

(1 +

1rp0

+ 1rn1

gmn+1

rn2

) (3.7)

(1rp0

+ 1rn1

)(1rp3

+ 1rn2

)gmn + 1

rn2

+1

rp3= ωcCload

(1 +

1rp0

+ 1rn1

gmn + 1rn2

)

18

ωc =

(1rp0

+ 1rn1

)(1rp3

+ 1rn2

)rp3 + gmn + 1

rn2

Cloadrp3

(gmn + 1

rn2+ 1

rp0+ 1

rn1

) (3.8)

3.2.2 Frequency Response Phase

For a phase analysis we start from the amplifier’s frequency response (3.3)and we separate real and imaginary parts.

H (ω) =

−

(1

rp0+ 1

rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

+ iωCload

(1 +

1rp0

+ 1rn1

gmn+1

rn2

)((

1rp0

+ 1rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

)2

+ ω2C2load

(1 +

1rp0

+ 1rn1

gmn+1

rn2

)2(3.9)

As the phase tangent is equal to the ratio between imaginary and realpart of frequency response, we obtain for ω << ωc

tan(φ) =

ωCload

(1 +

1rp0

+ 1rn1

gmn+1

rn2

)−

[(1

rp0+ 1

rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

] ≈ −180◦ (3.10)

because ω is very small compared to the rest of the ratio and the real partis negative.

At frequencies higher than the pole ωc

tan(φ) =

ωCload

(1 +

1rp0

+ 1rn1

gmn+1

rn2

)−

[(1

rp0+ 1

rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

] (3.11)

φ = −180◦ − tan−1

ωCload

(1 +

1rp0

+ 1rn1

gmn+1

rn2

)(

1rp0

+ 1rn1

)(1

rp3+ 1

rn2

)gmn+

1rn2

+ 1rp3

(3.12)

−180◦ < φ < 270◦

19

Vamp_Vi n_AMP 10: 43: 16 Tue Mar 3 2015

Vi n/ I : Vamp/ Vi n: Vamp/ I : phase( Vi n/ I ) : phase( Vamp/ Vi n) : phase( Vamp/ I )

Vamp/Vin

Mag (

)

10-1

100

101

102

103

phase(Vamp/Vin)

Ph

ase

(d

eg)

-375.0

-350.0

-325.0

-300.0

-275.0

-250.0

-225.0

-200.0

-175.0

Name

freq (Hz)10

010

110

210

310

410

510

610

710

810

9

Pr i nt ed on

by hvcmos

Page 1 of 1

Figure 3.4: Small-signal output module(above); small-signal output phase (below)

20

3.3 Amplifying Circuit

Before starting the analysis of this part of the circuit, let’s recall (3.3), whichcan be rewritten as:

VampV−

= −K(ω) =−K

1 + iωτamp(3.13)

I CD

RB

Cp1

VinCC

Cp2

−K(ω)

V−

Rf

Vamp

Cf

Figure 3.5: Small-signal equivalent circuit until amplifier’s output

Considering Fig. 2.2, it’s possible to neglect current passing through theparasitic capacitor Cp2 , because V− can be considered as the virtual ground ofan amplifier with negative feedback. Moreover, the current passing throughCf capacitor can be negligible; in fact, Cf , CD, Cp2 and Cc, which have aterminal shorted to Vin node, are in parallel. Cf is nearly 1 fF; instead,CD, Cp2 and Cc are nearly hundreds of femtofarad. So, small-signal currentpassing through CD or Cp2 or Cc are hundreds times bigger than one passingthrough Cf : we can consider ICf

negligible. The circuit is simplified as shownin Fig. 3.6.

To simplify the analysis, we divide this circuit into two smaller ones: thefirst which contains the reversely biased diode sensor and MOM capacitor(capacitor Cc and parasitic capacitor CP ); the second which contains MOMcapacitor (only Cc capacitor), amplifier and feedback resistance. These cir-cuits will be analyzed separately and then the frequency responses will becombined to obtain the frequency response of the circuit in Figure 3.6.

21

I CD

RB

Cp1

VinCC

−K(ω)

V−

Rf

Vamp

Figure 3.6: Small-signal circuit until amplifier’s output with Cp2 and Cf neglected

3.3.1 Sensor + MOM AC coupling capacitor

In this step, we analyze the part of the circuit which contains the reversely bi-ased diode sensor and MOM capacitor Cc and parasitic capacitor CP (Figure3.7).

I CD

RB

Cp1

VinCC V−

Figure 3.7: Small-signal circuit with sensor and MOM capacitor

Currents in Figure 3.7 are described by the following equations.

ICc = iωCc(Vin − V−)ID = iωCDVinICp = iωCpVinIRB

= VinRB

I = ID + IRB+ ICp + ICc

(3.14)

For the negative feedback circuit, V− is at virtual ground (V− ' 0).

22

ICc ' iωCcVinID = iωCDVinICp = iωCpVinIRB

= VinRB

I = ID + IRB+ ICp + ICc

(3.15)

Solving the set of equations, we obtain:

I = iωCDVin + iωCpVin + iωCcVin +VinRB

I = Vin

[iω(CD + Cp + Cc) +

1

RB

]VinI

=RB

1 + iω(CD + Cp + Cc)RB

(3.16)

Equation (3.16) relates the sensor (I) to the voltage at the amplifier input.

3.3.2 MOM + Amplifier + Feedback

Now, we analyze the part of the circuit which contains the MOM capaci-tor without parasitic capacitors, the amplifier and the feedback resistance(Figure 3.9).

Figure 3.9 is described by the following equations.Vamp = −K(ω)V−ICc = iωCc(V− − Vin)

IRf= (Vamp−V−)

Rf

ICc = IRf

(3.17)

Solving the equations, we obtain:ICc = iωCc

(−Vamp

K(ω)− Vin

)IRf

= 1Rf

(Vamp + Vamp

K(ω)

)ICc = IRf

(3.18)

iωCc

(− VampK(ω)

− Vin)

=

(1 +

1

K(ω)

)VampRf

−iωCcRf

(VampK(ω)

+ Vin

)=

(1 +

1

K(ω)

)Vamp

23

Vi n_I 17: 27: 08 Fr i Mar 13 2015

Vi n/ I : Phase( Vi n/ I ) : Vamp/ I : Phase( Vamp/ I ) : Vout / I : Phase( Vout / I )

Vin/I

Mag (

)

102

103

104

105

106

Phase(Vin/I)

Ph

ase

(d

eg)

-100

-80.0

-60.0

-40.0

-20.0

0.0

20.0

Name

freq (Hz)10

010

110

210

310

410

510

610

710

810

9

Pr i nt ed on

by hvcmos

Page 1 of 1

Figure 3.8: Small-signal output module (above); small-signal output phase (below)

24

Vin

CC−K(ω)

V−

Rf

Vamp

Figure 3.9: Small-signal circuit with MOM capacitor (only Cc capacitance), am-plifier and feedback resistance

−iωCcRfVin =

[1 +

1

K(ω)(1 + iωCcRf )

]Vamp

VampVin

= − iωCcRf

1 + 1K(ω)

(1 + iωCcRf )(3.19)

3.3.3 Sensor + MOM AC-coupling capacitor + Am-plifier + Feedback

Partial results coming from the analysis in the previous subsections are sum-marized in the equation set:{ Vamp

Vin= − iωCcRf

1+ 1K(ω)(1+iωCcRf)

VinI

= RB

1+iω(CD+Cp+Cc)RB

(3.20)

{Vamp = − iωCcRf

1+ 1K(ω)(1+iωCcRf)

Vin

Vin = RB

1+iω(CD+Cp+Cc)RBI

Combining these equations we can find the frequency response Vamp

Iof

the circuit in Figure 3.6.

VampI

= − iωCcRf

1 + 1K(ω)

(1 + iωCcRf )

RB

1 + iω(CD + Cp + Cc)RB

(3.21)

3.3.4 Frequency Response Module

As one can observe from (3.21), the frequency response has are 3 poles:one coming from the amplifier ( 1

τamp), one coming from the sensor stage

25

Vamp_Vi n 16:08:58 Fri Mar 13 2015

(VF("/ I 12/ net03") / VF("/ net014"))

Vamp/Vin

Mag()

10-1

100

101

102

103

Phase(Vamp/Vin)

Phase

(deg)

-400.0

-350.0

-300.0

-250.0

-200.0

-150.0

-100.0

-50.0

Name

freq (Hz)10

010

110

210

310

410

510

610

710

810

9

Figure 3.10: Small-signal output module (above); small-signal output phase (be-low)

26

( 1(CD+CP+Cc)RB

) and one coming from AC-coupling Capacitor Cc ( K+1CcRf

). At

first, we can’t know the order of these poles on frequency axis. However, it’spossible to extrapolate their order and approximately their own position onthe axis from the simulations of two part of the circuit before unifying. Usingthis method we can assert that these poles are ordered according to (3.22).

1

(CD + CP + Cc)RB

<K + 1

CcRf

<1

τamp(3.22)

Now we can analyze frequency response in every frequency ranges, usingsuitable approximations in every cases.

For ω < 1(CD+Cp+Cc)RB

VampI

= − iωCcRf

1 + 1K(ω)

RB

∣∣∣∣VampI∣∣∣∣ =

ωCcRf

1 + 1K(ω)

RB (3.23)

For 1(CD+Cp+Cc)RB

< ω < K+1CcRf

VampI

= − iωCcRf

1 + 1K(ω)

RB

iω(CD + Cp + Cc)RB∣∣∣∣VampI∣∣∣∣ =

CcRf(1 + 1

K(ω)

)(CD + Cp + Cc)

(3.24)

For K+1CcRf

< ω < 1τamp

VampI

= −iωCcRfK(ω)

iωCcRf

RB

iω(CD + Cp + Cc)RB∣∣∣∣VampI∣∣∣∣ =

K(ω)

ω(CD + Cp + Cc)(3.25)

For ω > 1τamp

VampI

= −iωCcRf

iωCcRf

K

iωτamp

RB

iω(CD + Cp + Cc)RB∣∣∣∣VampI∣∣∣∣ =

K

ω2τamp(CD + Cp + Cc)(3.26)

27

3.3.5 Frequency Response Phase

For ω < 1(CD+Cp+Cc)RB

VampI

= − iωCcRf

1 + 1K(ω)

RB

φ

(VampI

)= −90◦ (3.27)

At frequencies higher than the pole 1(CD+Cp+Cc)RB

VampI

= − iωCcRf

1 + 1K(ω)

RB

1 + iω(CD + Cp + Cc)RB

VampI

=ωCcRf

1 + 1K(ω)

RB [−i− ω(CD + Cp + Cc)RB]

1 + ω2(CD + Cp + Cc)2R2B

φ

(VampI

)= −180◦ + tan−1

[1

ω(CD + Cp + Cc)RB

](3.28)

−90◦ < φ

(VampI

)< −180◦ (3.29)

At frequencies higher than the pole K+1CcRf

VampI

= − iωCcRf

1 + 1K(ω)

(1 + iωCcRf )

RB

iω(CD + Cp + Cc)RB

VampI

= − CcRf(1 + 1

K(ω)

)+ iω

CcRf

K(ω)

RB

(CD + Cp + Cc)RB

VampI

= −CcRf

[(1 + 1

K(ω)

)− iωCcRf

K(ω)

](

1 + 1K(ω)

)2+ ω2

(CcRf

K(ω)

)2 RB

(CD + Cp + Cc)RB

φ

(VampI

)= −180◦ − tan−1

[ωCcRf

K(ω)

1 + 1K(ω)

]

φ

(VampI

)= −180◦ − tan−1

[ωCcRf

K(ω) + 1

](3.30)

−180◦ < φ

(VampI

)< −270◦ (3.31)

28

At frequencies higher than the pole 1τamp

VampI

= − iωCcRf

(iωCcRf )

K

1 + iωτamp

RB

iω(CD + Cp + Cc)RB

VampI

=−K

i− ωτamp1

ω(CD + Cp + Cc)

VampI

=K (i+ ωτamp)

1 + ω2τ 2amp

1

ω(CD + Cp + Cc)

φ

(VampI

)= −360◦ + tan−1

[1

ωτamp

](3.32)

−270◦ < φ

(VampI

)< −360◦ (3.33)

3.3.6 Simulation

According to previous analysis, we should get Vamp

Igrowing with the fre-

quency (+20 dB/dec), till the first pole. Between first and second poleit is constant in frequency. Between second and third pole, Vamp

Idecreases

(−20 dB/dec) and after the third pole it decreases more quickly (−40 dB/dec).Observing simulation results in Figure 3.11 (above), for frequencies higher

than 103 Hz the behavior expected by analysis is nearly right. On the otherhand, at lower frequencies than 103 Hz is absolutely wrong. In fact, wehave neglected the body effect. For high frequencies Cc capacitor conductssmall-signal current which arrives at the gate of input PMOS transistor.As gm transconductance is bigger than gb body effect, for high frequenciesbody effect neglecting is a good approximation. But, for small frequencies Cccapacitor conduct a small-signal current, which could be negligible. However,signal current coming from the sensor bypasses Cc capacitor, arriving at inputPMOS body and body effect prevails. Regarding the phase, it’s possible toobserve from Figure 3.11 (below) a disagreement for frequencies smaller than103 Hz. This is still for the body effect. As gb has the same signal of gmtransconductance, the amplifier phase is −180◦. The higher the frequency is,the less negligible Cc current is. Body effect is prevailed by transconductanceand phase changes from −180◦ to −90◦. When frequency is higher than103 Hz, phase is still predicted by the analysis. More precisely in 3.11 (below)the phase doesn’t return to −90◦, but it stops nearly at −100◦ and then itstarts to decrease. This is because the first two poles are close each other.So, before phase arrives at −90◦, second pole makes the phase to decrease.Moreover, for very high frequencies (nearly 1 GHz) the phase continues to

29

Vamp_I 17: 31: 45 Fr i Mar 13 2015

( VF( " / I 12/ net 03" ) / I F( " / I 12/ NWELL" ) )

Vamp/I

Mag (

)

102

103

104

105

106

107

108

Phase(Vamp/I)

Ph

ase

(d

eg)

-450.0

-400.0

-350.0

-300.0

-250.0

-200.0

-150.0

-100.0

-50.0

Name

freq (Hz)10

010

110

210

310

410

510

610

710

810

9

Pr i nt ed on

by hvcmos

Page 1 of 1

Figure 3.11: Small-signal output module (above); small-signal output phase (be-low)

30

decrease (below −360◦). This shows that there is an other pole (probablycoming from the amplifier) which was neglected in our calculations.

3.4 Buffer and ESD pad

rn2gmn

Vy

Vamp

gmin rn1

CBUF

RP

CP

Vout

Figure 3.12: Small-signal circuit of buffer and ESD pad

After having analyzed amplifying circuit, we can start to analyze the lastpart of all the circuit: buffer and ESD pad. Following analysis comes fromFigure 3.12. It’s necessary to put in evidence that CBUF is the buffer outputcapacitance, CP is pad capacitance and RP is the polysilicon resistor. Thereversely biased diodes, used as protection against ESD, are neglected.

I = gmin(Vamp − Vy)

Irn1= Vy

rn1

Irn2= Vy

rn2

ICBUF= iωCBUFVy

IRP= Vy−Vout

RP

ICP= iωCPVout

I = Irn1+ Irn2

+ ICBUF+ IRP

IRP= ICP

(3.34)

IRPOLY= ICPAD

=iωCP

1 + iωCPRP

Vy

Vout =1

1 + iωCPRP

Vy

31

gmin(Vamp − Vy) =

Vyrn1

+Vyrn2

+ iωCBUFVy +iωCP

1 + iωCPRP

Vy (3.35)

{Vout = 1

1+iωCPRPVy

gminVamp =

[(gmin

+ 1rn1

+ 1rn2

) + iωCBUF + iωCP

1+iωCPRP

]Vy

(3.36)

gminVamp =

[(gmin

+1

rn1

+1

rn2

) + iωCBUF +iωCP

1 + iωCPRP

](1+iωCPRP )Vout

(3.37)For simplicity we can write the following equality:

1

RBUF

= gmin+

1

rn1

+1

rn2

and RBUF is buffer output resistor.

gminVamp =

[1

RBUF

+ iωCBUF +iωCP

1 + iωCPRP

](1 + iωCPRP )Vout (3.38)

gminRBUFVamp =

[1 + iωCBUFRBUF +

iωCPRBUF

1 + iωCPRP

](1 + iωCPRP )Vout

(3.39)

VoutVamp

=gmin

RBUF

(1 + iωCBUFRBUF ) (1 + iωCPRP ) + iωCPRBUF

(3.40)

3.4.1 Frequency Response Module

Now we have the same problem we had the prior section: there are more polesthan one and parameters like buffer output impedance (CBUF and RBUF )aren’t known. As before, it’s possible to extrapolate the poles’ positions onfrequency’s axis. In this case we have found the following behavior.

1 <<1

CPRBUF

<<1

CPRP

∼ 1

CBUFRBUF

(3.41)

For ω < 1CPRBUF

VoutVamp

= gminRBUF

32

∣∣∣∣ VoutVamp

∣∣∣∣ = gminRBUF (3.42)

For 1CPRBUF

< ω < 1CPRP

VoutVamp

=gmin

RBUF

1 + iωCPRBUF∣∣∣∣ VoutVamp

∣∣∣∣ =gmin

RBUF√1 + ω2(CPRBUF )2

(3.43)

For ω > 1CPRP

VoutVamp

=gmin

−ω2CBUFCPRP + iωCP∣∣∣∣ VoutVamp

∣∣∣∣ =gmin√

ω4(CBUFCPRP )2 + ω2C2P

(3.44)

3.4.2 Frequency Response Phase

Before the pole 1CPRBUF

VoutVamp

= gminRBUF

φ

(VoutVamp

)= 0 (3.45)

At frequencies higher than the pole 1CPRBUF

VoutVamp

=gmin

RBUF

1 + iωCPRBUF

VoutVamp

=gmin

RBUF√1 + ω2(CPRBUF )2

(1− iωCPRBUF )

φ

(VoutVamp

)= − tan−1(ωCPRBUF ) (3.46)

0◦ < φ

(VoutVamp

)< −90◦ (3.47)

At frequencies higher than the pole 1CPRP

33

VoutVamp

=gmin

−ω2CBUFCPRP + iωCP

VoutVamp

=gmin√

ω4(CBUFCPRP )2 + ω2C2P

(−ω2CBUFCPRP + iωCP

)φ

(VoutVamp

)= −180◦ + tan−1

(1

ωCBUFRP

)(3.48)

−90◦ < φ

(VoutVamp

)< −180◦ (3.49)

3.4.3 Simulation

The simulation in Figure 3.13 shows that for frequencies lower than 100 MHzthe analysis is right. But, for higher frequencies there is some problems. Infact, frequency response module should have decreased and the phase stopsat −90◦. Instead, frequency response module stops and the phase increases,returning at 0◦. This means that in frequency response equation there isa zero, which was neglected in our analysis.. In fact, between Vamp and Vythere is a capacitative effect which lead to a capacitative voltage divider.

3.5 Current Injection

Small-signal analysis of current injection circuit in frequency domain isn’t soimportant to be described. moreover, the analysis of this circuit in time isimportant. Starting from the situation when both transistors are switchedoff, we inject a current from a external current generator into the transistorM1. At the beginning, the M1 gate voltage (and so drain voltage becausethey are shorted together) is at ground.

Considering a rectangular current injection in time, the gate voltage startto rise linearly; in fact, all the MOSFET are capacitor. Moreover, M1 has agate area larger by a factor of 100 than M2, so because of M1 capacitance weneed a large time to charge M1 capacitance and to rise gate potential abovethreshold voltage. When the gate voltage goes by the threshold voltage, bothtransistors will be switched on and they will begin to conduct current. gatevoltage continues to grow until input current will be equal to current drivenby gate-source voltage. When input current is stopped, gate voltage remainshigh and so M1 (and so M2) continues to conduct; in particular, the intrinsicM1 capacitance starts to be discharged, until gate voltage arrives below the

34

Vout_Vamp 16:09:12 Fri Mar 13 2015

Vout_Vamp

Vout_Vamp

Mag()

10-3

10-2

10-1

100

Phase(Vout_Vamp)

Phase

(deg)

-100

-80.0

-60.0

-40.0

-20.0

0.0

20.0

Name

freq (Hz)10

010

110

210

310

410

510

610

710

810

9

Figure 3.13: Small-signal output module (above); small-signal output phase (be-low)

35

Vout _I 17: 31: 34 Fr i Mar 13 2015

( VF( " / Out " ) / I F( " / I 12/ NWELL" ) )

Vout/I

Mag (

)

10-1

100

101

102

103

104

105

106

107

108

Phase(Vout/I)

Ph

ase

(d

eg)

-500.0

-450.0

-400.0

-350.0

-300.0

-250.0

-200.0

-150.0

-100.0

-50.0

Name Vis

freq (Hz)10

010

110

210

310

410

510

610

710

810

9

Pr i nt ed on

by hvcmos

Page 1 of 1

Figure 3.14: Small-signal output module (above); small-signal output phase (be-low)

36

iS CD

RB

Vin

M1

i

M2 CD

RB

imirrorVin

Figure 3.15: Schematic diagram of ideal current generator (left); schematic dia-gram of real current generator (right).

threshold one. After that, theoretically drain current of M1 transistor isstopped because M1 is switched off. Actually, there are some sub-thresholdcurrent which can discharge intrinsic capacitance of M1. During this phase,M2 has a drain current similar to M1. As we can see in Fig. 3.16, M2drain current is not similar to the square input signal because of its shortduration: it’s more similar to a triangle one. This is not so bad. A real signalcoming from a silicon sensor has a shape similar to a triangle; in fact, thefirst signal coming out the sensor is drift current (charges coming from h+/e−couples generated in the depleted zone and collected by electric field) andthen there is a second signal which is diffusion current. This last one comesfrom h+/e− couples generated outside depleted zone. These charges movealong a distance equal to its mean free path before their recombination. Ifthese charges go into depleted zone before of the recombination, they will becollected, going out of the sensor creating a signal. The combination of thesetwo effects produces an output signal with a shape similar to a triangle.

3.6 Noise Analysis

Until now we have analyzed the signal of the circuit only. Now it’s importantto analyze also the noise of this circuit to understand if the circuit has a goodsignal/noise ratio or if the noise exceed the signal. We have reported thenoise analysis of the two main noise contributions: one is the thermal noisecoming from bias bias resistance (parallel noise) and the other is the thermalnoise coming from input PMOS transistor of amplifier (series noise). In thefollowing, the noise is analyzed considering sensor and amplifier stages andneglected the buffer.

37

Wi ndow 18 14: 55: 53 Tue Mar 3 2015

Tr ansi ent Anal ysi s ` t r an' : t i me = ( 0 s - > 10 us)

Input Current

I (u

A)

-.5

0.0

.5

1.0

1.5

2.0

2.5

3.0

3.5

Mirrored Current

I (n

A)

-10.0

0.0

10.0

20.0

30.0

40.0

50.0

Name

time (ns)

0.0 25.0 50.0 75.0 100.0

Pr i nt ed on

by hvcmos

Page 1 of 1

Figure 3.16: Input signal current (above); M2 drain current (below)

38

V_t 16:04:16 Fri Mar 13 2015

Transi ent Anal ysi s `tran' : t i me = (0 s ->10 us)

Vin

V(V

)

1.7997

1.79975

1.7998

1.79985

1.7999

1.79995

1.8

1.80005

Vamp

V(V

)

1.34

1.345

1.35

1.355

1.36

1.365

1.37

1.375

1.38

Vout

V(m

V)

842.5

845.0

847.5

850.0

852.5

855.0

857.5

860.0

862.5

Name

time (us)

0.0 .5 1.0 1.5 2.0 2.5 3.0

Figure 3.17: Vin(t) (above); Vamp(t) (center); Vout(t) (below)

39

3.6.1 Parallel Noise

b CD

RB

Cp1

VinCC

−K(ω)

V−

Rf

Vamp

Figure 3.18: Small-signal circuit until amplifier’s output with parallel noise, whereb = 2kT

RB

The parallel noise analysis is similar to signal analysis (you can see itfrom Figure 3.18).

3.6.2 Series Noise

CD

RB

Cp1

VinCC

−

+

V−

Rf

Vamp

a

Figure 3.19: Small-signal circuit until amplifier’s output with series noise movedfrom negative input to an supposed positive input.

The series noise is a voltage at the input PMOS transistor of the amplifier,which is the negative input of the amplifier (a = 2

32KTgm

). To simplify thisanalysis let’s replace the amplifier with a differential amplifier and connected

40

the noise generator to the positive input (see Fig. 3.19). The Fig. 3.19 isdescribed by the set of equations (3.50).

VoutVin

=1+

Z2Z1

1+ 1K(ω)

(1+

Z2Z1

)Z1 = 1

iωCC+ RD

1+iωCDRD= 1+iωRD(CC+CD)

iωCC(1+iωRDCD)

Z2 = Rf

(3.50)

The analysis is limited at the module because the phase is not so impor-

tant. At first, at low frequenciesK(ω) is large enough to neglect 1K(ω)

(1 + Z2

Z1

)in (3.50) in the first equation of (3.51).

VoutVin

=

{1 + Z2

Z1, if ω < 1

τamp;

−Kiωτamp

, if ω > 1τamp

;(3.51)

VoutVin

= 1 +Z2

Z1

= 1 +iωRfCc(1 + iωRDCD)

iωRD (CD + Cc)(3.52)

For ω < 1τamp

, from (3.52) it’s possible to make the following approxima-

tions, considering RfCc ∼ RDCD.

VoutVin

=

1, if ω < 1

RD(CD+Cc);

1 +RfCc

RD(CD+Cc), if 1

RD(CD+Cc)< ω < RfCc;

iωRfCcRDCD

RD(CD+Cc), if ω > 1

RfCc;

(3.53)

3.6.3 Simulation

Computer simulation is more accurate than the previous analysis, because itdoesn’t neglect some conditions and it considers all contributes of noise inthe circuit (flicker noise too). In Fig. 3.20 the voltage noise spectral densityat amplifier output is plotted and In Fig. 3.21 the the voltage noise spectraldensity at the output of the buffer. It’s possible to observe that low-passfilter of the buffer reduces the noise at high frequencies.

Integrating the voltage noise spectral density at buffer output, we can getRoot-Mean-Square noise voltage (Vrms), useful for signal-noise ratio (

VsignVrms

).Table 3.1 lists the noises in order of magnitude. The sum of these noises isthe Total Noise.

I12.I0.M0.m1: Input PMOS transistor of amplifier;I12.I0.M3.m1: DC current generator of amplifier;I12.I0.M17.m1: one of NMOS transistor in bias circuit for amplifier;I12.I0.M18.m1: one of PMOS transistor in bias circuit for amplifier;

41

� �3�3�6�.�1�9�2�1�k�H�z�,� �5�4�.�0�1�5�6�1�p�V�*�*�2�/�H�z

� �A�m�p�O�U�T�(�V�N�2�)

�V�*�*�2�/�H�z� �(�p�V�*�*�2�/�H�z�)

�-�1�0�.�0

�0�.�0

�1�0�.�0

�2�0�.�0

�3�0�.�0

�4�0�.�0

�5�0�.�0

�6�0�.�0

�N�a�m�e

�f�r�e�q� �(�H�z�)�1�0

�2�1�0

�3�1�0

�4�1�0

�5�1�0

�6�1�0

�7�1�0

�8�1�0

�9

�N�o�i�s�e� �R�e�s�p�o�n�s�e

Figure 3.20: Plots of the voltage noise spectral density at amplifier output.

� �2�8�5�.�1�8�6�k�H�z�,� �3�5�.�3�0�2�9�4�p�V�*�*�2�/�H�z

� �O�U�T�(�V�N�2�) �

�V�*�*�2�/�H�z� �(�p�V�*�*�2�/�H�z�)

�-�2�0�.�0

�0�.�0

�2�0�.�0

�4�0�.�0

�6�0�.�0

�8�0�.�0

�1�0�0

�N�a�m�e �.�.�.

�f�r�e�q� �(�H�z�)�1�0

�2�1�0

�3�1�0

�4�1�0

�5�1�0

�6�1�0

�7�1�0

�8�1�0

�9

�N�o�i�s�e� �R�e�s�p�o�n�s�e

Figure 3.21: Plots of the voltage noise spectral density at buffer output.

42

Table 3.1: List of the noises in order of magnitude. In “param” column: fn isflicker and id is thermal

Device Param Noise Contribution % Of TotalI12.I0.M17.m1 fn 0.00598571 15.39I12.I0.M0.m1 fn 0.00567598 13.84I12.I0.M3.m1 fn 0.00519602 11.60I12.I0.M0.m1 id 0.0049407 10.49I12.I1.M4.m1 id 0.00476401 9.75I12.I0.M17.m1 id 0.00445346 8.52I12.I0.M3.m1 id 0.00411267 7.27I12.I0.M18.m1 fn 0.00354573 5.40

Total Noise 0.015258VInput Referred Noise 60.2716 nV

I12.I1.M4.m1: PMOS transistor used as bias resistance for sensor;Observing Figure 3.17 Vout has a peak value about similar to the total

noise. This means that it’s probable that noise can prevail on signal and soit could be impossible to discern signal and noise.

43

44

Chapter 4

The KC01 Chip

The BCD technology was never been studied by the Physics Department atUniversita degli Studi di Milano. STMicroelectronics provided some tran-sistors made with BCD technology to be analyzed under radiation. Thisanalysis can tell us if BCD technology can work in radiation environmentor not. The experimental analysis of the KC01 chip have three phases: thefirst the analysis will be done in laboratory conditions; the second one duringirradiation; the third one after the strong proton irradiation.

4.1 Chip and Bonding

4.1.1 Chip

The KC01 chip contains several transistors designed in BCD technology,each of them having different type, area, and geometry, with respect to theothers. The KC01 layout in Figure 4.1 exhibits a pads matrix. Every rowconsists of transistors of the same type. From the first to the fourth row,we can find transistors working at 1.8 V and from the fifth to the last rowthere are transistors working at 5 V. We are interested only on the first group(1.8 V) because they are the same type of transistors used for the KC53A testchip. The first two rows (1 and 2) are the pads of linear transistors, while thesecond two rows (3 and 4) are the pads of Enclosed-Layout-Transistor (ELT),wwich have circular geometry. Moreover, the first and the third rows containP-channel MOSFETs, while the second and the fourth rows contain the N-channel MOSFETs. Every transistor is built in a body isolated from thesubstrate. P-channel MOSFETs are built on a N-Well. A reverse bias voltageof the PN-junction between N-Well and substrate isolates transistors insidethe N-Well from the substrate. On the other hand, N-channel MOSFET bulk

45

Figure 4.1: KC01 Layout

46

Teg1− 1V 8CMOS −NoiseWEL L Notes S D G B DPC Sub

T1D1 1V8Pch 10 10 NG=2; SDS 1 2 21 19 20 22T1D2 1V8Pch 10 1 NG=2; SDS 3 4 21 19 20 22T1D3 1V8Pch 20 1 NG=2; SDS 5 6 21 19 20 22T1D4 1V8Pch 40 1 NG=2; SDS 7 8 21 19 20 22T1D5 1V8Pch 100 1 NG=2; SDS 9 10 21 19 20 22T1D6 1V8Pch 100 1 NG=20; SDS 11 12 21 19 20 22

Teg2− 1V 8CMOS −NoiseWEL L Notes S D G B N-ring Sub

T2D1 1V8Nch 10 10 NG=2; SDS 1 2 21 19 20 22T2D2 1V8Nch 10 1 NG=2; SDS 3 4 21 19 20 22T2D3 1V8Nch 20 1 NG=2; SDS 5 6 21 19 20 22T2D4 1V8Nch 40 1 NG=2; SDS 7 8 21 19 20 22T2D5 1V8Nch 100 1 NG=2; SDS 9 10 21 19 20 22T2D6 1V8Nch 100 1 NG=20; SDS 11 12 21 19 20 22

Teg3− 1V 8CMOS − Closed−NoiseWEL L Notes S D G B DPC Sub

T3D2 1V8Pch 10 1 NG=2; SDS 3 4 21 19 20 22T3D3 1V8Pch 20 1 NG=2; SDS 5 6 21 19 20 22T3D4 1V8Pch 40 1 NG=2; SDS 7 8 21 19 20 22T3D5 1V8Pch 100 1 NG=2; SDS 9 10 21 19 20 22T3D6 1V8Pch 100 1 NG=20; SDS 11 12 21 19 20 22

Teg4− 1V 8CMOS − Closed−NoiseWEL L Notes S D G B N-ring Sub

T4D2 1V8Nch 10 1 NG=2; SDS 3 4 21 19 20 22T4D3 1V8Nch 20 1 NG=2; SDS 5 6 21 19 20 22T4D4 1V8Nch 40 1 NG=2; SDS 7 8 21 19 20 22T4D5 1V8Nch 100 1 NG=2; SDS 9 10 21 19 20 22T4D6 1V8Nch 100 1 NG=20; SDS 11 12 21 19 20 22

Table 4.1: Description of transistors which there are in KC01 and relatives padstransistors components are connected to. The number of Teg corresponds to num-ber of row. WEL = effective channel width. L = channel lentgh. S = Source. D= Drain. B = Body. Sub = Substrate

47

is a P-Well surrounded by an N-doped region, called “N-Ring”. So, whenthis PN-junction is reversely biased, all the devices designed within the N-ring are isolated from the substrate. Moreover, NMOS gates are shortedto a N+ region in the substrate. This connection protects gate oxide fromESD during fabrication step when plasma is used. Similarly, PMOS gatesare shorted to a P+ region in an N-Well, called “Diode Protection Cathode”(DPC). PN-junctions between P+ region and N-Well are reversely biased.From the Table 4.1, it’s possible to understand which pads must be bondedand connected to measurement instruments, to analyze a particular transistorin the chip. From the same table, we see that we have 12 linear transistors(6 PMOS and 6 NMOS) and 10 ELTs (5 PMOS and 5 NMOS) working at1.8 V. It’s necessary to emphasize the absence of any ESD protection on thepads. So, it’s possible that some transistors are broken by an electrostaticdischarge during assembly and manipulation.

4.1.2 Bonding

Figure 4.2: Package draw (on the left) and pin order on the package (on the right).

According to what said before, it’s necessary to make 16 bonding for thefirst two rows and 14 for the second two rows, to connect all transistors. Ifwe bond all these pads on the same package, the chip must be put on a 60pin package at least. Anyway, bonding all pads on the same package is verydifficult. To simplify this part of experiment, it has been decided to bondfirst two lines on a package and the other two on an other package. However,for this test a 68 pin JLCC package is used because there are 17 pin on every

48

Figure 4.3: Schematic bonding for linear transistors (on the left) and ELT (on theright) working at 1.8 V.

sides; so, for simplicity it’s possible to bond a line on a side and the otherline on the opposite side of the package. In this way two sides are not used,but the bonding is simpler and faster. At the end the package where lineartransistors are bonded contains 32 and the package where ELTs are bondedcontains 28. Actually, the substrate is in common for all 8 rows of pads. So,only one substrate pad will be bonded. However, instead having a bondingin less, we keep previous bonding number because it has been decided tobond the Substrate also from chip back. In fact, it’s possible that transistorsbehavior could be different in these two cases. Now it’s important to talkabout the order (numeration) of the pins to bond right pads and so to buildan appropriate test board. It’s possible to see an inner pin with a 45◦ cut inthe middle of pin row on the right. In Figure 4.2 (right) this pin is circledin red. This is the pin number 1 and the others are numbered starting fromthis one in counterclockwise direction.

The KC01 chip is placed inside the package cavity in such a way thatrows of pads are in horizontal direction (pad1 on the left and pad22 on theright). As said before, bonding will be made with only two rows of pins. Inparticular, the row at the top will be bonded with pads line number 2 (forlinear transistors) and with line number 4 (for ELTs). Instead, the row atthe bottom will be bonded with pads line number 1 (for linear transistors)and with line number 3 (for ELTs). Figure 4.3 shows what has just beendescribed. In particular, we can observe pin 10 bonded to a soldering pointin the gold cavity, which is shorted to the chip back size by a conductive glue.

49

Figure 4.4: Photographs of bonding for linear transistors (on the left) and ELT(on the right) working at 1.8 V. The chip is connected to the package cavity withconductive glue.

It’s necessary to specify that Figure 4.3 is not in scale, i.e., chip dimensionsare not proportional to package dimensions. Chip dimensions have beenenlarged to better show the bonding connections. In Figure 4.4 one cansee the real chip bonded to the package. Wire bondings are used, made ofaluminum wires with 17 µm diameter.

4.2 PCB and Measurement Setup

The board has been built observing the bonding made for these chips and thepackage used. First of all, an appropriate socket, where the packages can beinserted, has been identified. Then, this socket has been soldered to a plasticplane, and external connectors are shorted to connected to the socket.

A Semiconductor Parameter Analyzer has been used to analyze KC01.This is equipped with a ground unit and 3 Source Meter Unit (SMU) whichcan be both voltage generator and current meter. Anyway, we need to bias 6elements which must be biased to analyze KC01 transistors (see Table 4.1).So, we have connected to the test fixture the 3 SMU and the ground unit ofthe Semiconductor Parameter Analyzer and two external voltage generator.One of the two external generators is a source meter, which is a voltagegenerator which detects the current (it’s similar a SMU, but the detecteddata aren’t recorded on the computer as the SMU).

50

CONNECTORS

SOCKET

Figure 4.5: Front (on the left) and Back (on the right) of the board

Figure 4.6: Semicondactor Parameter Analyzer (on the left) and test fixture (onthe right) connected to the board

51

4.3 Biasing

MOSFETs work at 1.8 V and they are built in BCD technology; so, we canbias these transistors with potential between 0 V and 1.8 V, while biasingsubstrate with a nearly −50 V potential. We want to characterize thesetransistors in three different configurations:

• ID(Vds), changing Vgs step by step;

• ID(Vgs), keeping Vds at maximum voltage drop (and so keeping tran-sistor in saturation);

• ID(Vds), keeping Vgs = 0V (observing leakage drain current).

To simplify these analyzes, we have decided to set the source voltage atground (0 V) both in NMOS and in PMOS. So, gate voltage (Vg) is directlygate source voltage (Vgs = Vg − Vs = Vg) and drain voltage (Vd) is directlydrain source voltage (Vds = Vd − Vs = Vd). In this conditions it’s possible tohave directly characterization plots without any computer elaboration. Table4.2 summarizes the polarizations and the voltage ranges.

Table 4.2: Biasing voltage range of NMOS and PMOS tranistors

NMOS PMOSSource 0 V 0 VDrain 0 V → 1.8 V 0 V → −1.8 VGate 0 V → 1.8 V 0 V → −1.8 VBody 0 V 0 V

N-ring/DPC N-ring = 1.8 V DPC = 0 VSubstrate 0 V → −50 V −1.8 V → −51.8 V

We can notice that we have translated all potentials from NMOS to PMOSto keep source and body voltagse at ground. In spite of this voltage transla-tion all transistors work with the same voltage drop.

4.4 Results

Substrate voltage = 0V (NMOS) / –1.8V (PMOS)

We have analyzed all NMOS transistors with substrate at 0 V and all PMOStransistors with substrate at−1.8 V. We started from these substrate voltages

52

to analyze these transistors in safe conditions (they work in 1.8 V voltagedrop). We have analyzed all the transistors (22 MOSFETs). Figure 4.7shows the characterization of one of 22 transistors: the PMOS ELT with100 µm × 1 µm channel size. Table 4.3summarizes which transistors areworking or broken.

PMOS lin (T1) NMOS lin (T2) PMOS ELT (T3) NMOS ELT (T4)D1 Broken OK!D2 Broken Broken OK! OK!D3 Broken OK! OK! OK!D4 Broken OK! OK! OK!D5 OK! OK! OK! BrokenD6 OK! OK! OK! OK!

Table 4.3: OK! = working transistor; Broken = NO-working transistor.

We can observe that in the first, in the second and in the fourth group ofplots, the gate current (IG) is too much large. This effect can be explainedby the presence of broken transistors. In fact, the third group of transistors(circular PMOS) are all working and gate current is very low (< 1 pA).On the other hand, in the other 3 groups there is a broken transistor atleast. When the gate oxide layer is broken, a conductive channel can beproduced. So, when transistors are switched on, a current flows from gate tochannel through the resistive breaking of gate oxide. The gate current of thethird group of transistors cannot be measured because it is lower than theresolution of Semiconductor Parameter Analyzer (nearly 1 pA).

Furthermore, we have analyzed transistors with substrate biased onlyfrom the package cavity, and not from the pad. From the plots in Figure4.11 and 4.12, no difference can be observed. It’s necessary to say that alllaboratory characterizations were made in DC. So, capacitive and inductiveeffects can’t be detected by the Semiconductor Parameter Analyzer.

Substrate voltage till –50V (NMOS) / –51.8V (PMOS)

With the previous analysis we have seen transistor characterization whensubstrate voltage is zero. Now, we want to characterize these transistorswhen the sustrate voltage is very negative (Vsub = −50 V (NMOS) / −51.8 V(PMOS)). We have brought the substrate to large negative voltages stepby step, without noticing any different behavior, as shown in Figure 4.13,until the substrate voltage does not exceed −25 V for PMOS or −23 V forNMOS. Below these values, we observed a current flowing from substrate

53

Figure 4.7: T3D6 (PMOS ELT, 100 µm × 1 µm, NG = 20) characterization withSubstrate voltage at −1.8 V biased from pad (above) and from cavity (below).

54

Figure 4.8: PMOS ELT, 100 µm × 1 µm, NG = 20) parasitic gate current (Vgs =0 V) with Substrate voltage at −1.8 V biased from pad (above) and from cavity(below).

55

Figure 4.9: T3D6 (PMOS ELT, 100 µm × 1 µm, NG = 20) leakage drain current(Vgs = 0 V) with Substrate voltage at −1.8 V biased from pad (above) and fromcavity (below).

56

Figure 4.10: T3D6 (PMOS ELT, 100 µm × 1 µm, NG = 20) characterization withSubstrate voltage at −1.8 V biased from pad (above) and from cavity (below).

57

Figure 4.11: T3D6 (PMOS ELT, 100 µm × 1 µm, NG = 20) characterization withSubstrate voltage at −1.8 V (above) and −25 V (below)

58

Figure 4.12: Parasitic gate current of T3D6 (PMOS ELT, 100 µm × 1 µm, NG =20) with Substrate voltage at −1.8 V (above) and −25 V (below)

59

to DPC for PMOS, or to N-ring for NMOS. This current increases withthe substrate voltage. It’s known that between the substrate (lightly P-doped) and N-ring/DPC (N-doped) there is a PN-junction. So, a junctionbreakdown occurs when the substrate to N-ring/DPC voltage drop is largerthan 25 V. Anyway, this current seems to be proportional to the substratevoltage, due to resistive effects in series with the substrate. This currentcan’t overcome 0.1 mA because it is limited by compliance current set up onthe Semiconductor Parameter Analyzer. This limit was set up to preservethe chip from possible damages.

4.5 Conclusions

After first analyses on KC01 it’s possible to say some of the transistors arebroken, probably because of the absence of ESD protection. If one transistoris broken, a parasitic gate current is detected for every tranistors in the row,because broken transistors are switched on, and the current flows throughthe damaged oxide. If all transistors in a row are not broken, a parasiticgate current is detected, which is lower than the Semiconductor ParameterAnalyzer resolution. All transistors work in the same way at different sub-strate voltage. When substrate and N-ring/DPC voltage drop is larger than25 V, we have observed a breakdown of the PN junction. Naturally, thereis no damage caused by breakdown, as the heat produced by this effect isdissipated. Moreover, it’s possible to observe that channel length modulationeffects are negligible.

60

Figure 4.13: Breakdown current flowing from DPC (above) to Substrate(below)

61

62

Chapter 5

Irradiation

The transistors in the KC01 test chip were characterized in laboratory with-out radiation, as described in the previous chapter. As we intend to use theBCD technology in radiation environment, it’s necessary to irradiate thesedevices and test their radiation hardness, as some parameter can change af-ter irradiation. We had the opportunity to irradiate the chip at LaboratoriNazionali del Sud (LNS) in Catania.

5.1 Irradiation effects

During irradiation two effects occur. The first effect is the displacementin silicon crystal lattice and the second the ionization in the silicon oxide.These can change the value of some parameter (threshold voltage, transcon-ductance, ...). This section is based on [5] and [7].

5.1.1 Displacement

Ionizing particles interact with silicon lattice and they can transfer enoughenergy to displace lattice atoms. This displacement introduce energy lev-els within band-gap and this effect changes generation and recombinationprobabilities. The main consequence is the changing of parameters value,like mobility or doping density. At the end, displacement changes electricproperties of crystal lattice.

5.1.2 Ionization

It’s known that particles with charge interact with semiconductor material.They give enough energy to electrons which pass to the conduction band

63

Figure 5.1: Threshold voltage shift due to irradiation [5].

64

from valence band. So, we find a free electron in conduction band and ahole in valence band. When there is no electric field, electrons and holesrecombine. However, if an electric field is present, electron-hole pairs areseparated and so they don’t recombine. This can occurs in silicon oxide. Inan NMOS transistor the gate voltage is higher than body, so the electric fieldin the silicon oxide is directed from the gate to the body. So, free electronsare collected quickly by the gate electrode because of their high mobility(20 cm2/V·s). On the other hand, holes are slowly collected near the SiO2-Siinterface, because their mobility ranges from 10−4 cm2/V·s to 10−11 cm2/V·s.Then, the holes can’t pass into the body and they are trapped on SiO2-Siinterface. The trapped holes decrease threshold voltage; in fact, less positivecharges are required on gate electrode to switch on the transistors. Theoret-ically, the thinner the silicon oxide is, the more negligible this effect is. Inthe PMOS transistor the gate have voltage is lower than body voltage. So,free electrons are driven near SiO2-Si interface and holes are collected at thegate electrode. Instead, free electrons aren’t trapped at SiO2-Si interface andthey pass from silicon oxide to silicon (body). At the end, threshold voltagein NMOS transistors shifts because of holes trapped coming from ionizationin silicon oxide. Instead, threshold voltage in PMOS transistors don’t shiftbecause electrons aren’t trapped. An other effect coming from ionization ischarge trapping in lattice defects on SiO2-Si interface. In fact, the defectson SiO2-Si interface introduce energy levels within band-gap. After particlesionization channel charge can pass and be trapped in these energy levels. Inthis case we are talking about of channel charge, so both PMOS and NMOShave threshold voltage increasing in module. In NMOS these charges com-pensate trapped holes in silicon oxide at first, then they prevail. Anyway,it’s necessary to underline that there are ionization effects only if transistorsare biased, otherwise, the charge trapping can’t happen in both cases andany parameter doesn’t change.

5.2 Equipment

5.2.1 Chip Bonding

For the test in radiation environment we have bonded all the pads of a testchip on a single package. Moreover, for security, we have decided to bondtwo packages in the same way, to have a spare part if one of the packageswas damaged during the journey. Figure 5.2 shows one of the packages.

65

Figure 5.2: All the pads bonded on the same package.

66

5.2.2 PCB

Before starting to describe the board for this experiment, it’s necessary todescribe the measurement setup. At LNS there isn’t the possibility to usea Semiconductor Parameter Analyzer. Anyway, we could use voltage gen-erators, a signal generator and an oscilloscope. Voltage generators are usedto bias transistors. The signal generator is used to drive the gate voltage.We want to see drain current as a function of the gate-source voltage, butan oscilloscope can’t detect the current. In a DC analysis it’s possible to getdrain current observing drain voltage drop when transistors are in series withresistors (drain is connected to resistor as in Figure 5.3). At the end draincurrent is calculated with the Ohm’s law.

Figure 5.3: Schematic plot of the board. PMOS schematic (left); NMOS schematic(right).

The board must contain resistors which are connected in series to tran-sistors. Anyway, there is the problem of the radiation because the packagewe have used contain gold (in particular, the cavity) and when gold is ir-radiated with protons (or neutrons) it becomes radioactive. For this reasonit’s dangerous to put interfacing connectors near the socket (and so near thepackage). So, we decided to put them on a different board and to put andconnect resistors on the board where there are interfacing connectors. Thetwo boards are connected with long cables (about 2 m) to guarantee a safedistance from package radiations. To simplify the data collection we haveplaced the connectors in an order similar to that on chip layout. As writtenin Sect. 5.1 to see any variation of parameter values and also to irradiate

67

transistors in conditions similar to ATLAS ones, all transistors have to beswitched on with voltage drops as large as possible. In this case maximumvoltage drops is 1.8 V. This is possible if we bias transistors directly fromconnectors, bypassing the resistors.

Figure 5.4: The two parts of the board: the part with the socket (on the left) andthe part with interfacing (male) connectors and resistors (on the right).

Figure 5.5: Part of the board used to bias and to keep switched on the transistorsduring irradiation. Above, female connectors which must be connected to maleconnectors in Figure 5.4. Below, BNC connectors to be connected to voltagegenerators.

During the last minutes before irradiation we made some corrections onthe board. In particular, if you observe Figure 5.5 there are 4 BNC connectorsand one of them is at ground. At the end we have used the external partof BNC connectors as common ground. There are two BNC connectors at1.8 V: one of them biases the linear transistors and the other one biases the

68

circular transistors. So, we can detect the sum of linear transistors currentsand of circular ones separately during irradiation. Using this configuration wecan know if linear and circular transistors have similar or different behaviorduring irradiation, without stopping proton beam to collect data from everytransistors.

5.3 Experiment

5.3.1 Beam

Before irradiation, a dosimetry of the proton beam was made, to calculatethe radiation dose that the chip has received. A radiation sensitive platehas been used for this purpose (see Figure 5.6). Then a computer programhas been used to verify the beam uniformity (in particular, where the chip isplaces) and to calculate the proton dose rate. So, it’s possible to calculate thetotal dose, knowing how much time the chip has been irradiated. We haven’tdealt with dose rate calculations, and we have employed the dosimetry data.The irradiation duration was about 24 h and, using the dose rate calculatedfrom the radiation sensitive plate, we were able to obtain the total dose:32 MRad within an error of 20%.

Figure 5.6: Radio-sensitive plate for dose rate calculation. Horizontal (on the left)and Vertical (on the right) profiles of proton dose

5.3.2 During Irradiation

After each stop of irradiation it was necessary to wait for the reductionof radiation level coming from the package (about 30 min at least), beforeperforming any data collection, even if the distance between the packageand connectors for interfacing is about 2 m. So, we have decided not to

69

Table 5.1: Data collection during irradiation.

Time Substrate Linear CircularMartedı

BeforeRad 4.5µA 32.3 mA 25.9 mA2:30 BeamStart;SEMCurrent = 10nA2:32 3.8µA 32.5 mA [23.5; 15.6] mA2:37 3.8µA 32.5 mA 0.2 mA2:42 BeamStop2:51 3.6µA 32.8 mA 20 mA2:52 BeamRestart2:55 3.6µA 32.8 mA 0.2 mA3:50 2.1µA 32.9 mA 0.6 mA4:22 2.0µA 32.9 mA 0.74 mA5:02 1.8µA 33.0 mA 0.84 mA5:18 1.9µA 33.0 mA 0.86 mA6:04 1.8µA 33.0 mA 0.70 mA6:33 1.7µA 33.0 mA 0.70 mA7:00 1.6µA 33.0 mA 0.70 mA8:14 1.3µA 33.0 mA 0.70 mA9:27 0.85µA 33.0 mA 0.70 mA10:57 0.85µA 33.0 mA 0.55 mA11:32 SEMCurrent = 20nA11:50 SEMCurrent = 10nA11:51 0.74µA 33.0 mA 0.55 mA12:32 0.68µA 33.0 mA 0.53 mA12:45 0.66µA 33.0 mA 0.51 mA13:45 0.59µA 33.0 mA 0.49 mA14:25 0.55µA 33.0 mA 0.50 mA15:30 0.50µA 32.9 mA 0.50 mA

Marcoledı1:18 0.26µA 32.6 mA 0.44 mA1:59 0.24µA 32.57 mA 0.43 mA2.00 BeamStop8.30 0.20µA 32.4 mA 20 mA

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make any intermediate data collection. Anyway, the chip has been biased byvoltage generators which could detect how much current is supplied to lineartransistors group and circular one. So, during the entire period of irradiationtime the supplied currents were measured (see Table 5.1).

5.3.3 After Irradiation

After having stopped the proton beam, we couldn’t collect immediately databecause of residual radiation coming from the package. We started collectingdata 8 h after beam stopping. All transistors were checked and analyzed usingthe voltage wave generator and the oscilloscope. With this measurementsetup, we have collected both the gate voltage wave and drain voltage drop(see Figure 5.7). To analyze these data it’s necessary to plot the drain voltagedrop in function of the voltage wave, which is gate source voltage, and thenthe drain Current in function of the gate source voltage, using Ohm’s law.

Figure 5.7: Plots of VG(t) (above) and VD(t) (below) (T2D5).

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Figure 5.8: Plots of T2D5 characterization before (above) and after (below) 32MRad of TID.

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5.3.4 Analysis

Now, we have data before and after irradiation and we can compare thresholdvoltage (Vth) and transconductance (gm) in these two situation. So, we tokethe transistors characterization before and after (like Figure 5.8), which plotdrain current in function of source voltage drop. It’s possible to fit bothmeasuremens with the same equation (5.1). These fits have been done usingROOT libraries and implementing an dedicated C++ program.

ID =

{0, if VGS < VTH ;

I0 + gm (Vgs − Vth)2 , if VGS > VTH .(5.1)

I0 is the offset current, gm is the transconductance and Vth is the thresholdvoltage. In the original equation offset current isn’t mentioned, but we havedecided to insert this modification in case that there were some errors inpolarization coming from the heat produced during the working of equip-ment. So, the offset current isn’t an important parameter to be analyzed.Furthermore, the part of channel-length modulation has been neglected (seeSect. 4.5) and in (5.1) the transistor equation in saturation region is used.Transistors are in saturation when VDS > VGS−Vth. Instead, when transistorsare in triode, we can’t fit the plot with (5.1). For simplicity we fit transistorscurves only in saturation conditions. But, the entire characterization is notin saturation conditions; in fact, in Figure 5.8 you can notice there are twodifferent behavior. When VGS < 1.6 V nearly, transistors are in saturation;instead, when VGS > 1.6 V, transistors are in triode. The measurementswere fitted when VGS < 1.4 V, which avoids the triode region. At the endit’s possible to compare the transconductance and the threshold voltage (seeTable 5.2 and Figure 5.9). In Table 5.3 we have shown all transistors results;in particular, we have shown the percent difference of transconductance andthreshold voltage for every transistors.

Table 5.2: gm and Vth before and after proton irradiation. T2D5: Linear NMOStransistor with W/L = 100 µm / 1 µm.

Before AfterVth (366.784± 3.3 10−4) mV (430.684± 5.4) mVgm (8.82448± 6.3 10−6) mA/V2 (7.5409± 0.095) mA/V2

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Figure 5.9: Fits of T2D5 characterization (offset current set to zero).

Table 5.3: gm and Vth before and after proton irradiation. Linear NMOS transistorwith W/L = 100 µm / 1 µm.

T1D1 T1D2 T1D3 T1D4 T1D5 T1D6Vth 14.68% 38.54% 16.10% 12.15% 21.05% 14.31%gm 0.82% –40.24% –3.92% –2.27% –4.03% –7.67%

T2D1 T2D2 T2D3 T2D4 T2D5 T2D6Vth 14.68% 9.86% 19.48% 11.12% 16.90% 17.42%gm 1.93% –3.24% –6.77% –14.24% –11.37% –14.55%

T3D2 T3D3 T3D4 T3D5 T3D6Vth 36.94% 45.82% 45.56% 25.98% LOST DATAgm –0.72% –5.82% –6.38% –4.61% LOST DATA

T4D2 T4D3 T4D4 T4D5 T4D6Vth 55.03% 12.64% 13.90% 41.45% 19.29%gm 1.25% –0.67% 0.81% –9.27% –9.45%

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Chapter 6

Conclusions

Radiation Hardness

MOS transistors designed in BCD technology have been studied in radiationenvironment. Results are very preliminary and don’t provide specific resultsfor each type of transistor because statistics would be required, for each typeof transistors only one was tested under radiation. Anyway, it’s possible togive qualitative results about every groups of transistors of the same type(PMOS/NMOS) and with the same channel geometry (Linear/Circular),even if designed with different sizes. All linear transistors supported highradiation dose, working during irradiation and after 32 MRad of total dose.The threshold voltage Vth is increased in module (around 15%) and transcon-ductance gm didn’t change so much, unless in few transistors. Instead, allcircular transistors (or most of them) were switched off during irradiation.Moreover, although these transistors were still conductive after 8 hour of an-nealing, in all PMOS and some NMOS ELTs the threshold voltage increasedin module very much (around 40%); some NMOS ELTs exhibited a similarincreasing of linear transistors. Anyway, ELTs transconductance didn’t varyrelevantly, as for linear transistors. At the end it’s possible to assert thatlinear transistors are radiation harder than ELTs.

Preamplifier Analysis

Small-signal analysis shows through simulations that the maximum gain iswithin the bandwidth between around 104 Hz and 106 Hz, while for otherfrequencies the signal is not ampified. So, this amplifier is too slow and itdoesn’t satisfy ATLAS upgrade requirements (100 MHz at least); in fact, thiscircuit is not optimized. Probably, the RC time constants in the sensor stage(see Figure 3.8) and in buffer stage (see Figure 3.13) slow down the circuit.

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The amplifier bandwidth is approximately 107 Hz, so the amplifier has tobe optimized too. Moreover, according to simulations, the output voltagesignal is 15 mV, which is very similar to root-mean-square voltage noise(nearly 15 mV); so, it’s improbable to observe a signal because this could becompletely covered by noise coming from bias rersistance and PMOS inputtransistor of the amplifier.

Further Development

Next prototypes will be designed using linear transistors, because of theirbetter radiation hardness. Circuit optimization is required to improve speedperformance and to increase the signal/noise ratio.

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