Stuck Attesting

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Fundamental Algorithms

for System Modeling,Analysis, and Optimization

Edward A. Lee, Jaijeet Roychowdhury,Sanjit A. SeshiaUC BerkeleyEECS 144/244Fall 2010

Copyright © 2010, E. A. Lee, J. Roychowdhury, S. A.Seshia, All rights reserved

Lec 15: Testing for Fault Detection/Diagnosis

Thanks to K.-T. Cheng, S. Devadas, K. Keutzer for some slides

2

Fault Detection and DiagnosisA fault is the adjudged or hypothesized cause of a

system failure.

Fault detection (is there a fault?) and diagnosis (where isthe fault?) are key steps in system design andmaintenance.

Integrated Circuits

– Faults: manufacturing defects or electrical effects

Control Systems (e.g. chemical process plants) – Faulty sensors or actuators, operator error, mechanical failures

Cyber-Physical Systems (e.g., cars, spacecraft)

– Faulty sensors/actuators, mechanical failures, …



3

Fault Detection and Diagnosis

.

.

.

.

.

. I N P U T S

O U T P U T S

XVE

Overall System

Propagation

(observability)Vc

Activation

(controllability)

Component

4

Observability and Controllability

Controllability

– A system with internal state x is called controllable ifthe state can be modified by changing the input to thesystem.

– E.g., for circuits: put a 0 or 1 at an arbitrary internalnode

Observability

– A system with internal state x is called observable ifthe state can be determined by observing the outputsof the system.

– E.g., for circuits, observe the 0-1 value of an internalnode from system outputs.



5

Manufacture Testing in ICs

Apply a sequence of input vectors to a circuit

Observe the output response and compare theresponse with a precomputed or “expected”response

Any discrepancy is said to constitute an error, thecause of which is a physical defect

FAB

?

a

b

s

q

0

1

d

clk

6

Defects and Fault models

Manufacturing defects can manifest in a variety of ways:

– Bridging

– Contaminants

– Shorts

– Opens

– Transistors stuck-open

These need to be reduced to models:

– Single stuck-at-1, stuck-at-0

– Multiple stuck-at-1, stuck-at-0

– Delay fault models:• Gate

• Path

– single-stuck-at fault model ubiquitous

– some use of delay fault modeling



7

Defect Model: Stuck-At Faults

Any input or internal wire in circuit can bestuck-at-1 or stuck-at-0

Single stuck-at-fault model: In the faultycircuit, a single line/wire is S-a-0 or S-a-1

Multiple stuck-at fault model: In the faultycircuit any subset of wires are S-a-0/S-a-1(in any combination)

a bf1

f2

AB

CD

8

Outline of Topics

Basics & Terminology

Single stuck-at faults and path sensitization

Boolean Satisfiability-based technique



9

Formal Problem Definition

Given a combinational circuit on n variables x1, x2, …, xnwith m outputs f1, f2, …, fm

Let g be an internal net that is stuck at 0

Then, we wish to find values of x1, x2, …, xn such that

g(x1, x2, …, xn) = 1

and there exists some j in 1,2,…m, such that

fj(x1, x2, …, xn) takes different values depending onwhether g is stuck at 0 or not.

How does the definition change for g stuck at 1 ?

10

Problem: What about the Flip-Flops?Solution 1: Unroll the sequential ckt in time

[Murray & Hayes, IEEE Computer, 1996]



11

Solution 2: Add scan logic

Scan Flip-flops

CombinationalLogic

add additional state to flip-flops(15 - 20% area overhead)

inputs outputs

Scan-chain Scan-chain

[See Murray & Hayes, IEEE Computer, 1996]

12

Outline of Topics






13

Single Stuck-At Faults

A fault is assumed to occur only on a single net.

x1

x2

x3

a

b

G

Z = x1 x2 + x2 x3

a s-a-1 Z = ?

G s-a-1 Z = ?

x1

x2

x3

a

b

G

This model is used because it has been found to bestatistically correlated with defect-free circuits

14

Single Stuck-At Faults

A fault is assumed to occur only on a single net.

x1

x2

x3

a

b

G

Z = x1 x2 + x2 x3

a s-a-1 Z = x1 + x2x3

G s-a-1 Z = x2x3

x1

x2

x3

ab

G

This model is used because it has been found to bestatistically correlated with defect-free circuits



15

Activation and Path Sensitization

In order for an input vector X to detect a fault hs-a-D, D = 0,1 the input X must cause thesignal h in the normal (fault-free) circuit totake the value D.

h

f

xs-a-1x2

x3

x1

x4

To activate the fault – i.e., detect h s-a-1we first need to make h = 0. How?

16

G3

Fault Activation

h0/1 0/1

0/1

h s-a-1, for h to be 0, need x2 = x3 = 0 ( x2 x3 )

G1

G5f

G4G2

xx2

x3

x1

x4

The condition is necessary but not sufficient.Error signal must be propagated to output(must affect the output value).



17

The error signal must be propagated alongsome path from its origin to an output

How to propagate the fault?

G3

Fault Propagation

h0/1


G1

G5f

G4G2

xx2

x3

x1

x4

18

The error signal must be propagated alongsome path from its origin to an output

Only one path G3, G5

In order to propagate an error through AND

gate G3, other input x1 = 1. To propagatethrough G5, need G4 = 0, x1 + x4

G3

Fault Propagation

h0/1 0/1

0/10

1


G1

G5f

G4G2

xx2

x3

x1

x4



19

Formal Problem Definition, Revisited

Given a combinational circuit on n variables x1, x2, …, xnwith m outputs f1, f2, …, fm

Let g be an internal net that is stuck at 0

Then, we wish to find values of x1, x2, …, xn such that

g(x1, x2, …, xn) = 1

and there exists some j in 1,2,…m, such that

fj(x1, x2, …, xn) takes different values depending onwhether g is stuck at 0 or not.

ACTIVATION

PROPAGATION

(Controllability)

(Observability)

20

Single Path Sensitization (SPS)1. Activate: Specify inputs so as to generate the

appropriate value (0 for s-a-1, 1 for s-a-0) at thesite of the fault.

2. Propagate: Select a path from the site of thefault to an output and specify additional signalvalues to propagate the fault signal along thispath to the output(error propagation).

3.Justify: Specify input values so as to producethe signal values specified in (2)(line justification).



21

Sensitization Example

h s-a-1

Activate?

f1

f2

G6

G5

G4G3

G1

h s-a-1

G2DABC

E

x

22


h s-a-1

Activate: To generate h = 0, need A = B = C = 1

Propagate?

f1

f2

G6

G5

G4G3

G1 h

G2DABC

E

x



23


h s-a-1

To generate h = 0, need A = B = C = 1

Have a choice of propagating through G5 or via G6.Propagating through G5 requires G2 = 1

A = D = 0 Contradiction

Propagating through G6 requires G4 = 1 C = 1, E = 0.

A valid test vector is ABCE

f1

f2

G6

G5

G4G3

G1 h

G2DABC

E

x

24

Line Justification

E s-a-1 E = 0

C = D = 1 to propagate through G1.

To propagate through G4, need G2 = G3 = 1

How do we justify these values?

G3

1G4G2

1

G1x

0 s-a-1

BHAF

CDE



25

Line Justification - 2

Attempt to line justify G2 = G3 = 1

G3 = 1 possible if A = F = 1 or B = H = 1

If A = C = 1, then G2 = 0.

G3 = 1 B = H = 1

G2 = 1 needs A = 0 or F = 0

Tests are A’BCDE’H, BCDE’F’H

G3

1G4G2

1

G1

x0

BHAF

CDE s-a-1

26

Not all faults result in failures!

Existence of a fault does not change thefunctionality of a circuit redundant fault

f = x1 + x1 x2 f = x1 + x2

A test generation algorithm is deemed completeif it either finds a test for any fault or provesits redundancy, upon terminating.

Redundancy

xs-a-1

x1

x2

fx1

x2

f



27

Completeness of SPS method ?

d s-a-0 A = B = 1

Propagate along G3, G6 C = 1

G2 = G4 = G5 = 1

For G4 = 1 either its top input = 0 or E = 0

If G1 = 0 fault is not activated (don’t want to force G1 = 0)

If E = 0 (B must be 1) G5 = 0 Inconsistency

AB

xd

s-a-0

f

G2

G6G3

G4

G5

C

E

G1

28

Completeness of SPS? - 2

Propagation along G4, G6 also results ininconsistencies by symmetric argument

Is there no test?

AB

xd

s-a-0

f

G2

G6G3

G4

G5

C

E

How about C = E = 1?



29

Multiple Path Sensitization

Error propagates down two paths G3, G6 and G4, G6to output (G3, G4 values are correlated)

It’s natural to work backwards (justifying) andforwards (propagating) from point of fault

activation but this focuses on sensitizing asingle path

Attempting to sensitize a single path will not find atest for this fault

1

1

1

1

1/0

1

0/1

0/1

1

xd

s-a-0

f

G2

G6G3

G4

G5

1/0

30

Note on the D-Algebra/ D-calculus

Need to be able to deal with an arbitraryerror at the inputs to a gate

D represents a signal which has value 1 innormal circuit, and value 0 in faultycircuit.

D 0/1

D, D behave like Boolean variables

DD

D

D0

0 D1

D

DD

D DD

0

D0

0



31

Outline of Topics




32

Another approach to ATPG (Larrabee, 1989)

The ATPG problem (automatic test pattern generation)

The CIRCUIT-SAT problem

The Boolean Satisfiability (SAT) problem

SAT

CIRCUIT-SAT

ATPG



33

The ATPG problem

Does there exist a value assignment to the primary inputs which distinguishes the faulty and correct

circuits ?

• A logic circuit

• A fault point

• A fault value

a

b

c

d

e

f

g

h

is-a-1

00(1)(1)

00(1)(1)

11

00

00

00

11

11

111, as f

Circuit C

34

The CIRCUIT-SAT problem

Does there exist a value assignment to the primary inputs which causes the primary output

to assume logic value ‘1’ ?

a

b

c

d

e

f

g

h

i



35

ATPG as a CIRCUIT-SAT problem

a

b

c

d

e

f

g

h

i

1

hf if

t = 1?

ATPG

ψ C Circuit

Can we find an input value in which the faulty circuit andthe good circuit differ?

36

The Boolean Satisfiability (SAT) problem

Given a formula, f :

))()(( cbacacba

C 1

C 2

C 3

a=b=c=1

(a,b,c)

(C 1,C 2 ,C 3 ) Comprised of a conjunction (AND) of clauses

Defined over a set of variables, V

Each clause is a disjunction (OR) of literals of thevariables V

Example :Example :

Does there exist an assignment of Boolean values tothe variables, V which sets at least one literal in each

clause to ‘1’ ?



37

CIRCUIT-SAT as a SAT problem

A set of clauses representing the functionality of eachgate

A unit literal (i) clause asserting the output to be ‘1’

a

b

c

d

e

f

g

h

i

))()(( f cb f c f b

))()(( h f ah f ha

))()(( ged gegd

)(i

))()(( ighigih

38

Solving the SAT problem

NP-complete problem, yet efficient techniques exist tosolve probems encountered in practice

We will review some of these methods in the next lecture



39

Current Status on Manufacture Test

Practical approach to test: use scan – achieve 99%+stuck-at coverage

Single stuck-at-fault testing for combinational logic is a``solved problem’’

– Despite the fact that it is NP-complete

– After 20+ years of research

– Results applied to combinational-equivalencechecking

Documents

Stuck Attesting