Stratix II GX & Stratix GXTransceivers With Integrity October 2005

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High-Performance FPGAs With Embedded TransceiversIf you need transceivers with superior signal integrity and the flexibility of an FPGA, you can rely on the Altera® Stratix® II GX and Stratix GX families. Building on the Stratix GX transceivers’ excellent jitter performance, the award-winning Stratix II architecture, and the industry’s easiest-to-use software, Altera created the Stratix II GX family and its complete system solutions to give you the tools you need for high-reliability systems for your trans-ceiver applications. Stratix II GX FPGAs are ideal for applications requiring high-bandwidth serial communica-tion, such as wireline, wireless, broadcast, military, test and measurement, and medical products.

Built for Your Success To meet your evolving transceiver requirements, Altera built Stratix II GX transceivers for best-in-class jitter performance over a wide range of data rates—from 622 Mbps to 6.375 Gbps—to comply with leading serial protocol standards. Stratix II GX devices offer up to 130,000 equivalent logic elements (LEs) and significantly enhanced pre-emphasis and equalization functionality. The high-performance 90-nm FPGA architecture, coupled with robust transceivers, helps you achieve your most challenging system performance and

high-speed interconnect goals.

To support your entire transceiver system, Altera offers design software, intellectual property (IP) cores, develop-ment kits and evaluation boards, reference designs, HSPICE models, and technical collateral. In addition, you can use board design tools from Cadence (Allegro SI) and Mentor Graphics (ICX and HyperLynx) to verify your design’s signal

integrity or simulate your entire system. Whether you are implementing standard or proprietary protocols or using transceivers for backplane or chip-to-chip applications, the Stratix II GX and Stratix GX families provide the most complete transceiver solutions for your designs.

Ideal Transceiver Features Stratix II GX transceivers support a wide variety of proto-cols in silicon. Each transceiver block includes dedicated circuitry to support the PCI Express, high-definition serial

Stratix II GX & Stratix GX Transceiver Features

Parameter Stratix II GX Stratix GX

Data Rate Range 622 Mbps—6.375 Gbps 500 Mbps—3.1875 Gbps

With Oversampling 270 Mbps 270 Mbps

Power Consumption 125 mW per Channel at 3.1875 Gbps

225 mW per Channel at 6.375 Gbps

150 mW per Channel at 3.1875 Gbps

Maximum Pre-Emphasis Level

500% 3 Taps

140% 2 Taps

MaximumEqualization Level

17 dB 4 Stages

9 dB 1 Stage

Output Differential Voltage Range

400 mV—1,400 mV 400 mV—1,600 mV

Channel Groups Quad (4 Receive Phase-Locked Loops (PLLs), 2 Transmit PLLs

Independent Channels 4 Different Data Rates

Quad (4 Receive PLLs, 1 Transmit PLL)

Independent Channels 1 Data Rate

Dynamic Reconfiguration

Yes Yes

Maximum Number of LEs

130,000 40,000

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digital interface (HD-SDI), standard-definition (SD)-SDI, XAUI, Serial RapidIO™ (SRIO), SerialLite II, and Gigabit Ethernet standards, among others. Both Stratix II GX and Stratix GX transceivers include built-in word detection and alignment circuitry and built-in 8b/10b encoder/decoders, which you can bypass when not required in your system. These devices are suitable for key standard and proprietary serial applications, and can be used in backplane or chip-to-chip applications.

Complete Protocol SolutionsIn conjunction with Stratix II GX FPGAs, Altera offers complete protocol solutions to simplify your design process and reduce your time-to-market. Serial data rates from 622 Mbps to 6.375 Gbps support popular standards with extra margin. The built-in Stratix II GX physical coding sublayer (PCS) blocks, which are part of the transceiver block, make designing for these standards easier than ever because they save valuable logic resources and simplify protocol support. In addition to meeting your hardware

requirements, Altera offers protocol-specific design software, development boards, IP cores, reference designs, and technical collateral (including board layout guidelines, characterization reports, and user guides).

Stratix II GX Device Family The 90-nm Stratix II GX family is Altera’s newest generation of FPGAs with embedded transceivers. The

family provides a complete solution for the growing number of applications and protocols requiring high-speed serial interconnect. Stratix II GX devices employ the same archi-tecture used in Stratix II FPGAs and integrate up to 20

serializer/deserializer (SERDES)-based transceivers.

Stratix II GX devices offer optimal signal integrity and ample design headroom. Performance at 6.375 Gbps shows excellent signal integrity, including low jitter generation and

Built-In Protocol Standards Support

Standard (Data Rate)

Feature Stratix II GX Stratix GX

PCI Express(2.5 Gbps)

PIPE-Compliant PCS Block (Version 1.1)

1

CEI 6G2

(6.375 Gbps)8b/10b Encoder/Decoder

Gigabit Ethernet(1.25 Gbps)

Gigabit Ethernet State Machine

XAUI(3.125 Gbps)

XAUI State Machine

SRIO(1.25, 2.5 & 3.125 Gbps)

8b/10b Encoder/Decoder

SONET OC-12(622 Mbps)

A1A2 Pattern Detector & Aligner

SONET OC-48(2.488 Gbps)

A1A2 or A1A1A2A2 Pattern Detector & Aligner

SD-SDI(270 Mbps)

Oversampling

HD-SDI(1.4835 Gbps or 1.485 Gbps)

Pattern Detector

SerialLite II(622 Mbps – 6.375 Gbps)

8b/10b Encoder/Decoder

Notes:1 In Stratix GX devices, receive detect, out-of-board signaling (OOBS), and electrical idle are not supported, and PIPE must be implemented in logic.

2 CEI-6G: Common Electrical Implementation 6 Gbit

Examples of Altera’s High-Speed Transceiver Features

Standard Complete Protocol Solutions

Gigabit Ethernet

Gigabit Ethernet MAC IP Development kit with HSSDC2 high-speed

connector, schematics & layout Characterization report

PCI Express PCI Express MegaCore® IP functions - Compliant, including PCI-SIG Integrators Listing - Supports x1, x4 & x8 - Endpoint Development kit with x8 edge connector & slot,

schematics & layout Characterization report Reference design

HD-SDISD-SDI

SDI IP - Full duplex interface that supports rate detec-

tion, cyclic redundancy check (CRC) & video pattern generator

Development kit with driver, cable equalizer, schematics & layout

Characterization report

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high jitter tolerance. Stratix II GX FPGAs comply with many protocol standards, providing generous margin as well as optimized transmit pre-emphasis, receive equalization, and signal integrity for even the most challenging backplanes. In addition, Stratix II GX devices feature low power consumption; for example, only 125 mW per channel at 3.125 Gbps and 225 mW per channel at 6.375 Gbps.

Stratix GX Device FamilyStratix GX devices include up to 20 full-duplex transceiver channels, each capable of operating at up to

3.1875 Gbps per channel while consuming low power. Built on the first-generation Stratix architecture, Stratix GX devices offer the same FPGA features, including TriMatrix™ memory, digital signal processing (DSP) blocks, and advanced clock management circuitry for intensive data path processing functions.

Stratix GX FPGAs integrate an optimized 3.1875-Gbps transceiver that includes customer-defined features such as 40-inch backplane drive strength capability, transmit pre-emphasis, receive equalization, channel alignment, and embedded 8b/10b encoding/decoding. In addition, Stratix GX devices contain source-synchronous differential I/O (operating at up to 1 Gbps) with circuitry that performs dynamic phase alignment (DPA).

Contact Altera TodayAltera’s Stratix II GX and Stratix GX families provide the industry’s leading transceiver solutions. For more information, visit Altera’s web site at www.altera.com/stratix2gx or www.altera.com/stratixgx.

Copyright © 2005 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. HyperTransport is a trademark of the HyperTransport Consortium. RapidIO is a trademark of the RapidIO Trade Association. All other trademarks are the property of their respective owners and may be registered in certain jurisdictions. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. GB-STXGX-4.1

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Stratix GX Device Family Overview (500 Mbps to 3.1875 Gbps)

Device Transceiver Channels

EquivalentLEs

PLLs User I/OPins

Package

EP1SGX10C 4 10,570 4 330 672-Pin FBGA

EP1SGX25C 4 25,660 4 426 672-Pin FBGA

EP1SGX10D 8 10,570 4 330 672-Pin FBGA

EP1SGX25D 8 25,660 4 426542

672-Pin FBGA, 1,020-Pin FBGA

EP1SGX40D 8 41,250 8 548 1,020-Pin FBGA

EP1SGX25F 16 25,660 4 542 1,020-Pin FBGA

EP1SGX40G 20 41,250 8 548 1,020-Pin FBGA

Stratix II GX Device Family Overview (622 Mbps to 6.375 Gbps)

Device Transceiver Channels

EquivalentLEs

PLLs User I/OPins

Package

EP2SGX30C 4 33,880 4 372 780-Pin FBGA

EP2SGX60C 4 60,440 8 364 780-Pin FBGA

EP2SGX30D 8 33,880 4 372 780-Pin FBGA

EP2SGX60D 8 60,440 8 364 780-Pin FBGA

EP2SGX60E 12 60,440 8 534 1,152-Pin FBGA

EP2SGX90E 12 90,960 8 558 1,152-Pin FBGA

EP2SGX90F 16 90,960 8 650 1,508-Pin FBGA

EP2SGX130G 20 132,540 8 734 1,508-Pin FBGA

Note: FBGA: FineLine BGA® package