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Strategy for unified d ata link Zhen-An LIU Institute of High Energy Physics

Strategy for unified data link

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Strategy for unified data link. Zhen-An LIU Institute of High Energy Physics. New Ideas on Belle II DAQ. Consideration Base HS data transmission Optical link Unified Readout Unified Data link Also trigger? Also timing? My talk on PMC/COPPER link. Trigger path suggestion to Iwasaki-san. - PowerPoint PPT Presentation

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Page 1: Strategy for unified data link

Strategy for unified data link

Zhen-An LIU

Institute of High Energy Physics

Page 2: Strategy for unified data link

New Ideas on Belle II DAQ• Consideration

Base– HS data

transmission– Optical link– Unified Readout– Unified Data link– Also trigger?– Also timing?

• My talk on PMC/COPPER link

Page 3: Strategy for unified data link

Trigger path suggestion to Iwasaki-san

• If HS data link used– RocketIO (SEDES)– Synchronization needed (per channel)– Channel Alignment needed (per system)– Pipelined processing

• Trigger latency should reserve big enough– 5 us maybe enough but conservative– 7 us in BESIII

• Trigger distribution– More time needed

Page 4: Strategy for unified data link

Scheme1 for Data link (to Copper)• Based on discussions two schemes in consideration • Scheme 1

– Detector specific readout( Gary’s board or other?)• 16 ch/optical line• Data preprocessing• Partial packaging• Data frame/protocol• Length/ch/event?• Trigger L1 driven

– Data merger• Further packaging • Necessary to save COPPER boards• Output to COPPER PMC• Data frame2

– PMC • Data mover to CPU on COPPER

Page 5: Strategy for unified data link

VMEBUS

Clock(40MHz)

Test output

Reserved

95Con

95Con

5V/3.3VBus

SwitchIDT

QS316211

OpticalFiber 9

HFBR5921L 0

HFBR5921L 9

HFBR5921L 1OpticalFiber 1

OpticalFiber 8 HFBR5921L 8

34 PinLVDS

34 PinLVDS

SN75LVDS387LVTTL-LVDS

SN75LVDS387LVTTL-LVDS

16*12 Test Pins

16 Test Pin

16 Test Pin

16 Test Pin

16 Test Pin

Power SupplyLT1764EQ-DD1.5V,2.5V,3.3V,5V1.6~2.5V Adjustable

LED Display

D(0:31)SN74

ALVTH162245

D(0:31)

SN74ALVTH162244MC100EP16FD

CDCF580180MHz

XC2VP40FF1152-6

Download circuit

1.6 GBps

/ch

Merger test module

From UnifiedReadout

To COPPERPMC Control

SignalsVia USERpins

Optical Fiber0

Page 6: Strategy for unified data link

To be decided with Scheme 1

• Clock for HS transmission• System clock• How many input ch / board?

– Data rate– Data size

• VirtexII Pro / VirtexV ?• Synch/Asych?

– Synchronized data transmission.

• Data frame

Page 7: Strategy for unified data link

Status• Hardware available

– Data source – Merger board– Test system available

• Protocol– Need FRST, Tsync sign

als from timing sys.– Need more discussion w

ith timing/readout/COPPER people

• PMC to be designed

Page 8: Strategy for unified data link

Scheme2 for Data link

• In scheme 1:– Optical transceiver inside detector( say CDC)– Question:

• Reliability not so good in BESIII– Radiation? Experiment did before design– ESD effect? Experiments under taken– Unclear yet!

• Stop machine for replacement?• Open the Detector for replacement?

– Possible solution• Optical transceiver outside detector• Merger before HS data link

Page 9: Strategy for unified data link

Scheme2 for Data link

• Scheme 2– Merger near detector – Electrical to FEE– Optical to

PMC/COPPER– Easy maintenance– SFP transceiver

Page 10: Strategy for unified data link

More discussion scheduled

• A discussion is scheduled tomorrow

• Idea from detector and FEE welcome