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IBM Research
© 2009 IBM Corporation
Storage Class Memory
Towards a disruptively low-cost solid-state non-volatile memory
Geoffrey W. BurrIBM Almaden Research Center
June 6, 2010 Short Course3:30pm
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation2
Outline Motivation
• by 2020, server-room power & space demands will be too high• evolution of hard-disk drive (HDD) storage and Flash cannot help• need a new technology – Storage Class Memory (SCM) – that combines
the benefits of a solid-state memory (high performance and robustness) the archival capabilities and low cost of conventional HDD
How could we build an SCM?• combine a scalable non-volatile memory (PCM, RRAM, STT-RAM)• with ultra-high density integration, using
micro-to-nano addressing multi-level cells 3-D stacking
Conclusion• With its combination of low-cost and high-performance,
SCM could impact much more than just the server-room...
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation3
Power & space in the server roomThe cache/memory/storage hierarchy is rapidly becoming the bottleneck for large systems.
We know how to create MIPS & MFLOPS cheaply and in abundance, but feeding them with data has become
the performance-limiting and most-expensive part of a system (in both $ and Watts).
• 5 million HDD 16,500 sq. ft. !! 22 Megawatts
Extrapolation to 2020(at 70% CGR need
2 GIOP/sec)
R. Freitas and W. Wilcke, Storage Class Memory: the next storage system technology –to appear in "Storage Technologies & Systems"
special issue of the IBM Journal of R&D.
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation4
• 21 million HDD 70,000 sq. ft. !! 93 Megawatts
(at 90% CGR need 8.4G SIO/sec)
…yet critical applications are also undergoing a paradigm shift
Compute-centricparadigm
Typical Examples:
Bottleneck:
Main Focus: Analyze petabytes of data
Storage & I/OSearch and Mining
Analyses of social/terrorist networks
Sensor network processing
Digital media creation/transmission
Environmental & economic modeling
Data-centricparadigm
Solve differential equations
CPU / MemoryComputational Fluid Dynamics
Finite Element Analysis
Multi-body Simulations
Extrapolationto 2020
(at 90% CGR need 1.7 PB/sec)
• 5.6 million HDD 19,000 sq. ft. !! 25 Megawatts[Freitas:2008]
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation5
Problem: The access-time gap between memory & storage
ON-chipmemory
OFF-chipmemory
ON-linestorage
OFF-linestorage
Decreasingco$t
100
108
103
104
105
106
107
109
1010
Get data from DRAM/SCM (60ns)10
1 CPU operations (1ns)Get data from L2 cache (10ns)
Read or write to DISK (5ms)
Get data from TAPE (40s)
Write to FLASH, random (1ms)
Read a FLASH device (20 us)
...(in human perspective)(T x 109)second
minute
hour
day
week
month
year
decade
century
millenium
Access time...(in ns)
• Modern computer systems have to be carefully designed to hide this gap
• Lots of server-room power spent to keep disk-drives spinning
• With no on-chip storage, sensor (& other) data must be passed deep into the network
• Slow searching through huge databases because all the data must come off of disk first
...what if we could build a technology that could bridge this gap?
Memory/storage gap
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation6
CPU RAM DISK TAPEFLASH
SSD2009
CPU RAM DISK TAPE1980
ArchivalActive StorageMemoryLogic
2013+ CPU SCMR
AM TAPE...DISK
Storage Class Memory A solid-state memory that blurs the boundariesbetween storage and memory by being
low-cost, fast, and non-volatile.
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation7
2 4 6 8 1010ns
100ns
1s
10s
100s
Rea
d La
tenc
y
Cell size [F2]
NAND
DRAM
Storage-type vs. memory-type Storage Class Memory
(Write) EnduranceCost/bit
Speed(Latency & Bandwidth)
Power!
Memory-typeuses
Storage-typeuses
low co$t
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation8
Storage Class Memory
SCM system requirements for Memory (Storage) apps• No more than 3-5x the Cost of enterprise HDD (< $1 per GB in 2012)
• <200nsec (<1sec) Read/Write/Erase time
• >100,000 Read I/O operations per second
• >1GB/sec (>100MB/sec)
• Lifetime of 109 – 1012 write/erase cycles
• 10x lower power than enterprise HDD
A solid-state memory that blurs the boundariesbetween storage and memory by being
low-cost, fast, and non-volatile.
(Write)Endurance
Cost/bit
Speed
Storage-typeuses
Memory-typeuses
Power!
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation9
SCM devicerequirements
Desired attributes• high performance (>1 GB/sec data rate, < 200nsec access time)
• low active & standby power (100mW ON power, 1mW standby)
• high read/write endurance (109 – 1012 cycles)
• non-volatility• compatible
with existing technologies• continuously scalable• lowest cost per bit (target: cost of Enterprise HDD)
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation10
Can HDD & Flash improve enough to help?
Flash• slow read/write access time (yet processors keep getting faster)
• low write endurance (<106 ) (need >109 for continuously streaming data)
• block architecture• scalability beyond the end of this decade?
Magnetic hard-disk drives (HDD)• bandwidth issues (hidden with parallelism, but at power/space cost)
• slow access time (not improving, hard to hide with caching tricks)
• reliability (newest drives are less reliable data losses inevitable)
• power consumption (must keep drives spinning to avoid even longer access times)
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation11
History of HDD is based on Areal Density Growth
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation12
Future of HDDHigher densities through
• perpendicular recording
• patterned media
Wikipedia
Jul 2008 610 Gb/in2 ~4 TB
www.hitachigst.com/hdd/research/images/pm images/conventional_pattern_media.pdf
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation13
Disk Drive Maximum Sustained Data Rate
1
10
100
1000
1985 1990 1995 2000 2005 2010
Date Available
MB
/s
Date1985 1990 1995 2000 2005 2010
Bandwidth[MB/s]
1000
100
10
1
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Disk Drive Latency
0
1
2
3
4
5
6
7
8
1985 1990 1995 2000 2005 2010
Date
Latency[ms]
Bandwidth Problem is getting much harder to hide with parallelism Access Time Problem is also not improving with caching tricks Power/Space/Performance Cost
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Can HDD & Flash improve enough to help?
Flash• slow read/write access time (yet processors keep getting faster)
• low write endurance (<106 ) (need >109 for continuously streaming data)
• block architecture• scalability beyond the end of this decade? (probably…)
Magnetic hard-disk drives (HDD)• bandwidth issues (hidden with parallelism, but at power/space cost)
• slow access time (not improving, hard to hide with caching tricks)
• reliability (newest drives are less reliable data losses inevitable)
• power consumption (must keep drives spinning to avoid even longer access times)
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation16
Cost competition between IC, magnetic and optical
devices comes down toeffective areal density.
[Fontana:2004, web searches]
Density is key
2F 2F
101.5210 nm (λ/2)Blue Ray
874.043 nm (half pitch)NAND (1 bit)
1752.043 nm (half pitch)NAND (2 bit)
506.045 nm (half pitch)DRAM
2501.050 nm (MR width)Hard Disk
Density(Gbit /sq. in)
Area(F²)
Critical feature-size FDevice
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation17
What is Flash?
• Based on MOS transistor
• Transistor gate is redesigned
• Charge is placed or removed near the “gate”
• The threshold voltage Vth of the transistor is shifted by the presence of this charge
• The threshold Voltage shift detection enables non-volatile memory function.
source drain
gate
source drain
control gate
source drain
e- e- e- e- e-
control gate
oxide
FloatingGate e- e-
FlashMemory
“0”
FlashMemory
“1”
FloatingGate
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MultimediaProgram codeApplications$14.2B$8BMarket Size (2007)
2ms750msecErase8MB/sec<0.5MB/secWrite
18-25 MB/s100 MB/sRead
2 F2
(4 F2 physical x 2-bit MLC)9-11 F2Cell Size
NANDNOR
FLASH memory types and application
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Tunnel oxide thickness in Floating-gate Flash is no longer practically scalable
Published NAND
ITRS 2003 CMOS Logic
Published CMOS Logic
ITRS 2003 NAND ITRS 2003
NOR
Flash – below the 100nm technology node
Source: Chung Lam, IBM
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Can Flash improve enough to help?
Floating Gate<40nm???
SONOSCharge trappingin SiN trap layer
TaNOSCharge trapping
in novel trap layercoupled with
a metal-gate (TaN)
Technology Node: 40nm 30nm 20nm
oxide oxide/nitride/oxide TaN
Main thrust is to continue scaling yet maintain the same performance and write endurance specifications…
<32nm???
<22nm???
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NAND Scaling Road Map
Chip Density, GBytes
Evolution?? Migrating to Semi-spherical
TANOS memory cell 2009 Migrating to 3-bit cell in 2010 Migrating to 4-bit cell in 2013 Migrating to 450mm wafer
size in 2015 Migrating to 3D Surround-
Gate Cell in 2017Source: Chung Lam, IBM
Minimum Feature Size, nm
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Vertically stack “horizontal-path” NAND [Park IEEE JSSC 2009]
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[Jang VLSI 2009]
“Vertical-path” NAND
[Maeda, Katsumata VLSI 2009]
Poly-silicon+Charge-trap
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3-D NAND
EffectiveDensity
Lower than NAND(pass
transistors, vias)
Lower than NAND(vias on
periphery)
Limit unknown-demonstration at very relaxed
pitch
Double-gateTFT
[Walker IEEE TED 2009]
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More IOPs means many more CPU cycles spent preparing IO requests
Hidden assumptions in software stack designed for HDD but fail badly for Flash “Seeks are slow, thus there’s plenty of time for garbage collection”
Difficult to tune Flash usage (“when to erase blocks”) to an apps’ particular needs/usage scheme
Perfect wear-leveling + RAID leads toa disaster when all SSDs wear out simultaneously
Application choices can lead to either wise (or foolish) use of the limited device lifetime
Tuning systems to use Flash-based SSDs
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation26
For more information (on HDD & Flash)
• E. Grochowski and R. D. Halem, IBM Systems Journal, 42(2), 338-346 (2003)..• R. J. T. Morris and B. J. Truskowski, IBM Systems Journal, 42(2), 205-217 (2003).• R. E. Fontana and S. R. Hetzler, J. Appl. Phys., 99(8), 08N902 (2006).• E. Pinheiro, W.-D. Weber, and L. A. Barroso, FAST’07 (2007).
HDD
• S. Lai, IBM J. Res. Dev., 52(4/5), 529 (2008).• R. Bez, E. Camerlenghi, et. al., Proceedings of the IEEE, 91(4), 489-502 (2003).• G. Campardo, M. Scotti, et. al., Proceedings of the IEEE, 91(4), 523-536 (2003).• P. Cappelletti, R. Bez, et. al., IEDM Technical Digest, 489-492 (2004).• A. Fazio, MRS Bulletin, 29(11), 814-817 (2004).• K. Kim and J. Choi, Proc. Non-Volatile Semiconductor Memory Workshop, 9-11 (2006).• M. Noguchi, T. Yaegashi, et. al., IEDM Technical Digest, 17.1 (2007).• J. Jang, H.-S. Kim, et. al., Symp. VLSI Technology, T10A-4, (2009).• R. Katsumata, M. Kito, et. al., Symp. VLSI Technology, T7-1, (2009).• J. Kim, A. J. Hong, et. al., Symp. VLSI Technology, T10A-1, (2009).• W. Kim, S. Choi, et. al., Symp. VLSI Technology, T10A-2, (2009).• T. Maeda, K. Itagaki, et. al., Symp. VLSI Technology, C3-1, (2009).• K. T. Park, M. Kang, et. al., IEEE J. Solid-State Circuits, 44(1), 208-216, (2009).• A. J. Walker, IEEE Trans. Electron Devices, 56(11), 2703-2710, (2009).• J. G. Yun, J. D. Lee, and B. G. Park, IETE Technical Review, 26(4), 247-257, (2009).• Y. Kim, I. H. Park, et. al., IEEE Transactions On Nanotechnology, 9(1), 70-77, (2010).• CMRR Non-Volatile Memory Workshop, April 2010,
cmrr.ucsd.edu/education/workshops/GeneralInformation.htm• L. M. Grupp, A. M. Caulfield, et. al., “Characterizing Flash Memory: Anomalies, Observations, and Applications,” April 12, 2010• C. Trinh, N. Shibata, et. al., “A 7.8MB/s 64Gb 4-Bit/Cell NAND Flash Memory on 43nm CMOS Technology,”April 12, 2010,
Flash
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation27
Can HDD & Flash improve enough to help?
Flash• slow read/write access time (yet processors keep getting faster)
• low write endurance (<106 ) (need >109 for continuously streaming data)
• block architecture• scalability beyond the end of this decade? (probably…)
Magnetic hard-disk drives (HDD)• bandwidth issues (hidden with parallelism, but at power/space cost)
• slow access time (not improving, hard to hide with caching tricks)
• reliability (newest drives are less reliable data losses inevitable)
• power consumption (must keep drives spinning to avoid even longer access times)
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation28
Landscape of existing technologies
Performance
Co
st
NOR FLASH
NAND FLASH
DRAM
SRAM
HDD ?
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation29
Memory/storage landscape
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation30
Tie-in to IITC many of these new NVM candidates are explicitly developed as Back-End-Of-the-Line (BEOL) technologies can be fabricated among the metal layers must be process-compatible with BEOL temperature budgets often placed in back-end even when silicon access device is used
cost always an issue, so # of masks required a strong consideration
with density improvements from lithographic innovation becoming harder to come by, future scaling maps now increasingly discuss 3D-in-the-BEOL for both Flash and new NVM candidates
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation31
Research interest Papers presented at• Symposium on VLSI Technology/Circuits• IEDM (Int. Electron Devices Meeting)
Flashnanocrystal FlashSONOS FlashFeRAMMRAMPCramRRAMsolid electrolyteorganic
Year
0
10
20
30
40
50
60
Num
ber o
f pap
ers
2001 2002 2003 2004 2005 2006 2007 2008 2009
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation32
Improved Flash improvements would be required in write endurance & speed
FeRAM – commercial product but difficult to scale!
MRAM – commercial product, also difficult to scale! STT-RAM – pass current through MTJ for lower currents Racetrack memory – new concept w/ promise, still at point of
RRAM (Resistive RAM) Organic & polymer memory Memristor Solid Electrolyte
PC-RAM (Phase-change RAM)
early basic physics research
Candidate device technologies
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation33
Improved Flash • Given an unpleasant tradeoff between scaling, speed, and endurance, designers are choosing to hold speed & endurance constant to keep the scaling going…
[GruppCMRR-NVM 2010]
[TrinhCMRR-NVM 2010]
Cell-to-Cell Coupling
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation34
Improved Flash improvements would be required in write endurance & speed
FeRAM – commercial product but difficult to scale!
MRAM – commercial product, also difficult to scale! STT-RAM – pass current through MTJ for lower currents Racetrack memory – new concept w/ promise, still at point of
RRAM (Resistive RAM) Organic & polymer memory Memristor Solid Electrolyte
PC-RAM (Phase-change RAM)
early basic physics research
Candidate device technologies
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation35
FeRAM (Ferroelectric RAM)
metallic electrodes
ferroelectric materialsuch as
lead zirconate titanate(Pb(ZrxTi1-x)O) or PZT
• perovskites (ABO3) = 1 family of FE materials
• destructive read forces need for high write endurance
• inherently fast, low-power, low-voltage
• first demonstrations ~1988
need select transistor –“half-select” perturbs
Coercivevoltage
Saturation chargeRemanent
charge
Qr
Qs
-Qs
-Qr
VC
[Sheikholeslami:2000]
+
-+
-
+
-+
-
+
-
+
-
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation36
FeRAM progress
• Commercially available (Playstation 2), mostly as embedded memory
[Hong:2007]
• Lots of attention in 1998-2003 timeframe
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation37
FeRAM difficulties• Signal V = transfer of charge Qr ~ 2 Pr Area onto bitline capacitance Cb
• scaling to smaller devices means lower signal !!• need material with large remanent polarization Pr
• tradeoff speed for signal with Cb
• Forces more complex integration schemes to keep effective area large
“Strapped”
“Stacked”
“3-D”
Materials difficult to etch vertically – forces guard
bands and thus less area
[Kim:2006]
> 30 F2
10 - 30 F2
< 10 F2
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation38
FeRAM difficulties• Many reliability & processing difficulties to overcome…
• Change FE material ( PZT)For crystalline FE material
High temperatureprocessing
• Change FE material (PZT SBT)Stored polarization is lost over time
retention
• Change FE material ( PZT)∝ voltage signalinsufficient Pr
• Eliminate defects introduced during fabrication by hydrogen
• Change FE material (PZT SBT)
a device left in one state tends to favor that polarization, causing hysteresis loop to shift
imprint
• Change electrodes from metals to metal-oxides
• Change FE material (PZT SBT)
remanent polarization Prdecreases with cycling
fatigue
SBT = SrBi2Ta2O9strontium bismuth tantalate
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation39
Alternative FeRAM concepts• 2T-2C concept – twice the signal but also twice the area
• Chain-FeRAM – improves signal but decreases speed, only minor density improvement
[Takashima:1998]
[Kim:2006]
• FeFET – perhaps more scalable but requires integration onto silicon and tends to sacrifice the non-volatility
[Miller:1992]
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation40
Improved Flash improvements would be required in write endurance & speed
FeRAM – commercial product but difficult to scale!
MRAM – commercial product, also difficult to scale! STT-RAM – pass current through MTJ for lower currents Racetrack memory – new concept w/ promise, still at point of
RRAM (Resistive RAM) Organic & polymer memory Memristor Solid Electrolyte
PC-RAM (Phase-change RAM)
early basic physics research
Candidate device technologies
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation41
MRAM (Magnetic RAM)
[Gallagher:2006]• inherently fast write speed• straightforward placement in the CMOS back-end• very high endurance (no known wear-out mechanism)• write by simply passing current through two nearby wires
(superimposed magnetic field exceeds a write threshold)(need transistor upon reading for good SNR)
Simple MTJ(magnetic tunnel
junction)MTJ with
pinned layer
MTJ withpinned “synthetic antiferromagnet”
ToggleMRAM
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation42
MRAM (Magnetic RAM)
[Gallagher:2006]
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation43
Progress in MRAM
[Gallagher:2006]
[Durlam:2007]
• lots of progress 2001-2004
• commercially available• focus on embedded memory
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation44
Problems with MRAM
[Gallagher:2006]
• “Half-select problem” solved by Toggle-MRAM, but introduces a read-before-write
[Worledge:2006]
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation45
Problems with MRAM• Write currents were very high – did not scale well
electromigration even at 180nm node
• Possible solutions• heat MTJ to reduce required current
• use “spin-torque” effect rotate magnetization by passing current through the cell now could have a wear-out mechanism (thin tunneling layers)
must insure read is non-perturbative
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation46
[OnoIEDM 2009]
[Driskill-SmithCMRR NVMW 2010]
Strengths: • Fast & low-power• potential for high endurance• BEOL compatible
embedded memory
• Low R-contrast tight margins to avoid read disturb & breakdown!
• Thermal stability bad – worse w/ scaling• Current densities almost as high as PCM• Probabilistic write at fast times
Worries:
Spin-Torque Transfer RAM
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation47
Magnetic Racetrack Memory a 3-D shift register• Data stored as pattern of magnetic domains in long nanowire or “racetrack” of magnetic material.
• Current pulses move domains along racetrack
• Use deep trench to get many (10-100) bits per 4F2
IBM trench DRAM
Magnetic Race Track MemoryS. Parkin (IBM), US patents
6,834,005 (2004) & 6,898,132 (2005)
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Magnetic Racetrack Memory• Need deep trench with notches to “pin”domains
• Need sensitive sensors to “read” presence of domains
• Must insure a moderate current pulse moves every domain one and only one notch
• Basic physics of current-induced domain motion being investigated
Promise (10-100 bits/F2) is enormous…
but we’re still working on our basic understanding of the physical phenomena…
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For more information (on FeRAM & MRAM)
• A. Sheikholeslami and P. G. Gulak, Proc. IEEE, 88, No. 5, 667-689 (2000).• Y.K. Hong, D.J. Jung, et. al., Symp. VLSI Technology, 230-231 (2007).• K. Kim and S. Lee, J. Appl. Phys., 100, No. 5, 051604 (2006).• N. Setter, D. Damjanovic, et. al., J. Appl. Phys., 100(5), 051606 (2006).• D. Takashima and I. Kunishima, IEEE J. Solid-State Circ., 33, No. 5, 787-792 (1998).• S. L. Miller and P. J. McWhorter, J. Appl. Phys., 72(12), 5999-6010 (1992).• T. P. Ma and J. P. Han, IEEE Elect. Dev. Lett., 23, No. 7, 386-388 (2002).
FeRAM
• R. E. Fontana and S. R. Hetzler, J. Appl. Phys., 99(8), 08N902, (2006).• W. J. Gallagher and S. S. P. Parkin, IBM J. Res. Dev. 50(1), 5-23, (2006).• M. Durlam, Y. Chung, et. al., ICICDT Tech. Dig., 1-4, (2007).• D. C. Worledge, IBM J. Res. Dev. 50(1), 69-79, (2006).• S.S.P. Parkin, IEDM Tech. Dig., 903-906 (2004).• L. Thomas, M. Hayashi, et. al., Science, 315(5818), 1553-1556 (2007).• A. Driskill-Smith, “Latest Advances and Future Prospects of STT-RAM,” CMRR NVMW, April 12, 2010• K. Ono, T. Kawahara, et. al., IEDM Technical Digest, 9.3, (2009).• C. J. Lin, S. H. Kang, et. al., IEDM Technical Digest, 11.6, (2009).
MRAM
G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, "An overview of candidate device technologies for Storage-Class Memory,"
IBM Journal of Research and Development, 52(4/5), 449-464 (2008).
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation50
Improved Flash improvements would be required in write endurance & speed
FeRAM – commercial product but difficult to scale!
MRAM – commercial product, also difficult to scale! STT-RAM – pass current through MTJ for lower currents Racetrack memory – new concept w/ promise, still at point of
RRAM (Resistive RAM) Organic & polymer memory Memristor Solid Electrolyte
PC-RAM (Phase-change RAM)
early basic physics research
Candidate device technologies
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation51
RRAM (Resistive RAM)• Numerous examples of materials showing
hysteretic behavior in their I-V curves
• Mechanisms not completely understood, butmajor materials classes include
• metal nanoparticles(?) in organics• could they survive high processing temperatures?
• metallic filaments in solid electrolytes
• oxygen vacancies in transition-metal oxides• tremendous progress over last few years Integrated demos with <1us write, 1e6 endurance
in ~50nm diameter devices• things I’d worry about if I worked on RRAM:
• need for higher-voltage forming step?• “switching reproducibility”?• bipolar operation/read-disturb vs. cross-point diode operation?• voltage-time dilemma (switch in 100ns, can it still retain for 10yrs?)
[Karg:2008]
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Memristor
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation53
Memristor ~50x50nmdevices
[KwonNature Nanotech
2010]
[WilliamsIEEE Spectrum
2008]
[NickelCMRR NVM
2010]
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation54
Memristor
Can nearly anything that involves a state variable w
become a memristor...?
Note time-range chosen for simulations,and the required switching current (power)
[PickettJAP 2009]
(Large & small devices said to exhibit similar
switching characteristics)
[BorghettiNature 2010]
[StrukovNature 2008]
Memristoras “logic”
device
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation55
WOx (unipolar)[Chien IEEE
EDL 2010]
[TsengIEDM 2009]
TiN/TiON (unipolar)Oxide-based RRAM
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation56
Solid Electrolyte
• Ag and/or Cu-doped GexSe1-x, GexS1-x or GexTe1-x
• Cu-doped MoOx• Cu-doped WOx• RbAg4I5 system
• Program and erase at very low voltages & currents
• High speed• Large ON/OFF contrast• Good endurance demonstrated• Integrated cells demonstrated
Advantages
[Kozicki:2005]
ONstate
OFFstate
Issues• Retention • Over-writing of the filament• Sensitivity to processing temperatures
(for GeSe, < 200oC)• Fab-unfriendly materials (Ag)
Resistance contrast by forming a metallic filament through insulatorsandwiched between an inert cathode & an oxidizable anode.
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Storage Class Memory @ IBM Almaden © 2010 IBM Corporation57
Solid Electrolyte “Memristor” RRAM100x100nm devices
[KimAPL 2010]
+5V, -3.5V 50usProgram at 100nA
Read at 0.5VEndurance for 1uA = 2.4e7
[JoNanoletters
2010]
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Unity semiconductor RRAM + diode [ChevallierISSCC 2010]
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation59
Unity semiconductor RRAM + diode
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For more information (on RRAM & SE)G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy,
"An overview of candidate device technologies for Storage-Class Memory," IBM Journal of Research and Development, 52(4/5), 449-464 (2008).
RRAM • J. C. Scott and L. D. Bozano, Adv. Mat., 19, 1452-1463 (2007).• Y. Hosoi, Y. Tamai, et. al., IEDM Tech. Dig., 30.7.1-4 (2006).• D. Lee, D.-J. Seong, et. al., IEDM Tech. Dig., 30.8.1-4 (2006).• S. F. Karg, G. I. Meijer, et. al., IBM J. Res. Dev., 52(4/5), 481-492 (2008).• D. B. Strukov, et. al., Nature, 453, 80(7191), 80-83 (2008).• R. S. Williams, IEEE Spectrum, Dec 2008. • D. B. Strukov, G. S. Snider, et. al., Nature, 453 (7191), 80-83, (2008).• J. Nickel, "Memristors: materials and mechanisms," CMRR NVM workshop, April 12, 2010.• M. D. Pickett, D. B. Strukov, et. al., J. Appl. Phys., 106(7), 074508, (2009).• D.-H. Kwon, K. M. Kim, et. al., Nature Nanotech., 5(2), 148-153, (2010). • Y. H. Tseng, C.-E. Huang, et. al., IEDM Tech. Dig., paper 5.6, (2009). • W. C. Chien, Y. C. Chen, et. al., IEEE Electron Dev. Lett., 31(2), 126-128, (2010). • H. Schroeder, V. V. Zhirnov, et. al., J. Appl. Phys., 107(5), 054517, (2010).
SE • M. N. Kozicki, M. Park, and M. Mitkova, IEEE Trans. Nanotech., 4(3), 331-338 (2005).• M.N. Kozicki, M. Balakrishnan, et. al., Proc. IEEE NVSM Workshop, 83-89 (2005).• M. Kund, G. Beitel, et. al., IEDM Tech. Dig., 754-757 (2005).• P. Schrögmeier, M. Angerbauer, et. al., Symp. VLSI Circ., 186-187 (2007).• K.-H. Kim, S. H. Jo, S. Gaba, and W. Lu, Applied Physics Letters, 96, 053106, (2010).• S. H. Jo, T. Chang, et. al., NanoLetters, 10(4), 1297-1301, (2010).• C. J. Chevallier, C. H. Siau, et. al., ISSCC 2010, page 14.3, (2010).
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Improved Flash improvements would be required in write endurance & speed
FeRAM – commercial product but difficult to scale!
MRAM – commercial product, also difficult to scale! STT-RAM – pass current through MTJ for lower currents Racetrack memory – new concept w/ promise, still at point of
RRAM (Resistive RAM) Organic & polymer memory Memristor Solid Electrolyte
PC-RAM (Phase-change RAM)
early basic physics research
Candidate device technologies
IBM Research
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History of Phase-change memory
[Neale:2001]
• late 1960’s – Ovshinsky shows reversible electrical switching indisordered semiconductors
• early 1970’s – much research on mechanisms, but everything was too slow!
Ele
ctric
al c
ondu
ctiv
ity
Crystalline phaseLow resistanceHigh reflectivity
Amorphous phaseHigh resistanceLow reflectivity
[Wuttig:2007]
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History of Phase-change memory
[Ohta:2001]
[Wuttig:2007]
• late-1990’s and on –return to PC-RAM with fast materials!
• late 80’s – 90’s – Fast phase-change materials discovered & optimized for re-writeable optical storage
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Phase-changeRAM
Access device(transistor, diode)
PCRAM“programmable
resistor”
Bit-line
Word-line
temperature
time
Tmelt
Tcryst
“RESET” pulse
“SET”pulse
VoltagePotential headache: High power/current affects scaling!
Potential headache: If crystallization is slow affects performance!
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“SET” stateLOW resistance “RESET” state
HIGH resistance
timetem
pera
ture Tmelt
Tcryst
“RESET” pulseHow a phase-change cell works
S. Lai, Intel,IEDM 2003.
Heat to melting...
& quench rapidly
crystallinestate
amorphousstate
‘heater’wire
access device
“Mushroom” cell
“SET”pulse
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“SET” stateLOW resistance
“RESET” stateHIGH resistance
timetem
pera
ture Tmelt
Tcryst
“RESET” pulseHow a phase-change cell works
S. Lai, Intel,IEDM 2003.
crystallinestate
amorphousstate
‘heater’wire
access device
Vth
Hold at slightly undermelting duringrecrystallization
Filamentbroadens,
then heats up
“SET”pulse
Field-inducedelectricalbreakdown starts at Vth
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“SET” stateLOW resistance
“RESET” stateHIGH resistance
timetem
pera
ture Tmelt
Tcryst
“RESET” pulseHow a phase-change cell works
S. Lai, Intel,IEDM 2003.
crystallinestate
amorphousstate
‘heater’wire
access device
• Keeping the RESET current low• Multi-level cells (for >1bit / cell)• Is the technology scalable?
“SET”pulse
Issues for phase-change memory
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Electrical “breakdown” in PC-RAM devices
[Ha:2003]
• 70’s – Study of electrical breakdown – “memory switching’ vs. “threshold switching”
• “Threshold voltage” observed to be a function of the “size” of the amorphous plug…
• Recent studies – electrical resistivity drops rapidly with electric field…
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Phase-change materials
[Chen:2006]
• Two types of materials: “nucleation-dominated” vs. “growth-dominated”
AFM takenafter optical
experiments on “as-deposited”
amorphous material…
Nucleation-dominatedMany crystalline nuclei start
growing inside each optical spot
Growth-dominatedAfter a long incubation time where nothing happens, one nuclei then gets started and rapidly grows to
cover the entire optical spot
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Phase-change materials
[Chen:2006]
We want a material that…
…retains data at moderate temperature…
yet switches rapidly at high temperature.
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Prototype memory device with ultra-thin (3nm) films – Dec 2006
W defined by lithographyH by thin-film deposition
PCM scales to small dimensions
3nm * 20nm 60nm2
≈ Flash roadmap for 2013 phase-change scales
PCM is very fast
[Bruns, APL 2009]
1nspulses
[ChenIEDM 2006]
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PCM data retention
PCM thermal crosstalk: considered tobe a second-order effect (no empirical observations yet!)
BEC
TEC
[Russo:2006IEEE Trans. Electron Devices]
• Crystallization is combination of nucleation & growth• Growth velocities at ~200oC are 10nm/sec
at ~400oC are 10m/sec• Popular material GST (Ge2Sb2Te5) is nucleation-dominated
- helps increase switching speed- data loss by nucleation within amorphous plug
• Large-array studies shown presence of low-probability “unlucky” early-fail cells
[Gleixner:2007 IRPS]
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PCM endurance
[Lai:2003IEDM]
[Gleixner:2007NVSMW]
• Stuck RESET – void/delamination at critical electrode-PCM interface
• Stuck SET – required switching point evolves over time due to bias-driven elemental segregation
Critically important to minimize time-spent-melted SET, intermediate-R MLC operations should avoid melting if possible
Very little known about how non-GST materials behave…
Flash endurance
Much better than Flash… but nowhere near SRAM & DRAM
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• Forces sublithographic patterning• CD error strong variability!• Processing sensitivity to etch fill high-aspect ratio vias with CVD less amenable to changing materials
High RESET current
5 10 20 30 50 70
10uA
100uA
1mA
1A/nm
8 16 22 32 45 65
Technology node F [nm]
PCM CD [nm]
AlmadenPCMpore
devices
ITRS roadmap
3A/nm
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Prototype memory devices
W defined by lithographyH by thin-film deposition
PCM @ IBM Almaden
3nm * 20nm 60nm2
≈ Flash roadmap for 2013 phase-change scales
[ChenIEDM 2006] Phase-change materials work
[B. S. LeeScience 2009]
Device & materials modeling
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Axon
Dendrite
synapses...Mimic biological
Dendrite
Neuron 15m
Axon
Dendrite
Axon
Neuron 2
5m
...in CMOS hardware...
PCM “pore” device
...using PCMmemorydevices
PCM as a CMOS-compatible synapse
Ultra-scaled PCM pore cells
PCM @ IBM Almaden
Improvements to PCM Drift of intermediate resistances Interplay between stoichiometry changes & endurance (+ other effects)
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Strengths of PCM
But success will require ultra-high density
PCM…
• low co$t requires high density
• NAND Flash is at 4F2/3 need 4F2 footprint
+ MLC + 3D
…offers huge resistance contrast…still works well at tiny dimensions…is inherently fast (easily < 300ns)…is not strongly affected by thermal xtalk…can support 10yr retention, certainly at 85oC…has 10,000x better endurance than FLASH
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For more information (on PCRAM)
• S. R. Ovshinsky, Phys. Rev. Lett., 21(20), 1450 (1968).• D. Adler, M. S. Shur, et. al., J. Appl. Phys., 51(6), 3289-3309 (1980).• R. Neale, Electronic Engineering, 73(891), 67-, (2001).• T. Ohta, K. Nagata, et. al., IEEE Trans. Magn., 34(2), 426-431 (1998).• T. Ohta, J. Optoelectr. Adv. Mat., 3(3), 609-626 (2001).• S. Lai, IEDM Technical Digest, 10.1.1-10.1.4, (2003).• A. Pirovano, A. L. Lacaita, et. al., IEDM Tech. Dig., 29.6.1-29.6.4, (2003).• A. Pirovano, A. Redaelli, et. al., IEEE Trans. Dev. Mat. Reliability, 4(3), 422-427, (2004).• A. Pirovano, A. L. Lacaita, et. al., IEEE Trans. Electr. Dev., 51(3), 452-459 (2004).• Y. C. Chen, C. T. Rettner, et. al., IEDM Tech. Dig., S30P3, (2006).• J.H. Oh, J.H. Park, et. al., IEDM Tech. Dig., 2.6, (2006).• S. Raoux, C. T. Rettner, et. al., EPCOS 2006, (2006).• M. Breitwisch, T. Nirschl, et. al., Symp. VLSI Tech., 100-101, (2007).• T. Nirschl, J. B. Philipp, et. al., IEDM Technical Digest, 17.5, (2007).• J.I. Lee, H. Park, Symp. VLSI Tech., 102-103 (2007).• S.-H. Lee, Y. Jung, and R. Agarwal, Nature Nanotech., 2(10), 626-630 (2007).• D. H. Kim, F. Merget, et. al., J. Appl. Phys., 101(6), 064512 (2007).• M. Wuttig and N. Yamada, Nature Materials, 6(11), 824-832 (2007).
PCRAM
S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y. Chen, R. M. Shelby,M. Salinga, D. Krebs, S. Chen, H. Lung, and C. H. Lam, "Phase-change random access memory —
a scalable technology," IBM Journal of Research and Development, 52(4/5), 465-480 (2008).
G. W. Burr, M. J. Breitwisch, M. Franceschini, D. Garetto, K. Gopalakrishnan, B. Jackson, B. Kurdi, C. Lam, L. A. Lastras, A. Padilla, B. Rajendran, S. Raoux, and R. Shenoy, "Phase change memory
technology," Journal of Vacuum Science & Technology B, 28(2), 223-262, (2010).
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Outline Motivation
by 2020, server-room power & space demands will be too high evolution of hard-disk drive (HDD) storage and Flash cannot help need a new technology – Storage Class Memory (SCM) – that combines
the benefits of a solid-state memory (high performance and robustness) with the archival capabilities and low cost of conventional HDD
How could we build an SCM? combine a scalable non-volatile memory (Phase-change memory)• with ultra-high density integration, using
micro-to-nano addressing multi-level cells 3-D stacking
IBM Research
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Improved Flash improvements would be required in write endurance & speed
FeRAM – commercial product but difficult to scale!
MRAM – commercial product, also difficult to scale! STT-RAM – pass current through MTJ for lower currents Racetrack memory – new concept w/ promise, still at point of
RRAM (Resistive RAM) Organic & polymer memory Memristor Solid Electrolyte
PC-RAM (Phase-change RAM)
early basic physics research
Candidate device technologies
IBM Research
Storage Class Memory @ IBM Almaden © 2010 IBM Corporation81
Cost structure of silicon-based technology
Co$t determined by
cost per wafer
# of dies/wafer
memory area per die [sq. m]
memory density[bits per 4F2]
patterning density[sq. m per 4F2]
Chart courtesy of Dr. Chung Lam, IBM Researchupdated version of plot from 2008 IBM Journal R&D article
$1 / GB
$10 / GB
$100 / GB
$1k / GB
$10k / GB
$100k / GB
$0.10 / GB
$0.01 / GB
NAND
DesktopHDD
DRAM
1990 1995 2000 2005 2010 2015
EnterpriseHDD
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Need a 10x boost in density BEYOND Flash!
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2F 2Fstartingfrom standard4F2 …
…add N 1-Dsub-lithographic“fins” (N2 with 2-D)
…go to 3-D with L layers
Paths to ultra-high density memory
…store M bits/cell with 2M multiple levels
83
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Sub-lithographic addressing• Push beyond the lithography
roadmap to patterna dense memory
• Must find a scheme to connectthe surrounding micro-circuitry tothe dense nano-array
• But nano-pattern has more complexity than just lines & spaces
[Gopalakrishnan:2005 IEDM]
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MLC (Multi-Level Cells)• Write and read
multiple analog voltages
higher density atsame fabrication difficulty
• Logarithm is not your friend:• 4 levels for 2 bits • 8 levels for 3 bits• 16 levels for 4 bits
• An iterative write scheme trades off performance for density but useful to minimize resistance variability
• Coding & signal processing can help
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• Direct write NOT sufficiently accurate
• Various schemes for iterative write
• Iterative write works, but• latency, endurance impact?• errors despite fixed # of iterations?
MLC (Multi-level cells)
10x10 test array
Single write
Iterative write
[Nirschl:2007 IEDM
[MittelholzerICC 2009]
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[Kang:2008 VLSI]Achilles heel for MLC Drift
• Resistance of amorphous phase increases as t appears to affect intermediate states too
• Device-to-device variations in coefficient • Possible materials and/or device solutions under investigation
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3-D stacking• Stack multiple layers of memory
above the silicon in the CMOS back-end
• NOT the same as 3-D packagingof multiple wafers requiringelectrical vias through-silicon
• Issues with temperature budgets, yield, and fab-cycle-time
• Still need access device within the back-end• re-grow single-crystal silicon (hard!)• use a polysilicon diode (but need good isolation & high current densities)• get diode functionality somehow else (nanowires?)
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3-D stacking
[Tanaka:2007]
• 3-D anti-fuse(Matrix semiconductor)
• 3-D Flash (Toshiba)
[Li:2004]
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3-D stacking of PCMIntel/Numonyx: use 2nd amorphous
PCM-like material as threshold switch
[KauIEDM 2009]
IBM Almaden: PCM-capable access device to appear in VLSI Technology Symposium, June 2010
• similar material to PCM• simply stack on PCM
• readout by breakdown, so read-reinforce SET, butdestructive read of MLC?
• high read-currents bandwidth?
• half-select leakage? (linear plots?)
but…
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Interplay between NVM and back-end interconnect• move to non-silicon access devices allows advent of 3D memory in the BEOL, using one or more of
• RRAM• STT-RAM • polysilicon and/or charge-trap Flash• PCM
• NVM candidates with significant switching currents can lead to cross-array problems with undesired voltage drops within the bitlines & wordlines
• unrelenting drive for high density leads to desire for much tighter pitches than usual at levels high up within the back-end
• memory is regular, uses a small set of critical repeating patterns, and is obsessed with cost it will continue to push hard on lithography (computational lithography, double-patterning) with tolerance for high mask costs (high wafer volume) but NOT for low throughput (in w.p.h.)
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For more information (on ultra-high density)
• ITRS roadmap, www.itrs.net• T. Nirschl, J. B. Philipp, et. al., IEDM Technical Digest, 17.5 (2007).• K. Gopalakrishnan, R. S. Shenoy, et. al., IEDM Technical Digest, 471-474 (2005).• F. Li, X. Y. Yang, et. al. IEEE Trans. Dev. Materials Reliability, 4(3), 416-421 (2004).• H. Tanaka, M. Kido, et. al., Symp. VLSI Technology, 14-15 (2007).• D. Kau, S. Tang, et. al., IEDM Technical Digest, 27.1 (2009).• K. Gopalakrishnan, R. Shenoy, et. al., to appear, Symp. VLSI Technology, 19.4 (2010)
G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, "An overview of candidate device technologies for Storage-Class Memory,"
IBM Journal of Research and Development, 52(4/5), 449-464 (2008).
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How does SCM compare to existing technologies?
Performance
Co
st
NOR FLASH
NAND FLASH
DRAM
SRAM
HDD
STORAGECLASS
MEMORY
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Chart courtesy of
Dr. Chung Lam
IBM Research
Updated version
of plot from
IBM Journal R&D
article
SCM
SCM
If you could have SCM, why would you need anything else?
$1 / GB
$10 / GB
$100 / GB
$1k / GB
$10k / GB
$100k / GB
$0.10 / GB
$0.01 / GB
NAND
DesktopHDD
DRAM
1990 1995 2000 2005 2010 2015
EnterpriseHDD
SCM
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Technology conclusions Motivation
• by 2020, server-room power & space demands will be too high• evolution of hard-disk drive (HDD) storage and Flash cannot help• need a new technology – Storage Class Memory (SCM) – that combines
the benefits of a solid-state memory (high performance and robustness) with the archival capabilities and low cost of conventional HDD
How to build SCM• combine a scalable non-volatile memory (PCM, RRAM, STT-RAM?)• with ultra-high density integration, using
micro-to-nano addressing multi-level cells 3-D stacking
If you build it, they will come• With its combination of low-cost and high-performance,
SCM could impact much more than just the server-room...
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For more information & acknowledgements• G. W. Burr, M. J. Breitwisch, Michele Franceschini, Davide Garetto, K. Gopalakrishnan, Bryan Jackson, B. Kurdi, C. Lam, Luis A. Lastras, Alvaro Padilla, B. Rajendran, S. Raoux, and R. Shenoy, "Phase change memory technology," Journal of Vacuum Science & Technology B, 28(2), 223-262, (2010).
• G. W. Burr, Bulent Kurdi, J. C. Scott, C. H. Lam, Kailash Gopalakrishnan, and Rohit Shenoy, "An overview of candidate device technologies for Storage-Class Memory," IBM Journal of Research and Development, 52(4/5), 449 (2008).
• Simone Raoux, G. W. Burr, M. J. Breitwisch, Charlie Rettner, Y. Chen, R. M. (Bob) Shelby, M. Salinga, D. Krebs, S. Chen, H. Lung, and C. H. Lam, "Phase-change random access memory — a scalable technology," 52(4/5), 465, IBM Journal of Research and Development, (2008).
• Rich Freitas and Winfried Wilcke, “Storage Class Memory, the next storage system technology,”52(4/5), 439, IBM Journal of Research and Development, (2008).
• T. Nirschl, J. B. Philipp, T. D. Happ, G. W. Burr, Bipin Rajendran, M.-H. Lee, A. Schrott, M. Yang, Matt Breitwisch, C.-F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.-H. Chen, S. Zaidi, S. Raoux, Y.C. Chen, Y. Zhu, R. Bergmann, H.-L. Lung, and Chung Lam, "Write strategies for 2 and 4-bit multi-Level phase-Change memory," IEDM Technical Digest, paper 17.5, (2007).
• Yi-Chou Chen, C. T. Rettner, S. Raoux, G. W. Burr, S. H. Chen, R. M. Shelby, M. Salinga, W. P. Risk, T. D. Happ, G. M. McClelland, M. Breitwisch, A. Schrott, J. B. Philipp, M. H. Lee, R. Cheek, T. Nirschl, M. Lamorey, C. F. Chen, E. Joseph, S. Zaidi, B. Yee, H. L. Lung, R. Bergmann, and C. Lam, "Ultra-Thin Phase-Change Bridge Memory Device Using GeSb," IEDM Technical Digest, paper S30P3, (2006).
• M. Breitwisch, T. Nirschl, C.F. Chen, Y. Zhu, M.H. Lee, M. Lamorey, G.W. Burr, E. Joseph, A. Schrott, J.B. Philipp, R. Cheek, T.D. Happ, S.H. Chen, S. Zaidi, P. Flaitz, J. Bruley, R. Dasaka, B. Rajendran, S. Rossnagel, M. Yang, Y.C. Chen, R. Bergmann, H.L. Lung and C. Lam, "Novel Lithography-Independent Pore Phase Change Memory," Symposium on VLSI Technology, pages 100-101, (2007).
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