Stop Watch

Sean HicksDongpu Jin

ELEC 307 Project 2

Instructor: Alvaro Pinto

April/12/2011

OverviewBackground and TheorySpecificationExplanationSummaryWork to Be DoneConclusion

Background and TheoryWe are modeling a stop watch

using a FPGA board. This stop watch has the most

commonly used functionalities:◦Count, Pause and Reset.

Background and TheoryThis is a hardware and software

co-design project. Models are written in VHDL. Individual model and the entire

system will be tested using simulators.

Design will be implemented on a FPGA board.

Specification• Hardware: • Altera DE II board with: • Cyclone II FPGA• On board 50MHz internal clock• On board seven segments LEDs• On board push buttons

• Software: • Altera Quartus• ModelSim• VHDL

Specification

6

Push buttons

FPGA

7-Seg LEDs

50MHz Clock

ExplanationPrimarily Design:

◦Behavioral Model◦State Transition

ExplanationWe have tested this model using

ModelSim, and it works fine.

Explanation• This model does not work in Quartus.

So we moved to develop a Structural Model. • Inputs:• reset, run, pause, 50MHz internal clock.

• Outputs: • five 7-segment LEDs display each digits.

ExplanationComponents:

◦10Hz Clock Converter, mod 10 counter, mod 6 counter, 7-seg decoder.

SummaryEach component and the entire

system has been tested using waveform in Quartus.

The entire system also has been tested on FPGA.

Work to Be DoneWe have done the experiment

part of this project. Just need to write the report.

ConclusionThis concludes our presentations

of Project 2- Stop Watch.Any questions?

ConclusionThanks for your attention!