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STOCHASTIC LOGIC STOCHASTIC LOGIC STOCHASTIC LOGIC Architectures for post-CMOS switches STOCHASTIC LOGIC Architectures for post-CMOS switches David S. Ricketts Jehoshua (Shuki) Bruck Electrical & Computer Engineering Electrical Engineering Carnegie Mellon University California Institute of Technology Carnegie Mellon University California Institute of Technology www.ece.cmu.edu/~ricketts [email protected]

STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

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Page 1: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

STOCHASTIC LOGICSTOCHASTIC LOGICSTOCHASTIC LOGICArchitectures for post-CMOS switchesSTOCHASTIC LOGICArchitectures for post-CMOS switches

David S. Ricketts Jehoshua (Shuki) BruckElectrical & Computer Engineering Electrical EngineeringCarnegie Mellon University California Institute of TechnologyCarnegie Mellon University California Institute of Technologywww.ece.cmu.edu/~ricketts [email protected]

Page 2: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

“Random” at the Nanoscale

Statistical Variation Probabilistic

St h ti Stochastic …….

© D. S. Ricketts 2009

Page 3: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

“Statistical” VariationRandom Dopant

FluctuationsSiO2

GateSiO2Gate

wl

M M

A. Brown et al., IEEE Trans. Nanotechnology, p. 195, 2002

Source DrainSource Drain

Mp1 Mp2

Mn1 Mn2

Ms1 Ms21 2

Line Edge Roughness

Column muxwe we

data dataMwr

Mmux

Gate Oxide Variation

1µmK. Shepard, U.

Columbia

At nanoscale, nothing is deterministic

Gate Oxide VariationYear Leff 3σ Tox 3σ VT 3σ W 3σ H 3σ ρ 3σ

90 nm 47% 16% 13% 33% 36% 33%

© D. S. Ricketts 2009

Momose et al, IEEE Trans. Electron Devices, 45(3), 1998

[Sani Nassif, Proc. IEEE CICC, May 2001]

BOX Devices Wires

Page 4: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

“Probabilistic” Random events during operation, dice are rolled

continuouslyE l P b bili ti CMOS (PCMOS) K V Example: Probabilistic CMOS (PCMOS), K. V. Palem, Rice Univ, et. al.

© D. S. Ricketts 2009 VLSI-SoC: Research Trends in VLSI and Systems on Chip, Springer Boston,

Page 5: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

“Probabilistic” (2) Markov Random Field (MRF) Logic, A. Zaslavsky,

Brown Univ. Nepal, et. al. “Designing Logic Circuits for Probabilistic Computation inthe Presence of Noise”

RAZOR, T. Austin, T. Mudge, Univ Michigan

© D. S. Ricketts 2009D. Ernst, et. al., “Razor: A Low-Power Pipeline Based on Circuit-Level Timing

Speculation”

Page 6: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

“Stochastic” LogicGoal: Leverage random fluctuations of nanoscale switches to build a new paradigm in logic/computation

Random events during operation, dice are rolled continuously

logic/computation.

dice are rolled continuously We don’t look to fix randomness,

but rather exploit it. We are investigating

architectures/logic families that are based on stochastic logicare based on stochastic logic using stochastic switches.

We leverage the inherent

© D. S. Ricketts 2009

“random” state of certain nanoscale devices….

Page 7: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Switch: Bistable Elements Basic idea of a switch* is a

bistable elementT iti b t t t Transition between states can be external, i.e. input, or internal, e.g. thermal energy.

Energy Barrierg gy

In nature, many physical systems have two stable, or meta stable states with anmeta-stable states with an energy barrier between them.

Transitions occur “randomly” ydue to the thermal energy of the system “0” “1”

© D. S. Ricketts 2009

Page 8: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Switch: Bistable Elements (2) Transition between states can

be calculated from the barrier height and the thermal energyheight and the thermal energy of the system ~ kT. Energy Barrier

Tk

EPB

exp

01/ expflipER f

“0” “1”E

0/ e pflipB

fk T

© D. S. Ricketts 2009

Page 9: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Switch: Bistable Elements (3) Probability of state determined

by symmetry of potential well

Energy Barrier

E 2EE

Tk

EPB

exp 2E1E

“0” “1”

© D. S. Ricketts 2009

Page 10: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Example #1 Rotaxane Molecule

Used for dense memory cross bar arrays Switching/relaxation

CHEMPHYSCHEM 2002, 3, 519 ― 525CHEMPHYSCHEM 2002, 3, 519 525

Phil. Trans. R. Soc. A (2007) 365, 1607–1625

1 expBk T GRh RT

: s days

© D. S. Ricketts 2009

Eyring equation

Page 11: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Example #2 Data storage (disk drive) bit

VLow

FePt Nanoparticle arrays E K V V1

V2

Moderate

FePt Nanoparticle arrays uE K V

V3 < V1V2 < V3

High

Stored Data Data Lost

2

Stored Data Data Lost

%)

Magnetization Decay

1050

nm3.03.6 d

20 nm

V3

Mag

netiz

atio

n (

V1V2

S. Sun, C. Murray, D. Weller, L. Folks, A. Moser, Science, 287, pp. 1989 2000

nm05.0d

© D. S. Ricketts 2009

1 minute

Log Time (s)

10 years0

1 year

Page 12: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Stochastic Logic (J. Bruck)“Shannon’s work focused on deterministic switching circuits, circuits where each switch is associated with a Boolean variable defining whether the switch is closed. We instead focus on stochastic switching circuits,the switch is closed. We instead focus on stochastic switching circuits, circuits where each pswitch is associated with a Bernoulli random variable defining the (independent) probability that the pswitch is closed.”

D. Wilhelm and J. Bruck, “Stochastic switching circuit synthesis,” IEEE Int.Sym. on Inf. Theory, Toronto, 2008.

Deterministic switch

Deterministic switch

Switches are ON or OFF with a known probability (not necessarily 50%)( ot ecessa y 50%)

We construct global probabilities based upon a logical connection of probabilistic switches (P it h) d d t i i ti it h

© D. S. Ricketts 2009

(Pswitch) and deterministic switches.

Page 13: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Stochastic Logic (2) Series/Parallel Pswitches

© D. S. Ricketts 2009

Page 14: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Stochastic Logic (3) Examples: Series/Parallel Pswitches

75%

1) Let circuit C1 be the single-pswitch circuit.

37.5% 43.8%

) g p2) For bit Fi, i = 2 to n, let circuit Ci be:

a) If Fi = 0, C1 in series with Ci−1, orb) If Fi = 1, C1 in parallel with Ci−1 1101.011

© D. S. Ricketts 2009

3 2 1 0 1 2 32 2 2 2 .2 2 2

Page 15: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Stochastic Logic: Universal Probability Generator Generating a deterministic input to

desired probabilistic statesC ld t 2n i di id l Could generate 2n individual probability generators and select one Inefficient – exponential increase in switch

count. Need an algorithm that creates the Need an algorithm that creates the

desired probabilities with the minimum hardware

Need universal Pswitch network “synthesizer”

© D. S. Ricketts 2009

Page 16: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Universal Probability Generator Recursive architecture generates a

minimal sized probability generator using 4n 2 switchesusing 4n-2 switches

© D. S. Ricketts 2009

Page 17: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Universal Probability Generator (2) Example

© D. S. Ricketts 2009

Page 18: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Stochastic Logic Summary Goal: Leverage random fluctuations of nanoscale

switches to build a new paradigm in logic/computationlogic/computation.

Utilize thermal energy of nano-scale switches to generate switches that open/close randomlyg p y

Probability of open/close is determined by energy states, i.e. double well geometry. B ild t h ti it h “P it h ” f th Build stochastic switches “Pswitches” from these random devices.

Are able to synthesize arbitrary probabilities given a Are able to synthesize arbitrary probabilities given a known, but not “designed”, probability.

Universal Probability Generator allows for minimal

© D. S. Ricketts 2009

designs of arbitrary deterministic to probability logic networks.

Page 19: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

An Application Example“1 Million RF temperature sensors distributed

uniformly over Indiana, powered by solar energy scavenging circuits that operate sensors for 15scavenging circuits that operate sensors for 15 min per 24 hour period”

© D. S. Ricketts 2009

Page 20: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

An Application Example (2) How to ensure temperature readings throughout

the state 24 hours a day?N d 1/100 f t ll ti Need 1/100 of sensors on at all times.

Need sensors that are on to be even distributed, so that no area is missed.

What is the overhead of organization? Of communication?

B ild h ith 1/100 b bilit f b i Build each sensor with a 1/100 probability of being turned ON. Sensor network will inherently provide even coverage and time/energy organization.

What if 15 min varied by weather, by adjusting random wake-up, energy adaptive networks could be implemented

© D. S. Ricketts 2009

be implemented.

Page 21: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

Outlook Applications

General probability generators Energy/distribution management Stochastic computation in

e ol tionar s stems e g evolutionary systems, e.g. “Stochastic switching as a survival strategy in fluctuating environments”, Nature Genetics

Efficient implementation of Ps ithces at the Efficient implementation of Pswithces at the nanoscale

Development of more complex synthesis and

© D. S. Ricketts 2009

p p ycomputation theory/ algorithms.

Page 22: STOCHASTIC LOGIC Architectures for post-CMOS switchesmind/news/WorkshopSlides/05_Ricketts.pdf · 2009. 9. 14. · “Stochastic” Logic Goal: Leverage random fluctuations of nanoscale

QUESTIONSQUESTIONS

© D. S. Ricketts 2009