STMicroelectronics presentation

Packaging services

SEMI Packaging Tech Seminar

Nanium Portugal, June 18th 2015

Who we are 2

As of December 31, 2014

Listed on New York Stock Exchange,

Euronext Paris and Borsa Italiana, Milano

• A global semiconductor leader

• 2014 revenues of $7.40B

• Approximately 43,600 employees worldwide

• Approximately 8,700 people working in R&D

• 11 manufacturing sites

Where you find us 3

Our automotive products

are making driving safer,

greener and more

entertaining

Our smart power products

are allowing our mobile products to operate longer

and making more of our energy resources

Our MEMS & Sensors

are augmenting

the consumer experience

Our Microcontrollers

are everywhere

making everything smarter

and more secure

Our digital consumer products

are powering the augmented

digital lifestyle

Packaging R&D sites

Grenoble - France Kirkop - Malta

Corporate Packaging and Automation / Packaging R&D sites

(France, Italy, Malta, Singapore, Philippines, China)

Agrate - Italy

Calamba - Philippines

Toa Payoh - Singapore

4

Agrate

Grenoble

CPA - China

Kirkop CPA-China

Calamba

Toa Payoh

Packaging Platforms 5

Leadframe

package

Laminate substrate

package (BGA)

MEMS & sensors

package

Wafer level

package / 3D

WL

Camera

6

BGA (Ball Grid Array) Platform Development

& Advanced Packaging R&D – ST Grenoble, France

• Assembly Process R&D

• Low k/ Ultra Low k Packaging solutions

• Package Design & BGA Substrate Technology

• New Product / Packaging Project Management

• Package Electrical Modeling & Measurement

• Assembly Design Rules Management

• 3D Advanced Packaging

• Wafer Level Solutions

Copper wire dev.

For low k wafers

3D TSV assembly

(ST & Leti)

Flip-Chip dev.

For low k wafers

Ceramic, BGA (Ball Grid Array)

& Advanced Packaging Prototyping – ST Grenoble, France

• Best in class cycle time with

Fab/EWS/Package test proximity

• 1000m² clean room facilities

• Class 10K to class100

• Thin wafers < 100um

• Wire Bonding @ 36um pitch

• Fine Pitch Flip-Chip assembly @

80um (D2substrate) 40um (D2D)

• 0.3mm BGA ball pitch

Laminate

& ceramic packages

12 inches wafer

size capability

SIP capability

including

01005 SMD & FC

3D TSV assembly

Now open for external customers

ST Grenoble – External offer 8

Package

Design

Modeling

Assembly Package test

Package

reliability/

Physical

analysis

9

ST Gnb assembly pilot line– packages portfolio

PBGA WB 27² & 35²

Heat spreader

BGA Matrix& Single

FC & Stud bump

Matrix BGA WB

Matrix BGA SIP

WB and/or FC

Ceramic WB

Gel or waffle pack

service

Backgrinding &

Sawing service

WB: Wire Bonding, FC: flip-Chip

Package Interconnections 10

BGA, 3D die to die, 3D die to wafer

Process Mass Reflow

process

Thermo

Compression

Process

Thermo

Compression

Process

Thermosonic

Process (GGI)

Bumping

capability No No Yes Yes

Bump /

Process

Solder bump +

CUF Copper

pillar + CUF

Copper pillar

+ NCP

Gold stud bump

+ NCP Gold stud bump

Flip-Chip

Wire Bonding Stacked dies

ST Grenoble external offer

• Complete offer

• High expertise

• Advanced process capability

11

• Cycle time

• Flexibility

• Security/ Traceability