Stereo Vision Using Parallel Processing

8/2/2019 Stereo Vision Using Parallel Processing

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Plan of the Talk

Introduction

Stereo Vision

Parallel Processing: Architecture Summary and conclusions


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We are planning to design and implement areal time stereo vision-based hardware and

software architecture, based on a full-custommassively parallel hardware, capable of givingdepth map of the image.

We aim to achieve a latency of about 20ms soit can be implemented in real time.

Introduction


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Algorithm design and Implementation


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With two (or more) cameras we can infer depth, by means oftriangulation, if we are able to find corresponding (homologous) pointsin the two images


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Symmetric support Combines accuracy of adaptive weights approaches with

efficiency of traditional (correlative) approach Deploys a regularized range filter computed on a block basis of

size wxw

Increase noise robustness Efficient pixel-wise cost computation by means of integral-

image/box-filtering schemes Results comparable to top performing approaches Segment Support and Adaptive Weights Fast: 32 sec on Teddy (w=3) Moreover, several trade-off speed vs accuracy are feasible: 14 sec

(w=5) , 9 sec (w=7), 5 sec (w=9)


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Exploits the mutual relationships among neighbouringpixels by explicitly modelling the continuity constraints

Very accurate (significant improvements near depthdiscontinuities and low textured regions)

Notable improvements compared to state-of-the-artapproaches

Fast 37 sec* on Teddy (un-optimized code) deploying thedisparity hypotheses provided by Fast Bilateral Stereo

Fast: 15 sec* on Teddy (un-optimized code) deploying thedisparity hypotheses provided by Fixed Window


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Architecture


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Stereo Vision and Learning Algorithms can be easilyimplemented in parallel. [4][5][6] These algorithms consists of high no. of mutually

independent processes at any particular instant.

The speed with which a single processor can processdata(number of instructions per second, FLOPS) cannot beincreased beyond a limit: It is difficult to cool faster CPUs. Faster CPUs demand smaller chip size which again creates

more heat. Using a fast/parallel computer :

Can solve existing problems/more problems in less time. Can solve completely new problems leading to new findings.


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Requirement Data acquisition (Frames)

Stereo vision computation

Data Storage in real-time

Adapted for stereo vision algorithms

Solution Proposed

Effective CPU utilization Parallel and pipeline stages

Checking Memory Latency time Balancing slow external storage units and fast closer

memory units


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Microprocessors Floating Point (FP) units + SIMD C/C++ (+ assembly) Power, cost and size are the main drawbacks

Application-specific integrated circuit (ASIC)

Low power & low cost processor C/C++ Costly Physically large, high power consumption no SIMD (often)

GPUs (Graphic Processing Units) raw power high power dissipation and cost programming is difficult (CUDA and OpenCL help)

FPGA (Field Programmable Gate Array) efficient, low power (


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Using standard parallel processing units Designing interface between components following standards

Pros

Can be used for solving many problems ( Servers, DNA, DynamicSimulation etc.) Less detailed programming

Cons

Generally requires more hardware then required for specificproblem Costly Physically large, high power consumption


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Using Application-specific integrated circuit (ASIC) ASICs can achieve superior performance for a limited set of

applications.

ASICs need long design cycle and restrict the flexibility of the

system and exclude any post-design optimizations andupgrades in features and algorithms

Reconfigurable systems (FPGA-based real-time Systems)

Reduce the time, cost and expertise requirements inhardware-based algorithm implementation

Can be reprogrammed to facilitate improvement andmodification in design


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SRAM SRAMSRAM

SRAM

SRAM

SRAM SRAMSRAM

SRAM SRAMSRAM

Perm

anentMemory

Thread (Core) Memory Unit

N units

N units

ProcessDistribu

tion


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[1] S. Mattoccia, S. Giardino, A. Gambini, Accurate and efficient cost aggregation strategy for stereocorrespondence based on approximated joint bilateral filtering, Asian Conference on ComputerVision (ACCV2009)

[2] S. Mattoccia, A locally global approach to stereo correspondence, 3D Digital Imaging andModelling (3DIM2009)

[3] F. Tombari, S. Mattoccia, L. Di Stefano, E. Addimanda, Classification and evaluation of costaggregation methods for stereo correspondence, IEEE International Conference on Computer Visionand Pattern Recognition (CVPR 2008)

[4] A Parallel Reconfigurable Architecture for Real-Time Stereo Vision , Lei Chen Yunde Jia Sch. ofComput. Sci., Beijing Inst. of Technol., Beijing , Embedded Software and Systems, 2009. ICESS '09.

[5] An on-chip parallel memory architecture for a stereo vision system , Motten, A. Claesen, L.Expertise Centre for Digital Media, Hasselt Univ., Diepenbeek, Belgium , Electronics, Circuits, andSystems (ICECS), 2010 17th IEEE International Conference on 12-15 Dec. 2010

[6] http://danstrother.com/2011/01/24/fpga-stereo-vision-project/ [7] http://www.iucaa.ernet.in/~jayanti/parallel.html

[8] An Overview of Parallel computing , Jayanti Prasad ,Inter-University Centre for Astronomy &Astrophysics, Pune, India (411007) , May 20, 2011

[9] Stereo Vision: Algorithms and Applications, Stefano Mattoccia, DEIS, University of Bologna,[email protected], http://www.vision.deis.unibo.it/smatt/stereo.htm
http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://www.iucaa.ernet.in/~jayanti/parallel.htmlmailto:[email protected]://www.vision.deis.unibo.it/smatt/stereo.htmhttp://www.vision.deis.unibo.it/smatt/stereo.htmmailto:[email protected]://www.iucaa.ernet.in/~jayanti/parallel.htmlhttp://www.iucaa.ernet.in/~jayanti/parallel.htmlhttp://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/http://danstrother.com/2011/01/24/fpga-stereo-vision-project/


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Thank You !


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Rajesh Uniyal 2k10/EC/112

Naman Madan 2k10/EC/086

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Stereo Vision Using Parallel Processing