Stellaris® LM3S9997 RevB1 ErrataSTELLARISERRATA Stellaris® LM3S9997RevB1Errata ThisdocumentcontainsknownerrataatthetimeofpublicationfortheStellaris® LM3S9997 microcontroller

S T E L L AR I S ERRATA

Stellaris® LM3S9997 RevB1 ErrataThis document contains known errata at the time of publication for the Stellaris® LM3S9997microcontroller. The table below summarizes the errata and lists the affected revisions. See thedata sheet for more details.

See also the ARM® Cortex™-M3 errata, ARM publication number PR326-PRDC-009450 v2.0.

Revision(s) AffectedErratum TitleErratumNumber

B1JTAG INTEST instruction does not work1.1

B1The Recover Locked Device sequence does not work1.2

B1Hard Fault possible when waking from Sleep or Deep-Sleep modes and Cortex-M3Debug Access Port (DAP) is enabled2.1

B1Sleep and Deep-Sleep mode not usable at higher speeds when ISRs reside in Flashmemory2.2

B1Device Capabilities registers may not accurately reflect available signals2.3

B1The PIOSC is not trimmed by the factory2.4

B1Hibernation module may have higher current draw than specified in data sheet undercertain conditions3.1

B1Hibernate POR may not reset the Hibernation module until VDD is applied3.2

B1Power consumption increases if VDD is not restored after wake from hibernation3.3

B1ESD protection on the VBAT pin does not meet specifications3.4

B1Use of the VDD3ON mode to initiate hibernation damages the part3.5

B1Hibernatemodule power consumption higher than expected in event wakeup configuration3.6

B1The Real-Time Clock gains or loses time going in and out of hibernation when using acrystal3.7

B1Low-battery detect circuit is powered down during hibernate3.8

B1Cumulative page erases may introduce bit errors in Flash memory4.1

B1Flash Write Buffer does not function above 50 MHz4.2

B1Ethernet fails to connect when using the Boot loader software in ROM5.1

B1Some ROM functions are unsupported5.2

B1ROM mapping check for the Boot loader does not function properly5.3

B1Port B [1:0] pins require external pull-up resistors6.1

B1UART Smart Card (ISO 7816) mode does not function7.1

B1When in IrDA mode, the UnRx signal requires configuration even if not used7.2

B1An interrupt is not generated when using µDMA with the SSI module if the EOT bit is set8.1

1Texas Instruments

October 02, 2009/Rev. [email protected]

Revision(s) AffectedErratum TitleErratumNumber

B1Some bits in the I2SMCLKCFG register do not function9.1

B1I2S SCLK signal is inverted in certain modes9.2

B1Ethernet receive packet corruption may occur when using optional auto-clock gating10.1

B1Ethernet packet count decremented before the FCS is read10.2

B1Ethernet packet loss with cables longer than 50 meters10.3

B1Ethernet PHY interrupts do not function correctly10.4

B1USB0ID and USB0VBUS signals are required to be connected regardless of mode11.1

B1Latch up may occur if power is applied to the VBUS pin but not to VDD11.2

B1PWM generation is incorrect with extreme duty cycles12.1

B1Sync of PWM does not trigger "zero" action12.2

B1PWM "zero" action occurs when the PWM module is disabled12.3

B1PWM Enable Update register bits do not function12.4

B1Power-on event may disrupt operation13.1

B1Momentarily exceeding VIN ratings on any pin can cause latch-up13.2

1 JTAG1.1 JTAG INTEST instruction does not work

Description:

The JTAG INTEST (Boundary Scan) instruction does not properly capture data.

Workaround:

None.

Silicon Revision Affected:

B1

Fixed:

Fixed in Rev C.

1.2 The Recover Locked Device sequence does not workDescription:

If software configures any of the JTAG/SWD pins as GPIO or loses the ability to communicate withthe debugger, there is a debug sequence that can be used to recover the microcontroller, calledthe Recover Locked Device sequence. After reconfiguring the JTAG/SWD pins, using the RecoverLocked Device sequence does not recover the device.

Workaround:

To get the device unlocked, follow these steps:


2Texas Instruments

Stellaris® LM3S9997 B1 Errata

1. Power cycle the board and run the debug port unlock procedure in LM Flash Programmer. DONOT power cycle when LM Flash Programmer tells you to.

2. Go to the Flash Utilities tab in LM Flash Programmer and do a mass erase operation (check"Entire Flash" and then click the Erase button). This erase appears to have failed, but that isok.

3. Power cycle the board.

4. Go to the Flash Utilities tab in LM Flash Programmer and do another mass erase operation(check "Entire Flash" and then click the Erase button).


B1

Fixed:

Not fixed in Rev C.

2 System Control2.1 Hard Fault possible whenwaking fromSleep or Deep-Sleepmodes

and Cortex-M3 Debug Access Port (DAP) is enabledDescription:

If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a lowpower sleep or deep-sleep mode, the core may start executing code before all clocks to peripheralshave been restored to their run mode configuration. The DAP is usually enabled by software toolsaccessing the JTAG or SWD interface when debugging or flash programming. If this conditionoccurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock.

Workaround:

A software delay loop can be used at the beginning of the interrupt routine that is used to wake upa system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code thataccesses a peripheral register that might cause a fault. This loop can be removed for productionsoftware since the DAP is most likely not enabled during normal execution.

Since the DAP is disabled by default (power on reset), the user can also power cycle the device.The DAP will not be enabled unless it is enabled through the JTAG or SWD interface.


B1

Fixed:

Will not be fixed.

2.2 Sleep and Deep-Sleep mode not usable at higher speeds whenISRs reside in Flash memoryDescription:

Sleep and Deep-Sleep modes cannot be used when running the processor at 66 or 80 MHz whenthe ISRs and vector table reside in Flash memory. If Sleep or Deep-Sleep mode is used at those

3Texas Instruments



speeds, an invalid PC is sometimes returned for the interrupt vector address when exiting sleepmode.

Workaround:

There are two possible workarounds for this issue:

1. Store the ISRs and vector table in the on-chip SRAM when running the processor at 66 or 80MHz.

2. Run the processor at 50 MHz.


B1

Fixed:

Fixed in Rev C.

2.3 Device Capabilities registers may not accurately reflect availablesignalsDescription:

Some of the Device Capabilities register bits reflect the presence of specific pins on themicrocontroller. These bits do not always properly reflect the available signals. Bits affected includeDC3 [31:0], DC4 [15:14], DC5 [27:24] and [7:0], and DC8 [31:0]. Do not rely on the value of thesebits in system design.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

2.4 The PIOSC is not trimmed by the factoryDescription:

The PIOSC is not trimmed by the factory prior to shipment.

Workaround:

For parts that have a Hibernation module, the PIOSC can be user calibrated.


B1

Fixed:

Fixed in Rev C.


4Texas Instruments


3 Hibernation Module3.1 Hibernation module may have higher current draw than specified

in data sheet under certain conditionsDescription:

If a battery voltage is applied to the VBAT power pin prior to power being applied to the VDD powerpins of the device, the current draw from the VBAT pin is greater than expected. The current maybe as high as 1.6 mA instead of the data sheet specified 17 µA. The condition exists until power isapplied to the VDD pin. Once the VDD pin has been powered, the VBAT current draw functions asexpected. The VDD pin can then be powered up and down as required and the VBAT pin currentspecification is maintained.

Workaround:

The VBAT pin higher-than-specified current draw condition can be avoided if the microcontroller'sVDD power pins are powered on prior to the time a battery voltage is initially applied to the VBATpin.


B1

Fixed:

Fixed in Rev C.

3.2 Hibernate POR may not reset the Hibernation module until VDD isappliedDescription:

If VDD is not powered when voltage is first applied to VBAT, the state of the Hibernation module isindeterminate and the HIB signal may be asserted. In this indeterminate state, a lock condition canoccur in which the Hibernation module waits for a power-on-reset, but that reset cannot occur untilthe module deasserts HIB. This issue is related to the errata “Hibernation module may have highercurrent draw than specified in data sheet under certain conditions” on page 5.

Workaround:

The workaround implementation depends on the system-level power supply configuration. Forsystems that use a battery as the primary power source, an external voltage supervisor(TPS383J25DBV or similar) circuit can be added to force the VDD power supply to start when thebattery voltage is first applied (see Figure 1). The voltage supervisor requires only 220 nA andgenerates a 200-ms positive pulse to turn on the VDD regulator and activate the microcontoller'sinternal POR circuit.

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Figure 1. Workaround Circuit to Ensure Initial Power Up

*

* Additional Parts for Workaround

TPS3837J25Voltage Supervisor*RST

VBATVBAT

CTVDD

MR

VoltageRegulatoror Switch

VOUTVIN

EN10 KΩ*

3.3 MΩ(typ.)

VDD tosystem

HIB

Stellaris®Device

VBATVBAT

LowVf

Diode

VDD

VDD


B1

Fixed:

Fixed in Rev C.

3.3 Power consumption increases if VDD is not restored after wakefrom hibernationDescription:

If a wake event occurs and VDD does not rise to specified levels, then the wake event is held offuntil VDD is within specified levels. If a large delay occurs between the wake event and VDD reachingspecified levels, the VBAT current increases substantially to a typical value of 255 µA until VDDreaches the specified levels, at which point the microcontroller comes out of hibernation and powerconsumption returns to expected levels.

Workaround:

Ensure that VDD reaches specified levels within 250 μs after the wake event occurs.


B1


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Fixed:

Fixed in Rev C.

3.4 ESD protection on the VBAT pin does not meet specificationsDescription:

The ESD protection on the VBAT pin fails when tested at 2 kV.

Workaround:

Extra precaution should be taken to protect the part from ESD events. Some applications mayrequire system-level ESD protection on this pin.


B1

Fixed:

Fixed in Rev C.

3.5 Use of the VDD3ON mode to initiate hibernation damages the partDescription:

The VDD3ON mode is enabled by setting the VDD3ON bit in the Hibernation Control (HIBCTL)register. Permanent damage can occur to the device if this mode is used.

Workaround:

Do not use the VDD3ON mode to enter hibernation, instead use an external switch or regulator tomanage VDD power to the device.


B1

Fixed:

Fixed in Rev C.

3.6 Hibernate module power consumption higher than expected inevent wakeup configurationDescription:

With the Hibernation module configured for an external event wakeup, the current consumption ofthe device is higher than expected. The Hibernation module clock does not shut down properlyduring the hibernate asynchronous external wake mode resulting in extra current consumption.Some devices properly shut down the clock the first time entering this mode and others do not.When waking from a hibernate event, the Hibernation module clock is always enabled. In subsequenthibernate cycles, the oscillator is not shut down properly and remains active. Hibernate modulecurrent consumption averages 21µA with the clock disabled. The current consumption averages31µA with the Hibernation module clock enabled.

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Workaround:

When the Hibernation module clock is not required during hibernation, software can disable it byclearing the CLK32EN bit in theHibernation Control (HIBCTL) register before going into hibernationmode.


B1

Fixed:

Fixed in Rev C.

3.7 The Real-Time Clock gains or loses time going in and out ofhibernation when using a crystalDescription:

When using a 4.194304-MHz crystal, the Real-Time clock in the Hibernation module gains or losesa small amount of time (on the order of one second over a 24-hour period when cycling hibernatemode 4 times a minute) when going in and out of hibernation.

Workaround:

Use an external 32.768-kHz oscillator as the source for the Hibernation module clock.


B1

Fixed:

Fixed in Rev C.

3.8 Low-battery detect circuit is powered down during hibernateDescription:

The low-battery detect feature on the VBAT input is only valid when VDD power is present. As a result:

Because the battery is not electrically loaded when VDD is present, the low-battery detect circuitmay not reflect the actual battery status.

In Hibernate mode, a low-battery condition may prevent wake until the battery is completelydepleted.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.


8Texas Instruments


4 Internal Memory4.1 Cumulative page erasesmay introduce bit errors in Flashmemory

Description:

Cumulative page erases anywhere in the Flash memory array may introduce bit errors. The bit erroris not confined to the page being erased or the 4-KB block but could be in any page in the Flashmemory. A page erase is used to erase a 1-KB page so it can be rewritten. A mass erase erasesthe entire Flash memory array (all pages). A bit error means that a bit may change from 0 to 1 or 1to 0.

Workaround:


1. Minimize total page erases to less than 3000 betweenmass erases for the lifetime of the product.After each mass erase, an additional 3000 page erase operations are allowed before bit errorsmay be introduced. At the rate of one page erase per week, this issue would not be seen overat least 17 years.

2. Perform CRC checks on all Flash memory after page erases to increase the chances of detectingthe issue. The two CRC functions built into ROM can assist in this.


B1

Fixed:

Fixed in Rev C.

4.2 Flash Write Buffer does not function above 50 MHzDescription:

The Flash Write Buffer does not successfully program the Flash memory at speeds above 50 MHz.

Workaround:

Lower the speed of the system clock to 50 MHz or less while programming the Flash memory.


B1

Fixed:

Fixed in Rev C.

5 ROM5.1 Ethernet fails to connect when using the Boot loader software in

ROMDescription:

The Ethernet controller takes longer to connect than the Boot loader software in ROM allows.

9Texas Instruments



Workaround:

Download the Boot loader software in the on-chip Flash memory and ensure that the Ethernetconnection uses MDI mode only.


B1

Fixed:

Fixed in Rev C.

5.2 Some ROM functions are unsupportedDescription:

The following functions are unsupported in ROM:

CANBitRateSet GPIOPinConfigure GPIOPinTypeI2S I2CSlaveIntClearEx I2CSlaveIntDisableEx I2CSlaveIntEnableEx I2CSlaveIntStatusEx I2SIntClear I2SIntDisable I2SIntEnable I2SIntStatus I2SMasterClockSelect I2SRxConfigSet I2SRxDataGet I2SRxDataGetNonBlocking I2SRxDisable I2SRxEnable I2SRxFIFOLevelGet I2SRxFIFOLimitGet I2SRxFIFOLimitSet I2STxConfigSet I2STxDataPut I2STxDataPutNonBlocking I2STxDisable I2STxEnable I2STxFIFOLevelGet I2STxFIFOLimitGet I2STxFIFOLimitSet I2STxRxConfigSet I2STxRxDisable I2SRxDataGet I2STxRxEnable SysCtlDelay SysCtlI2SMClkSet UARTBusy UARTFIFODisable UARTFIFOEnable


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UARTRxErrorClear UARTRxErrorGet UARTTxIntModeGet UARTTxIntModeSet uDMAChannelSelectDefault uDMAChannelSelectSecondary USBDevEndpointConfigGet USBEndpointDataAvail USBEndpointDMAChannel USBEndpointDMADisable USBEndpointDMAEnable USBModeGet USBOTGHostRequest

Workaround:

Code for these functions is included in the current version of StellarisWare, which can be downloadedfrom the website at http://www.luminarymicro.com/products/software_updates.html.


B1

Fixed:

Fixed in Rev C.

5.3 ROMmapping check for the Boot loader does not function properlyDescription:

Before the processor is released from the reset state, the System Control module is supposed tocheck offset 0x0000.0004 of Flash memory looking for a reset vector that is not 0xFFFF.FFFF. Ifan initialized reset vector is found, Flash memory is mapped to address 0x0000.0000, otherwiseROM is mapped to address 0x0000.0000. Currently, the System Control module errantly checksoffset 0x0000.0008, which is the NMI vector. So, in situations where a valid reset vector (offset0x0000.0004) has been programmed, but the NMI vector has not been programmed, the ROM iserrantly mapped to zero preventing the application that is stored in Flashmemory from being executedout of reset.

Workaround:

Ensure that the NMI vector is always programmed.


B1

Fixed:

Not fixed in Rev C.

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6 GPIO6.1 Port B [1:0] pins require external pull-up resistors

Description:

The internal pull-up resistors are not effective for the Port B0 and B1 pins.

Workaround:

External pull-up resistors must be used on these two pins.


B1

Fixed:

Fixed in Rev C.

7 UART7.1 UART Smart Card (ISO 7816) mode does not function

Description:

The UnTX signal does not function correctly as the bit clock in Smart Card mode.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

7.2 When in IrDA mode, the UnRx signal requires configuration evenif not usedDescription:

When in IrDA mode, the transmitter may not function correctly if the UnRx signal is not used.

Workaround:

When in IrDA mode, if the application does not require the use of the UnRx signal, the GPIO pinthat has the UnRx signal as an alternate function must be configured as the UnRx signal and pulledHigh.


B1


12Texas Instruments


Fixed:

Fixed in Rev C.

8 SSI8.1 An interrupt is not generatedwhen using µDMAwith the SSImodule

if the EOT bit is setDescription:

When using the primary µDMA channels with the SSI module, an interrupt is not generated ontransmit µDMA completion if the EOT bit (bit 4 of the SSICR1 register) is enabled.

Workaround:

Use the alternate µDMA channels for the SSI module.


B1

Fixed:

Fixed in Rev C.

9 I2S9.1 Some bits in the I2SMCLKCFG register do not function

Description:

The top 2 bits of the RXI and TXI bit fields in the I2SMCLKCFG register do not function (bits [29:28]of RXI and bits [13:12] of TXI). The RXI and TXI fields contain the 10-bit integer input for thereceive and transmit clock generator, respectively. The remaining 8 bits in each field functioncorrectly, so most of the possible integer input choices can be used in system design.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

9.2 I2S SCLK signal is inverted in certain modesDescription:

When the I2S controller is operating as a receiver in SCLK Master mode, the WS signal is latchedon the rising edge of SCLK, not the falling edge. In addition, when the controller is operating as atransmitter in SCLK Slave mode, the data is launched on the rising edge of SCLK, not the fallingedge.

13Texas Instruments



Workaround:

For the transmitter, there are two possible workarounds for this issue:

1. Ensure that the I2S0TXSCK signal leads the I2S0TXWS signal by at least 4 ns.

2. Configure as I2S mode with DAC in Left-Justified audio format.

For the receiver, ensure that the CODEC is configured as the SCLK master, and the I2S receivemodule is configured as the SCLK slave.


B1

Fixed:

Fixed in Rev C.

10 Ethernet Controller10.1 Ethernet receive packet corruptionmay occur when using optional

auto-clock gatingDescription:

Ethernet receive packets may be corrupted if the ACG bit in the Run-Mode Clock Configuration(RCC) register is set.

Workaround:

Do not set the ACG bit in the RCC register.


B1

Fixed:

Fixed in Rev C.

10.2 Ethernet packet count decremented before the FCS is readDescription:

The Number of Packets Register (NPR) decrements in the cycle before the Frame Check Sequence(FCS) is read from the Receive FIFO. As a result, software may incorrectly believe the entire packethas been received when it has not.

Workaround:

Use either the DriverLib routine or compare the number of bytes received to the Length field fromthe Frame to determine when the FIFO is empty.


B1


14Texas Instruments


Fixed:

Will not be fixed.

10.3 Ethernet packet loss with cables longer than 50 metersDescription:

The microcontroller experiences some packet loss with Ethernet cables longer than 50 meters innormal operating conditions.

Workaround:


1. Add 10 Ω resistor to the center-tap of the transformer as shown in the figure. These resistorsshould be replaced by a direct connection for silicon that has this item fixed.

2. Continue using the recommended circuit, but limit cable lengths to 50 meters.

Figure 2. Recommended Center-Tap Connections

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Document Number:

RevSheetDate: of4/13/2009 1 6

Drawing Title:

Page Title:

Size

LM3S9B96 Development Board

Micro, EPI connector and Ethernet

B

A

DB-LM3S9B96

10PF

C1

10PF

C2

PC0/TCKPC1/TMSPC2/TDIPC3/TDO

6

5

8

4

2

3

1

7

1CT:1

TX+

TX-

RX+

RX-1CT:1

Y+

Y-

G+

G-

3

8

7

4

5

6

1112

21

GL

GR

910

NC

GND

J1

R649.9

R449.9

R549.9

R749.9

C18

0.1UF

+3.3V

C19

0.1UF

+3.3V

C1710pF

C1310pF

C1610pF

R8

330

Stellaris Microcontroller

R9

330

+3.3V

PF2/LED1

1 2Y1

25.00MHz

C1410pF

10PF

C3

10PF

C4 +3.3V

C50.1UF

PJ2/EPI18PJ1/EPI17PJ0/EPI16

PG7/EPI31

PC4/EPI02PC5/EPI03PC6/EPI04

C70.01UF

C90.1UF

C112.2UF

PH0/EPI06PH1/EPI07

PF4/EPI12

PH3/EPI00PH2/EPI01

OSC1OSC0

XTALPXTLN

M+3.3V

PB4/ADC10/EPI23PB5/EPI22PA5/SSI0TX

PA4/SSI0RX

PA2/SSI0CLK

Ethernet 10/100baseT

PG1/EPI14

PF5/EPI15

Y2

16.00MHz

123456789

10111213141516171819202122232425 26

272829303132333435363738394041424344454647484950

J2

DF12D-50DP

EPI Expansion Connector

PD2/EPI20PD3/EPI21

PE2/EPI24PE3/EPI25

PH4/EPI10PH3/EPI00PH2/EPI01PH1/EPI07PH0/EPI06PJ1/EPI17PB5/EPI22PB4/ADC10/EPI23PE2/EPI24PE3/EPI25PJ3/EPI19PJ4/EPI28PJ5/EPI29PJ6/EPI30PD2/EPI20PD3/EPI21

PH7/EPI27PJ0/EPI16

PG1/EPI14PG0/EPI13 PC4/EPI02

PC5/EPI03PC6/EPI04PC7/EPI05

PH6/EPI26PH5/EPI11PE0/EPI08PE1/EPI09

+3.3V

PG7/EPI31PJ2/EPI18PF5/EPI15PF4/EPI12

+5V

Revision Date Description

History

0 11 Mar 09 Initial Prototype

R1

12.4K

RESETn

PJ3/EPI19PJ4/EPI28PJ5/EPI29PJ6/EPI30

PA3

PA1/U0TXPA0/U0RX

PE4/I2STXWSPE5/I2STXSD

PE6/ADC1PE7/ADC0

PJ7

PB0/USBIDPB1/USBVBUSPB2/I2C0SCLPB3/I2C0SDA

PD0/I2SRXSCK

PD4/I2SRXSD

PD6PD7

PB6/TXSCK/AVREFPB7/NMI

PF0PF1/TXMCLK

LED2

JP2

PF3/LED0

VBUS D- D+ ID G

1 2 3 4

G2

5

G1

J3

USB Micro AB

USB On-the-Go

+VBUS

PB0/USBIDOTG ID

JP4

+VBUS

JP3PB1/USBVBUS

PA0/U0RX26

PA1/U0TX27

PA2/SSI0CLK28

PA3/SSI0FSS29

PA4/SSI0RX30

PA5/SSI0TX31

PC0/TCK/SWCLK80

PC1/TMS/SWDIO79

PC2/TDI78

PC3/TDO/SWO77

PC4/EPI0S0225

PC5/EPI0S0324

PC6/EPI0S0423

PC7/EPI0S0522

PD0 10

PD1 11

PD2/EPI0S20 12

PD3/EPI0S21 13

PE2/EPI0S2495

PE3/EPI0S2596

PD6 99

PD7 100

GND9

GND21

ERBIAS33

RST_n64

LDO 7

OSC048

OSC149

PB0/USB0ID 66

PB1/USB0VBUS 67

PB4/EPI0S23 92

PB5/EPI0S22 91

PB6/AVREF 90

PB7/NMI 89

PB2/CCP0 72

PE0/EPI0S0874

PE1/EPI0S0975

PE4/ADC36

PE5/ADC25

PA6/USB0EPEN34

PA7/USB0PFLT35

PE6/ADC12

PE7/ADC01

PF0 47

PF1 61

PF2/LED1 60

PF3/LED0 59

TXON 46

TXOP 43

PF5/EPI0S15 41

PG0/EPI0S1319

PG1/EPI0S1418

XTLN17

XTLP16

PF4/EPI0S12 42

RXIP 40

RXIN 37

PG7/EPI0S3136

PH0/EPI0S06 86

PH1/EPI0S07 85

PH2/EPI0S01 84

VDDA3

PD5 98PD4 97

GNDA4 VDD 56

VDD 68

VDD 81

VDD 93

PJ2/EPI0S1839

GND45

PJ654

GND57

GND69

GND82

PJ1/EPI0S1787

GND94

PJ0/EPI0S1614

VDD25 38

VDD25 88

PJ350

NC51

PJ452

PJ553

PJ755

PB3 65

C60.01UF

C80.01UF

C120.1UF

C100.1UF

C152.2UF

C210.01UF

+3.3V

PD2/EPI20PD3/EPI21PB4/ADC10/EPI23PB5/EPI22

PE2/EPI24PE3/EPI25

LED1

JP1

PH6/EPI26PH7/EPI27

PA7/USBPFLT/CAN0TXPA6/USBEPE/CAN0RX

PD1/I2SRXWS

PD5/I2SRXMCLK

PE2/EPI24PE3/EPI25PD2/EPI20PD3/EPI21

PB4/ADC10/EPI23PB5/EPI22PH6/EPI26PH7/EPI27

1 2D2

B72590D0050H160

1 2D5

B72590D0050H160

12D1

B72590D0050H160

Indicates factory-default jumper position.

24 Mar 09 Add Rev 0 rework changes.24 Mar 09 Change D3 type9 Apr 09 Add annotation for rework (2 places)

GN

D2

VIN 1VOUT5

PG 4EN 3

U16FAN2558S12X +5V

U16 Required only for LM3S9B96 Rev B1.See errata.

R60

10

R61

10

+3.3V

LED+3.3V

LED


B1

Fixed:

Fixed in Rev C.

10.4 Ethernet PHY interrupts do not function correctlyDescription:

The Ethernet PHY interrupts are not functional. Ethernet PHY interrupts are not necessary for normalEthernet operation. MAC interrupts are all functional and provide necessary operation.

Workaround:

None.

15Texas Instruments




B1

Fixed:

Fixed in Rev C.

11 USB11.1 USB0ID and USB0VBUS signals are required to be connected

regardless of modeDescription:

The DEVMODOTG bit in the USB General-Purpose Control and Status (USBGPCS) register doesnot function correctly.

Workaround:

Connect the USB0VBUS input to VBUS in all modes. In addition, connect the USB0ID pin to groundfor Host mode operation and to VDD for Device mode operation using the DEVMOD bit in the USBGeneral-Purpose Control and Status (USBGPCS) register.


B1

Fixed:

Fixed in Rev C.

11.2 Latch up may occur if power is applied to the VBUS pin but not toVDDDescription:

If power is applied to the VBUS pin but not to VDD, the microcontroller may latch up and or drawexcessive current. This condition can occur if the microcontroller is unpowered and is connectedas a USB device or OTG B.

Workaround:

Power up the microcontroller before attaching the USB cable. Also, the USB cable must be detachedbefore powering down the microcontroller.


B1

Fixed:

Fixed in Rev C.


16Texas Instruments


12 PWM12.1 PWM generation is incorrect with extreme duty cycles

Description:

If a PWM generator is configured for Count-Up/Down mode, and the PWM Load (PWMnLOAD)register is set to a value N, setting the compare to a value of 1 or N-1 results in steady state signalsinstead of a PWM signal. For example, if the user configures PWM0 as follows:

PWMENABLE = 0x00000001

– PWM0 Enabled

PWM0CTL = 0x00000007

– Debug mode enabled

– Count-Up/Down mode

– Generator enabled

PWM0LOAD = 0x00000063

– Load is 99 (decimal), so in Count-Up/Down mode the counter counts from zero to 99 andback down to zero (200 clocks per period)

PWM0GENA = 0x000000b0

– Output High when the counter matches comparator A while counting up

– Output Low when the counter matches comparator A while counting down

PWM0DBCTL = 0x00000000

– Dead-band generator is disabled

If the PWM0 Compare A (PWM0CMPA) value is set to 0x00000062 (N-1), PWM0 should output a2-clock-cycle long High pulse. Instead, the PWM0 output is a constant High value.

If the PWM0CMPA value is set to 0x00000001, PWM0 should output a 2-clock-cycle long negative(Low) pulse. Instead, the PWM0 output is a constant Low value.

Workaround:

User software must ensure that when using the PWM Count-Up/Down mode, the compare valuesmust never be 1 or the PWMnLOAD value minus one (N-1).


B1

Fixed:

Fixed in Rev C.

17Texas Instruments



12.2 Sync of PWM does not trigger "zero" actionDescription:

If the PWM Generator Control (PWM0GENA) register has the ActZero field set to 0x2, then theoutput is set to 0 when the counter reaches 0, as expected. However, if the counter is cleared bysetting the appropriate bit in the PWMTime Base Sync (PWMSYNC) register, then the "zero" actionis not triggered, and the output is not set to 0.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

12.3 PWM "zero" action occurs when the PWM module is disabledDescription:

The zero pulse may be asserted when the PWM module is disabled.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.

12.4 PWM Enable Update register bits do not functionDescription:

The ENUPDn bits in the PWM Enable Update (PWMENUPD) register do not function. As a result,enabling the PWM modules can't be synchronized.

Workaround:

None.


B1

Fixed:

Fixed in Rev C.


18Texas Instruments


13 Electrical Characteristics13.1 Power-on event may disrupt operation

Description:

Incorrect power sequencing during power up can disrupt operation and potentially cause devicefailure.

Workaround:

VDDC must be applied approximately 50 µs before VDD. Normally VDDC is controlled by the part’sinternal LDO voltage regulator. The workaround requires the addition of an external regulator (seeFigure 3) to ensure that VDDC sequencing requirements are met (see Figure 4). Recommendedregulators include FAN1112SX (SOT223) and FAN2558S12X (SOT23-5).

This fix mitigates the on-chip power issue, but does not solve it completely. During development,the Flash memory should also be reprogrammed (using LMflash or another programming tool) atleast once a week.

Figure 3. Configuration of External Regulator

Existing3.3 V

Regulator

1.2 VNew1.2 V

Regulator

VDDVDDVDDVDD

LDOVDDCVDDC

3.3 V+5 V

Figure 4. VDDC Sequencing Requirements

VDDC

VDD

VDDC

VDD

Default PowerSequence

Modified PowerSequence

19Texas Instruments



Detailed characterization is ongoing. Contact the Applications Support Team for the latest information.


B1

Fixed:

Fixed in Rev C.

13.2 Momentarily exceeding VIN ratings on any pin can cause latch-upDescription:

To avoid latch-up, the maximum DC ratings of the part must be strictly enforced. The most commonviolation of the VIN electrical specification can occur when amechanical switch or contact is connecteddirectly to a GPIO or special function (RST, WAKE, ...) pin. The circuit shown in Figure 5 on page 20typically has stray inductance and capacitance that can cause a voltage glitch when the switchtransitions, as shown in Figure 6 on page 20. The magnitude of the glich may exceed the VIN in themaximum DC ratings table in the Electrical Characteristics chapter. Figure 7 on page 21 shows animproved circuit that eliminates the glitch.

Figure 5. Incorrect Reset Circuitry

PU

RST

Stellaris®R

VDD

Figure 6. Excessive Undershoot Voltage on Reset

Volta

ge

Time

0 V

Workaround:

Use a circuit as shown in Figure 7 on page 21. In this circuit, RS should be less than or equal toRPU/10. C1 should be matched to RPU to achieve a suitable tRC for the application. Typical valuesare:

RPU = 10 kΩ

RS = 470 Ω

C1 = 0.01 µF


20Texas Instruments


Figure 7. Recommended Reset Circuitry

PU

C1

RS

RST

Stellaris®R

VDD

After implementing the circuit shown in Figure 7 on page 21, confirm that the voltage on the RSTinput has a curve similar to the one in Figure 8 on page 21, and that the VIN specification is notexceeded.

Figure 8. Recommended Voltage on Reset

Volta

ge

Time

0 V


B1

Fixed:

Fixed in Rev C.

Copyright © 2008-2009 Texas Instruments Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks ofTexas Instruments. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other namesand brands may be claimed as the property of others.

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21Texas Instruments



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Documents

Stellaris® LM3S9997 RevB1 ErrataSTELLARISERRATA Stellaris® LM3S9997RevB1Errata ThisdocumentcontainsknownerrataatthetimeofpublicationfortheStellaris® LM3S9997 microcontroller