Status Report - CERNcds.cern.ch/record/1602590/files/TIARA-REP-WP8-2013-013.pdfTIARA-REP-WP8-2013-013 Test Infrastructure and Accelerator Research Area Status Report Construction and

TIARA-REP-WP8-2013-013

Test Infrastructure and Accelerator Research Area

Status Report

Construction and test of a prototype LLRFelectronics at SPARC

Bronnimann, M. (PSI) et al

23 September 2013

The research leading to these results has received funding from the European Commissionunder the FP7-INFRASTRUCTURES-2010-1/INFRA-2010-2.2.11 project TIARA (CNI-PP).

Grant agreement no 261905.

This work is part of TIARA Work Package 8: HGA R&D Infrastructure.

The electronic version of this TIARA Publication is available via the TIARA web site athttp://www.eu-tiara.eu/database or on the CERN Document Server at thefollowing URL: http://cds.cern.ch/search?p=TIARA-REP-WP8-2013-013

http://www.eu-tiara.eu/database

http://cds.cern.ch/search?p=TIARA-REP-WP8-2013-013

TIARA WP8: High Gradient Acceleration

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Test Infrastructure and Accelerator Research Area

Construction and test of a prototype LLRF electronics at SPARC

Manuel Brönnimann, Ingo Brunnenkant, Alexander Dietrich, Florian Gärtner, Andreas Hauff, Mario Jurcevic, Roger Kalt, Stefan Mair, Lionel Schebacher, Thomas Schilcher, Werner Sturzenegger

(PSI)

02 September 2013

Milestone Report


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WP8.2: RF Low Level Electronics for SPARC

Milestone 32: First LLRF electronics prototype

This report summarizes the work, which has been carried out to reach MS32, "First LLRF electronics prototype" (RF-LLE-P), within the framework of TIARA, work package 8.2 (RF Low Level Electronics for SPARC). The Low Level RF (LLRF) system requirements will be presented followed by a more detailed description of the LLRF system prototype electronics including performance measurements in the laboratory.

1. System Requirements

The SPARC energy upgrade program requires a stable and flexible LLRF system to improve the synchronization between the photo injector laser pulse and the Linac RF (incl. RF pulse compressor) down to ± 0.1 ps. The LLRF system requirements for the SPARC C-band LLRF system have already been presented in the TIARA Milestone report 31 [1] and are summarized again here in Table 1.

Table 1: SPARC LLRF system requirements

PARAMETERS REQUIREMENTS

Main RF Frequency (fRF) 5.712 GHz

Real time waveform display of RF signals shot by shot:

- update rate:

- time window:

preferably all simultaneously

10 Hz

> 4 μs

Number of RF channels ≥ 12

Phase readout resolution < 0.03° @ 5.712 GHz

(preferably: < 0.02° @ 5.712 GHz)

Phase readout error < 0.2° @ 5.712 GHz

Amplitude readout error < 1 % (≈ 0.1 dB)

synchronicity synchronous to flaser=79.333 MHz

external trigger interface 5V TTL level @ 50Ω

programmable trigger delay steps < 8 ns

monitoring bandwidth > 18 MHz

wideband RF output modulation bandwidth > 20 MHz

amplitude set-point dynamic range > 60 dB

amplitude set-point step size < 0.1 dB

phase set-point dynamic range 360°

phase set-point step size < 0.02°

RF waveform mathematical calculations (shot by shot) mean value in defined time window,

standard deviation, max./min. values

interface to control system Ethernet command protocol

RF pulse compressor control manage arbitrary phase programs

pulse-to-pulse RF feedbacks possibility for local implementation


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2. LLRF System Prototype Electronics

The tasks of a modular digital low level RF (LLRF) system is to measure the pulsed RF fields (amplitudes/phases) at various locations along the RF drive path, and control the RF signal from the reference signal distribution (with frequency fCB = 5712 MHz), which is the input to the amplifier chain. The use of powerful digital processing platforms provides the possibility to implement sophisticated feedback algorithms in order to compensate possible drifts of the RF accelerating fields with respect to the electron beam. In this respect, much emphasis has been put on a reliable LLRF measurement system with minimal systematic amplitude and phase readout errors. A C-band low level RF system has been developed and tested in the laboratory. The prototype system is shown in Figure 1 where all digital signal processing boards are installed in a VME64x crate.

Figure 1: C-band digital low level RF prototype electronics with its main components

2.1. Digital Low Level RF System Overview

The main components of the LLRF system are

vector modulator

4x4 channel RF receiver (RF front-end)

local oscillator (LO) generation unit (also generates ADC and DAC clocks)

digital signal processing platform (including ADC’s and DAC)

which are shown in a more detailed layout in Figure 2. As described in the LLRF design report [1] all 5712 MHz RF signals from directional couplers are down-converted to intermediate frequencies (IF) of fIF = 39.667 MHz = fCB/144. Those IF signals are then digitized by 16bit-ADCs on FMC (FPGA Mezzanine Card according to ANSI/VITA 57.1 standard), FMC-516 from company Curtiss Wright, with a sampling rate of fADC = 3 x flaser = 238.0 MHz. The prototype LLRF system has been designed for 16 RF input channels. The C-band drive signal to the amplifier chain can be controlled by a baseband vector modulator with its I/Q inputs connected to a 16bit-DAC FMC (FMC204 from company 4dsp) with an output rate of 238.0 MHz and a clock rate of fDAC = 6 x flaser = 476.0 MHz. The local oscillator generation unit provides the common LO signal for all RF receiver channels and also delivers the very low jitter ADC and DAC clocks for all FMC. The demodulation of each digitized IF signal to baseband is carried out by a non-IQ algorithm with a ratio fIF/fADC = 1/6 where fADC denotes the ADC sampling frequency. This algorithm has been implemented on FPGAs (Xilinx Virtex-6 LXT130T) of each of the three digital processing boards, IFC1210 from company IOxOS. A more detailed description about the characteristics of the non-IQ algorithm is given in chapter 2.2.


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Figure 2: Layout of the SPARC LLRF system with its main components: RF receiver, LO generation unit, vector modulator, digital processing boards with FMCs, and rear transition modules

2.2. Low Level RF Firmware

A graphical overview about the firmware layout of a measurement channel is shown in Figure 3 and is described in more detail in the following.

Figure 3: LLRF FPGA firmware structure for one measurement channel including data transfer to the IFC1210

on-board CPU


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An external hardware trigger signal (TTL signal) to the FPGA selects 2048 consecutive digitized intermediate frequency (IF) 16bit values from the ADC-FMC (ADC raw samples), which are then stored in memory and transferred to the CPU later on. These samples cover a time window of 8.6 μs (=2048/238 MHz). The non-IQ algorithm down-converts the digitized IF signals to baseband (I/Q values). The advantage of this type of algorithm is its simplicity with respect to digital implementation issues, and the fact that the generated upper sideband in the digital down-conversion process at 2∙fIF as well as harmonics up to a certain degree are automatically suppressed due to the non-IQ filter characteristics. The selected non-IQ algorithm with an IF to ADC sampling clock ratio of

results in an amplitude filter characteristics which is shown in Figure 4. The algorithm implemented on the FPGA is a 6-tap FIR filter and is given by

∑ ( ) ∑

∑ ( )

∑

where yi denotes the digitized IF samples from the ADC. The phase advance Δφ between samples is given by

with fixed filter coefficients for the I and Q path.

( )

(

)

( )

(

)

Figure 4: Amplitude transfer function of the non-IQ algorithm with fIF/fADC=1/6 after digital down-conversion

to baseband (fIF=39.667 MHz; fADC=238.0 MHz)


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The algorithm suppresses any harmonic frequency up to the 4th harmonics, which might originate from the RF receiver as well as from ADC non-linearities, by folding it back onto the notches of the non-IQ filter. The -3dB theoretical filter bandwidth (frequency deviation from the RF carrier at which the input amplitude reaches the -3 dB point) amounts 17.8 MHz which corresponds to 35.6 MHz (FWHM) monitoring bandwidth which fulfills the requirement. The I/Q values are then passed through a rotation stage, which provides any desired phase rotation of the measured RF signal. The I/Q buffers are stored in memory and furthermore converted to amplitude/phase by a Cordic algorithm. A down-sampler block reduces the 2x2048 amplitude/phase values to 512 values each in order to provide smaller buffers, which might be used for graphical user interface purposes thereby reducing the data traffic on the controls network. Several other small firmware blocks have been implemented to detect the maximum amplitude within an RF pulse, calculate a partial vector sum based on selectable I/Q channels, and provide I/Q as well as amplitude/phase sums of a user defined time window within the RF pulse which is then used by the real-time application on the PowerPC CPU to calculate intra-pulse and pulse-to-pulse averages and statistics. All these memory buffers are transferred to the PowerPC CPU shared memory in Linux kernel space over the PCI Express switch by a DMA process (Direct Memory Access), after the FPGA has indicated “data ready” by generating a CPU interrupt. A simplified view of the vector modulator control path (DAC output) is shown in Figure 5. The received I/Q tables (2048 values each) from the PowerPC CPU are written to FPGA memory locations, which have been implemented as shadow memories. Only after full I/Q tables download the pulse control block activates this block in order to guarantee an atomic table for I/Q when a trigger is received.

Figure 5: Simplified view of the DAC control firmware to control the baseband vector modulator

Any arbitrary I/Q table can be downloaded which for example allows any desired phase modulation of the klystron output. This is especially important for controlling the output power of the RF pulse compressor. Before the I/Q values are written to the DAC-FMC user defined I/Q offsets are added which allow the offset compensation at the vector modulator inputs to suppress the residual carrier at the RF output of the vector modulator.

2.3. Low Level RF Software

Three processing boards (IFC1210) read in data from the ADC-FMCs as already shown in Figure 2. One of them controls the vector modulator baseband I/Q input through the DAC-FMC. Since it might be necessary to base a pulse-to-pulse feedback on the information of any other RF input channel, it will be necessary to collect all relevant data in one central place. This processing board is defined as master board, which can collect the required data from both slaves either over VME bus or over PCI Express (see Figure 6). However, this application is strongly dependent on the channel configuration. Therefore, it is not yet implemented on low level but the software structure has been prepared for it. Nevertheless, all channels can be read out by the control system, which allows a flexible feedback implementation in high-level applications. Each processing board runs a PREEMPT_RT patched Linux kernel (3.6.11.5-rt37). As described in chapter 2.2 the pre-processed data in FPGA memory is transferred to kernel space memory of the PowerPC CPU. After completion an interrupt is generated for the real-time application, which calculates various averages, standard deviations and pulse-to-pulse jitter values of all RF channels for a user defined time window. Finally, all data is stored in an inter-process shared memory, which provides all information to the implemented EPICS

Pulse

controlDAC

Trigger I

Q

+

+

I_offset

Q_offset

I/Q m em ory

I/Q shadow

m em ory

I

Q

I

Qfrom

CP

U


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(Experimental Physics and Industrial Control System) control system (EPICS version 3.14.12). Through the generation of an interrupt on the EPICS level it is guaranteed that the control system reads all data of every pulse thereby making sure that all provided data belongs to the same RF pulse. The system has been designed to cope with a pulse repetition frequency of up to 100 Hz. New DAC tables are directly downloaded from EPICS to the FPGA memory IQ / IQ shadow tables when those are received through the EPICS channel access protocol (see Figure 7).

Figure 6: One of the three processing boards (IFC1210) acts as master board which can collect the measured

I/Q information of the two slave boards either over VME bus or over PCI Express.

Figure 7: Local data transfer on each processing board.

The data from FPGA memory is transferred to the kernel space of the CPU. A real-time application processes

the data and communicates to the EPICS control system via inter-process communication channels (shared

memory and Unix domain sockets).

The SPARC control system can communicate to the LLRF system over Ethernet by the so-called EPICS channel access protocol.

2.4. Analogue Low Level Electronics

The analog low level electronics (baseband vector modulator, RF receiver, and local oscillator generation unit) are described in detail in [1].

2.4.1. Baseband Vector Modulator

The vector modulator provides the possibility to control the amplitude and phase of the drive signal to the amplifier chains simultaneously. It is based on a low-noise

MemoryKernel space

User space

CP

U

Memory

PCI Express

LAN

(Ethernet)

FPGA

EPICS

Sockets

Shared

MemoryReal-time

Application


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direct quadrature modulator chip (TRF370417) from Texas Instruments, which operates at RF frequencies of 50 MHz through 6 GHz. A balun at its input, an additional RF output amplifier, and two consecutive PIN switches for interlock purposes, which are controlled through TTL input signals, complete the device. The bandwidth of the vector modulator has been measured to be >40 MHz. A schematic overview of the vector modulator is given in Figure 8. The vector modulator resides in the same chassis as the LO generation unit, which can be seen in Figure 9.

Figure 8: Schematic overview of the baseband vector modulator, which includes two consecutive PIN

switches for interlock purposes

Figure 9: Picture of the vector modulator prototype (right-hand side), which resides in the same chassis as

the LO generation unit (left-hand side)

The differential I/Q inputs are controlled by 16 bit D/A converters, which provide a phase set-point dynamic range of 360° and a phase step size of below 0.01° @5712 MHz. The amplitude dynamic range is more than 90 dB while the amplitude step size is below 1e-4 (relative to full-scale). The phase to amplitude modulation errors (PM to AM) have been measured at DAC full-scale voltage and at 32% of DAC full-scale (corresponds to -10dB below full-scale). The results are shown in Figure 10 (upper plot). At full-scale DAC amplitudes the maximal amplitude error for PM to AM conversion is ±0.1dB. This error increases with smaller vector modulator output amplitudes to ±0.2dB at -10dB below maximum output. The maximal relative phase error for amplitude to phase modulation has been evaluated to be less than ±1.5° (see lower plot of Figure 10).


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Figure 10: phase to amplitude (upper plot) and amplitude to phase conversion of the vector modulator,

which is connected to DAC FMC204, at two output levels;

Amax = (DAC full-scale voltage);

Amin = (DAC full-scale voltage) - 10dB ≙ 32% of DAC full-scale voltage

2.4.2. RF multi-channel receiver

A maximum of 16 C-band signals (5712 MHz) are down-converted to an intermediate frequency of 39.667 MHz by the multi-channel receiver. The unit consists of 4 individual 4-channel receiver modules. Thus, it can provide 16 RF channels (see Figure 11).

Figure 11: 16-channel C-band multi-channel receiver, which converts all 5712 MHz down to 39.667 MHz.

An internal splitter distributes the supplied 10 dBm LO signal to the four internal 4-channel receiver sub-modules. Low noise output amplifiers increase the down-converted IF signal levels to match the ADC input range of +11 dBm (2.2 Vpp) (see Figure 12).


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Figure 12: Layout of a 4-channel receiver sub-module within the 16-channel receiver unit.

2.4.3. Local oscillator generation unit

The generation of the local oscillator frequency signal, which is required for the down-conversion process, is accomplished by the LO generation unit. In addition, it also generates the required clock signals for ADC- and DAC-FMCs. As already described in chapter 2.4.1 the LO chassis also includes the vector modulator (see Figure 9). The 5712 MHz reference input signal from the master oscillator will be divided by 144 to result in an intermediate frequency of 39.667 MHz, which is then mixed with the 5712 MHz reference signal. The extraction and amplification of the upper mixing product provides the required LO signal of 5751.667 MHz of about +10 dBm. Dividing the reference signal by 12 generates the DAC clocks of 476 MHz while a division by 24 is demanded to generate the ADC clocks of 238 MHz. A simplified layout of the LO signal generation is shown in Figure 13.

Figure 13: Simplified layout of the C-band local oscillator (LO) signal generation unit, which also generates

the required ADC and DAC clocks

3. Performance Measurements

The C-band LLRF system has been characterized in the laboratory, where the achievements were

compared with the requirements. For these purposes, the signal from a low noise RF master

oscillator has been split to be used as a reference input signal into the LO generation unit and as a

reference C-band signal which has been measured by the LLRF system. Goal of this measurement

setup was the characterization of the intra-pulse phase and amplitude resolution. The intra-pulse

amplitude and phase standard deviations are calculated for a user-defined window between 0.5 μs

and 8.5 μs within the total pulse recording window of 8.6 μs. The results, which are given in Table 2,

show that the intra-pulse resolution of the phase measurements fulfill the requirements and almost

the preferred resolution of 0.02°


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Intra-pulse

standard deviation

Amplitude

(relative)

Phase

required not specified 0.03°

(preferably <0.02°)

measured 3.6 e-4

0.021°

Table 2: Intra-pulse amplitude and phase resolution of the LLRF measurement channels (RF front-end + ADC)

In order to verify the absolute phase and amplitude measurement accuracy of the C-band LLRF

system prototype, a comparison measurement between a four-port vector network analyzer and the

LLRF system has been carried out. An external mechanical phase shifter could shift the signal from

the vector network analyzer up to 360°, which has been measured by the LLRF system and in parallel

by the vector network analyzer. This approach provides the possibility to directly compare the

absolute phase shift measured by both systems. In addition, the reference signal from the vector

network analyzer, which has not been shifted, is measured by the LLRF system in order to quantify

possible drifts of the LLRF measurement system. Any measured drift in this reference signal is solely

due to drifts of the LLRF system and can therefore be subtracted from all other phase measurement

channels. This concept is known in literature as “reference tracking”. Applying the reference tracking

method to the LLRF measurement channel of the phase shifted input signal, the absolute phase

difference between the LLRF C-band prototype system and the vector network analyzer can be

calculated. This measurement also provides the absolute amplitude accuracy of the LLRF prototype

system during a 360° phase scan. The results in the absolute phase and relative amplitude deviations

with respect to the vector network analyzer are shown in Figure 14.

Figure 14: Absolute phase and amplitude measurement error of the C-band LLRF prototype system with

respect to a vector network analyzer. The reference tracking method has been applied in order to correct for

drifts of the LLRF measurement system.

The results confirm that the read back error in phase is below 0.1° peak-to-peak (specified < 0.2°) and in amplitude below 0.1% peak-to-peak (specified <1 %).


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4. Summary and Outlook

The construction of a SPARC C-band LLRF prototype system has been accomplished and its

performance verified in the lab at PSI. The system meets the specifications, which are required for

the successful operation of the new high gradient C-band accelerating structures with a SLED pulse

compressor at the SPARC Test Facility at LNF-Frascati. The LLRF prototype system has been delivered

to INFN Frascati where the integration into the SPARC infrastructure and controls system is being

carried out.

References [1] M. Brönnimann, I. Brunnenkant, A. Hauff, R. Kalt, L. Schebacher, S. Scherrer, T. Schilcher,

“Design of a LLRF system for a High Gradient Acceleration R&D Infrastructure”

(TIARA-REP-WP8-2012-011), 26 July 2012

Documents

Status Report - CERNcds.cern.ch/record/1602590/files/TIARA-REP-WP8-2013-013.pdfTIARA-REP-WP8-2013-013 Test Infrastructure and Accelerator Research Area Status Report Construction and