Status of the Silicon Strip Detector/ FEE development

Status of the Silicon Strip Detector/ FEE development

E. Atkin Moscow Engineering Physics Institute (State University) – MEPhI,

M. Merkin, A.Voronin Skobeltsyn Institute of Nuclear Physics / Moscow State University – SINP / MSU,

V. SavelievState University, Obninsk

CBM Collaboration meeting

October 6-8, 2004

CBM Collaboration meeting, October 6-8, 2004

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New Si-Strip STS Geometry New Si-Strip STS Geometry

40 cm

60 cm

80 cm

100 cm

x

y

z

STS_4

STS_5

STS_6

STS_7 New Geometry of the Si-Strip STS

4 Si-Strip Planes inside the Magnet( equivalent distances along z )

Significantly Reducing the Requirements for the Si-Strip STS Design ( STS_3 is MAPS technology )

by V. Saveliev


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Basic Technology of Si-strip STSBasic Technology of Si-strip STS

Double Sided Si-Strip DetectorsThickness : 100 mkmPitch of strips : 25 mkmStereo Angle : 15o

Inner region of Si-Strip STS:25 mkm Pitch gives 400 strips per cmAccording the occupancy plots for STS_4: 10 Point per cm per event, or 2.5 % for 1 cm length strip17 Point per cm per event, or 4.2% for 2 cm length of strip

by V. Saveliev


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Si strip STS_6 Layout

(layer 6)

Si strip STS_6 Layout

(layer 6)

Basic Elements: Inner : 6x4 cm Middle : 6x12 cmOuter : 6X20 cm

+40 cm

-40 cm

Read out

+4cm

- 4cm

by V. Saveliev


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Silicon Sensors: What we have

•15 years experience in sensor design and production;

•Experience in double side photolitography, first prototype for ATLAS SCT;

•Good new mask aligner for double side photolitograpy (up to 6”)


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Silicon Sensors: What we have

•Fine pitch (25 µm) sensors have been designed and produced for SVD-2 experiment at Protvino;

•Radiation hard sensors designed, prototypes produced and tested up to 8 MRad for D0 RunIIb;

•Almost all equipment for sensor testing.


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Silicon Sensors: What we need

• We need to know physics requirements for sensor geometry;

• Estimation of radiation environment(!!!);

• Estimation of temperature inside tracker;

• Long term scenario: possible warm-cold circles, estimated detector life time – 5 years(?), 10 years(?);


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Silicon Sensors: What we can do

•Photomask design as soon as geometry will be clear;

•Several geometries of sensors could be on the same mask;

•Sensor prototypes production;•Full electrical sensor testing;•Radiation testing (with KRI).


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• Double side polished silicon wafers: 300 µm – 25 wafers (for tests only) 200 µm – 50 wafers; (for prototype 150 µm – 50 wafers; production) 100 µm – 50 wafers.

Total wafers cost – 4000 ÷ 6000€Depends on resistivity and supplier

Silicon Sensors: Cost estimation


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•Photomasks design and production. For double side sensors we need 14 or 15 photomasks. Cost is about 500 - 600 €/mask.

Total masks price: 7000 ÷ 9000 €


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• Sensor production cost (prototypes):– 300 µm – 600 €/wafer;– 200 µm – 700 €/wafer;– 150 µm – 800 €/wafer;– 100 µm – 850 €/wafer.!!! This is not a sensor cost !!!It might be a lot of sensors on

wafer, total active area ~36 cm2


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•Tools and fixtures for testing (? €);

•Testing - 1 man*day/sensor (25 €);

•Cutting – few € per wafer depends on number of cuts;

•Second testing (after cutting) - 1 man*day/sensor (25 €).


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Silicon Sensors: Schedule

• Photomasks design and production - 3 months;

• Sensor prototype production:– 300 µm – 10÷15 wafers - 4 months;– 200 µm – first 10 wafers - 4 months;– 200 µm – second 10 wafers – 2

months;– 150 µm – first 10 wafers -3 months;– 150 µm – second 10 wafers -2 months;– 100 µm – first 10 wafers -3 months


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In total according to this optimistic schedule we will have about 50 wafers with different sensors in 12 – 14 months.Two last months are mainly for testing sensors.Radiation tests could be started on the first batches of 10 sensors.


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Pessimistic case: • no money;• mistakes in sensor design (second

set of masks needs to be made);• problems with thin wafers.

Approximately 20 - 24 months for the whole project, including radiation tests


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Specifications for the silicon strip detector chip

• Minimal signal – 7000 electrons per mip (100um detector thickness)• Detector capacitance can be 30-300 pF depending on thickness and length

of the strip, as follows from the simulation and design of tracker at a suitable signal/noise ratio

• Signal noise ratio – better than 10 for 1 mip• Dynamic range (?) – 10 mips• Input signals come at random time. Maximal average frequency of the

signal at the chip input is 10 MHz• Radiation hardness – 15-20 MRad• Power consumption, as small as possible. The maximal one – few

mW/channel • Supply voltages depend on the technology• Number of channels on the chip is dictated by tracker design (128, 256,….)• Minimal number of external components


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• AC detector-input coupling with a possible DC one for (?) detector dark current management

• Input overvoltage protection. It must not increase noise.

• Input pad pitch – 25-100 um

• Connection between the chip and detector – (?) by bonding, bumping, gluing to the designed tracker

• back contact – (?) insulated or VSS

• Base line stability (?)

• Linearity (?)

• Working temperature – (?) 0-50˚C


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Main Features

– Amplitude measurement

– Time of event

– Digitization of amplitude and time

– Dead-time free

– No external trigger

– Calibration (test) system

– Flexibility of control and adjustment


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Chip general structure– Analog part

– ADC

– Digital part

– Control

– Calibration (test) system

Completely self-triggered or signal finder built-in

Synchronizing with external clock – 5-100 ns

ADC resolution (?) – 4-6 bits for amplitude, 6 bits for time (resolution – few ns)

Signal processing – analog shaping (?) 10-30 ns, digital signal shape analyzing

Data processing – maximal data reduction and compression

How to realize the chip?


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Biasing for Si detector and its readout scheme

To amplifierTo next stage

To next stage


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Peak timeadjustment

PolaritySwitch

CSA

Feedbackadjustment

Inputprotection

Ccal

SoftLimiter

Limitationadjustment

CR-RCn

Shaper(n=2)

Scaleamplifier To ADC

Gainadjustment

Switcharray

DACarray

Testdata

Calibration (test) System

T-Pulse Fastshaper

Analog finder

Threshold

DAC


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ADC

Buf

fer

Pedestalsubtraction

Pedestalmemory

Pedestalcalculator

Pedestalmeasurement

mode

Noisereduction

Shapereconstruction

Signalfinder

Amplitude& Time

reconstruction

Zero suppression

Datareduction

Interface(serial)

Internalpulser

(phase control)

ExternalCLK

Control


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Peak timeadjustment

Polarityswitch

CSA

Feedbackadjustment

Inputprotection

Ccal

CR-RCn

shaper(n=2)

Switcharray

DACarray

Testdata

Calibration (test) System

T-Pulse Fastshaper

Analog finder

Threshold

DAC

Peakdetector

Delay(adjust.)

Pipeline

To ADC

From pulser


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ADC

Buf

fer

Pedestalsubtraction

Pedestalmemory

Pedestalcalculator

PedestalMeasurement

Mode

Zero suppression

Datareduction

Interface(serial)

Internalpulser

(phase control)

ExternalCLK

Control

To pipeline

Timemeasurement


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Short resume on the aim of the ASIC• The main aim of the ASIC to be developed for CBM Si microstrip detectors is to provide both amplitude and timing (event

separation) measurements

• Mechanical (dimensional) fit (face-to-face) between strips and caseless ASICs

• Space limitation at the detector forces to provide reasonable multiplexing to save a number of cables (communication lines) to be used

• The self-triggering is an important issue

• Accurate track reconstruction forces to have:» Massive parallelism of read-out» High complexity (functionality) of mixed-signal ASICs» Radiation hardness (tolerance)


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Technology choice

• “Today 0.18…0.25 µm CMOS processes form the mainstream industrial production technologies and 0.13 µm processes are coming on-line as the next industrial generation” (P. Jarron. Trends in microelectronics and nanoelectronics and their impact on HEP instrumentation. Proc. of the 8th Workshop on Electronics for LHC experiments, 9-13 Sept. 2002, Colmar, CERN/LHCC-2002-034, p.9-16)

• Probably it is expedient to add 0.25 µm Bi-CMOS processes. Bipolar is dictated by fast and precise analog blocks (like fast low-offset comparators, op amps). Usually it simplifies and shortens the design stage at the expense of more complexity of the process.

• Radiation tolerant Deep Sub Micron (DSM) 0.13 µm CMOS process (0.25 µm Bi-CMOS one) for prototyping and studying the possibilities seems to be the best candidate and was recommended by the 1st CBM FEE ASIC workshop at CERN on Sept. 24-26, 2004.


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Possible selection of manufacturers

• UMC, Taiwan is the best as it was recommended by the meeting at CERN on Sept. 24-26, 2004.

• IHP GmbH – Innovations for High Performance Microelectronics, Frankfurt (Oder), Germany

• AMS – AustriaMicroSystems AG, Schloss Premstätten, Austria

• TSMC – Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan

• Others


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In the Moscow Design Group(MEPhI* Europractice full membership number A47530)

• PCs and Sun Workstations

• Linux and Solaris environment

• Cadence tools

• Europractice Design Kits

• ISE TCAD tools

We are using mostly:

* since 1996 Cadence software usage

since 2004 Partner of Cadence/Moscow


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ASIC Development scheduleID Task Name

1 Start point --> CBM meeting Oct. 6-82 CBM standard software (Cadence, Mentor) installation, upgrade3 Design Kits (DKs) installations, upgrade4 FEE general structure development (I prototype -- functional one). ABM5 Schematics design for all structure units6 Whole ASIC (I prototype) schematics simulation + spread (Monte-Carlo) 7 Floorplanning and layout design + DRC, LVS, PS8 Transferring files to MPW service and manufacturing prototype chips there9 Lab tester development (board development, array programming, Lab View)10 ASIC (I prototype) lab tests11 1st prototype ASIC ready12 FEE general structure modification. ABM13 Schematics design for units needed14 Whole ASIC (II prototype) schematics simulation + spread (Monte-Carlo) 15 Layout design + DRC, LVS, PS16 Transferring files to MPW service and manufacturing there prototype chips17 Lab tester upgrade 18 ASIC (II prototype) lab tests19 2nd prototype ASIC ready20 Making decision on mass production

08.10

30.11

24.01

24.01

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q32004 2005 2006 2007 2008


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Schedule is a quite optimistic (only two prototypes used to reach a final solution).

Moscow Si-strip group also plans to develop read-out electronics for lab test purposes of the Si strips at the detector lab of MSU. Most likely it forces to design a quite fast and low noise analog chain, based on Bi-CMOS process (0.25…0.8 µm).

As a main tech. process for ASIC development it is expected to use UMC 0.13 µm one with RF option. Unfortunately there is not any strategy for scaling down the ASIC design to 90 nm (or even 65 nm) processes, which will be evidently the next generation of technology era.

Remarks


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Cost estimation for ASIC designThe ASIC design cost is consist of the following main parts:

• Fabrication cost of prototype ASICs (given by e.g. Europractice) It strongly depends on process. (Currently Europractice discounted prices are 240…64000 € /mm2 typ.)

•The mass (more correctly to say small volume) production cost should be comparable with prototyping cost. 1.5*101.5*1066 channels channels ~100 ~100 channels/chip & ~1000chips/wafer channels/chip & ~1000chips/wafer ~15 wafers only!~15 wafers only!

• Designer man-power cost*. It is roughly 2..3 man*year per each prototype ASIC

• Man power cost of test electronics development is about 1..2 man*year per each prototype ASIC

• Man power cost of rad-had tests is about 0.5 man*year per each prototype ASIC

• On the way costs for computing are estimated as a few k€

* – It is supposed, that the design group contains PhD qualified staff only


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MEPhI GroupsMEPhI Groups

• Si-strip FEE structure developmentSi-strip FEE structure developmentE.Atkin, I.Ilyushchenko, A.Silaev, Yu.Volkovin collaboration with SINP/MSU (A.Voronin & oths)

• ASIC designASIC design E.Atkin, A.Silaev, A.Krasniuk

• IC tester designIC tester designM.Alyushin, A.Alyushin, E.Onishchenko

• IC rad had testsIC rad had testsB.Bogdanovich, A.Simakov

• HV fuse designHV fuse designA.Simakov

• CBM PhysicsCBM Physics?

Documents

Status of the Silicon Strip Detector/ FEE development