PSI - Feb. 9th, 2005 1

Status of the electronic systems of the MEG

ExperimentPietro Creti

Stefano GiurgolaMarco Grassi Fabio MorsaniDonato Nicolo Wataru Ootani Marco Panareo

Stefan RittMatthias SchneebeliGiovanni Signorelli

PSI - Feb. 9th, 2005 2

Topics

PMT ActiveSplitter

~11m~3m

area

monitor

~3mDRS

Board(32chn)+ CPU

DC Pre-Amp DRSBoard

(32chn)+ CPU

~7mSIS

3100

5 VME crates

800 + 160

1920

opticalfiber (~20m)

Trigger

Front-End PCs

On-line farm

Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)

Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)Rack – PC (Linux)

3+1 VME cratestrigger

ready

PSI - Feb. 9th, 2005 3

Active Splitters Status

PSI - Feb. 9th, 2005 4

Original splitter structure

Monitor output

DRS output

Trigger output

input

Sum output

test

• High gain, low noise first stage to reduce total noise.

• Low distortion second stage to drive the outputs.

• 4 input adder.• Precise layout design

to reduce parasitic coupling.

• Defined impedance striplines for the interconnections.

PSI - Feb. 9th, 2005 5

Prototypes• In July 2004 a 8-

channels 6U prototypes was ready

• The prototype was tested in Lecce with the help of Y. Yudin.

• Then we realized a 4-layer printed circuit, and we built 2 card with a mini-crate and power supply.

PSI - Feb. 9th, 2005 6

Splitter redesign• At the PSI July meeting

we decide to modify the output lines from single-ended to differential, to reduce the crosstalk at the DRS input.

• This choice required a complete redesign of the card.

• Moreover we evaluated the possibility to use flat (twisted) cable to connect the splitter outputs to the DRS inputs.

DRS output

Trigger output

Sum output

Differential

input

test

Spare

PSI - Feb. 9th, 2005 7

New components

• AD8009 - 1GHz, 5500 V/μs Low Distortion Amplifier– Amplifier stages and adder;

• AD8351 Low Distortion Differential RF/IF Amplifier– DRS and sum outputs driver;

• AD8137 – Low Distortion Differential ADC Driver– Differential output driver.

2004 manufactured

PSI - Feb. 9th, 2005 8

New prototype

• Test of new chips and interconnections: new 4-channels prototype

• Currently under test

PSI - Feb. 9th, 2005 9

Preliminary measurements

Input : 46.0mV, Input : 46.0mV, ttff: 2.4 ns: 2.4 ns

Out 1 : 311mV, Out 1 : 311mV, ttrr: 2.5 ns: 2.5 ns

Out 2 : 307mV, Out 2 : 307mV, ttff: 1.5 ns: 1.5 ns

Diff : 619mV, Diff : 619mV, ttff: 1.6 ns: 1.6 ns

PSI - Feb. 9th, 2005 10

Preliminary measurements

Integral non-linearity: <2% (0mV÷50mV)

f =100MHz

PSI - Feb. 9th, 2005 11

Preliminary measurements

• Crosstalk level is about 14mVpp, having a signal of ±1.7V on the adjacent channel

• So we conclude that crosstalk is below 1%

• noise level at about 1mVpp

Crosstalk

Noise

PSI - Feb. 9th, 2005 12

Temperature dependence

Propagation delay Propagation delay coefficient coefficient < < 2ps/°C2ps/°C

PSI - Feb. 9th, 2005 13

Distortion measurement

Difference Difference between Vbetween Vinin∙A∙Avv and Vand Voutout

VVinin rise time rise time

PSI - Feb. 9th, 2005 14

Towards the final system

• Test of this prototype with the DRS and the trigger board

• Study of the maximum channel density compatible with the routing on a standard format (6U, 9U, …) card. June 2005

• Design of the final board September 2005

PSI - Feb. 9th, 2005 15

Cable tests• Input signal: rectangular pulse of 14 ns with 0.9ns rise time and

0.9ns fall time • Quality parameter: rise time of the output pulse• For short lengths (~2m) the

flat twisted cable (green curve) is equivalent to the coaxial ones.

1. Splitter outputs: differential on twisted pairs

• The 3M coaxial solution uses the RG178B/U (black curve) which have the worst performances

2. Splitter inputs: optimization of connectors, cable type and length is necessary

PSI - Feb. 9th, 2005 16

Trigger System status

PSI - Feb. 9th, 2005 17

Reminder

Digital approach – Flash analog-to-digital converters (FADC)– Field programmable gate array (FPGA)

trigger observables – energy, direction and time (LXe calorimeter)– e+ time and approx. direction (Timing Counters)

Expected rate – For 108 muon stop rate

e

1-s 20 4

ff

TRfRRe

PSI - Feb. 9th, 2005 18

MEG trigger makes use of all variables of the photons and the positrons with

baseline algorithms

Efficiency-debugging triggers like MEG trigger but relaxing 1 selection criteria

Calibration triggers selection of e events for timing calibration selection of induced physical events (LED, α, π0, laser); the connection of auxiliary external devices (like calorimeters,

laser) occurs through further Type1 boards

Alternative triggers trigger hardware is dimensioned to support other algorithms

(Principal Component Analysis)

Trigger types

PSI - Feb. 9th, 2005 19

QSUM > QTH && (z,) DWN && |T| < TWN

Charge: QSUM > QTL && (z,) DWN && |T| < TWN

Direction: QSUM > QTH && (z,) DWW && |T| < TWN

Time: QSUM > QTH && (z,) DWN && |T| < TWW

MEG Trigger

QTHQTL

MeV

DWW

DWN

Efficiency-debugging triggers

PSI - Feb. 9th, 2005 20

Calibration TriggersAlpha : PMT patches on lateral faces near the source wires

QPATCH>QTPATCH && QSUM< QTL && |T| >TWW

0 : Use of auxiliary external devices (calorim. and timing counter) QSUM >QTL && QAUX >QTAUX && |TAUX|<TWN

LXe single : high thr. QSUM > QTH , low thr. QSUM > QTL

e : narrow coinc. QSUM> QTL && |T| > TWN

wide coinc. QSUM> QTL && |T| > TWW

Baseline: internally generated random triggers for DRS baseline evaluationLED: use of LED driver signal LASER: reference Laser PMT signal > Laser ThrDC trigger: use of a wire layer of the drift chambers

PSI - Feb. 9th, 2005 21

All triggers can be:• masked• prescaled (up to 65535 counts)

Various features

Other stored information Type 1

• Single rate for each PMTType 2

• Rate for each trigger type• Event Counter (hardware distributed to the DRS boards)• Trigger pattern (hardware distributed to the DRS

boards)• Live Time and Dead Time

PSI - Feb. 9th, 2005 22

Trigger system structure

Type2. .

. 14 boards

15 x 48Type1Type1

Type116

4

LXe inner face(216 PMTs)

2 boards

. . . 11 boards

11 x 48Type1Type1

Type116

4

LXe lateral facesback (216 PMTs) 4 in 1lat. (144x2 PMTs) 4 in 1

up/down (54x2 PMTs) 4 in 1

2 boards

Timing counterscurved (640 APDs) 8 in 1u/d stream (30x2 PMTs)

1 board

2 x 48

1 board

2 x 48

4 x 48

2 VME 6U

1 VME 9ULocated on the platform

Type2Type2

Type2

Type2

Type2

4 x 48. .

. 9 boards

9 x 48Type1Type1

Type116

4

. . . 2 boards

2 x 48Type1Type1

16

4

Drift chambers2 x 16 groups of wire fan in

PSI - Feb. 9th, 2005 23

Number of boards: summary table

row col tot faninn.

board Type1

Connections Type1-Type2

n. board Type2

Connections Type2-Type2

n. board Type2

inner 9 24 216 1 14 1 2 1

lateral 6 24 144 4

lateral 6 24 144 4

back 9 24 216 4 4 1

up 9 6 54 4 1 1

down 9 6 54 4 1 1

Total 828 25 4

TC u.s. 15 2 30 1 2 1

TC d.s. 15 2 30 1 2 1

TC curved 320 2 640 8 5 1

Total 700 9 1

34 5 1

2 2

1 2

TOTAL mounted

TC

PMT Number of trigger boards

LXe

1

5 1

PSI - Feb. 9th, 2005 24

Information flow LXe inner face

4 7 . .

4 4

4 3 . .

4 0

3 9 . .

3 6

3 5 . .

3 2

3 1 . .

2 8

2 7 . .

2 4

2 3 . .

2 0

1 9 . .

1 6

1 5 . .

1 2

1 1 . . 8 7 . . 4 3 . . 0

LXe inner Type1 --> Type 2 X X X S X X

Type2 --> Type 2 S

LVDS BUS bits .

MAX PMT SUM PMT

SUM PMTTIM PMT

TIM PMTIND MAX

IND MAX MAX PMT

SUMPMT: Sum of PMT chargeMAXPMT: Charge of the PMT that has seen maximum light yieldINDMAX: index of the PMT that has seen maximum chargeS: Saturation bit. Warns whether PMT saturation occursTIMPMT: index of the PMT that has seen maximum charge

PSI - Feb. 9th, 2005 25

Information flow other LXe faces

4 7 . .

4 4

4 3 . .

4 0

3 9 . .

3 6

3 5 . .

3 2

3 1 . .

2 8

2 7 . .

2 4

2 3 . .

2 0

1 9 . .

1 6

1 5 . .

1 2

1 1 . . 8 7 . . 4 3 . . 0

LXe lateral Type1 --> Type 2

LXe sides Type1 --> Type 2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

LXe back Type1 --> Type 2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

Type2 --> Type 2 X X X X

Type2 --> Type 2 X X X X X X

PARTIAL SUM BIND SUMB

PARTIAL SUM B

PARTIAL SUM D PARTIAL SUM C

PARTIAL SUM A

LVDS BUS bits .

SUM PMTPARTIAL SUM AIND SUMA

SUM PMT

SUM PMT

SUM PMT

IND SUMA

IND SUMB

IND SUMC

IND SUMD

SUMPMT: Sum of PMT chargePARTIAL SUM: Sum of the PMT charge for PMT belonging to the same patchIND SUM: Index of the Patch that has seen a charge over a min. threshold

PSI - Feb. 9th, 2005 26

Information flow TC and AUX devices

4 7 . .

4 4

4 3 . .

4 0

3 9 . .

3 6

3 5 . .

3 2

3 1 . .

2 8

2 7 . .

2 4

2 3 . .

2 0

1 9 . .

1 6

1 5 . .

1 2

1 1 . . 8 7 . . 4 3 . . 0

TC timing Type1 --> Type 2 X X X X X X X X X X X X

TC curved Type1 --> Type 2 X X X X X X X X

Aux Device Type1 --> Type 2 X X

Type2 --> Type 2 X X X X

Type2 --> Type 2 X X

COU TIMLED

AUX TIM AUX CHARGE

LASER

LED

AUX TIM

indcur 2 indtim 2

t-cur 1

t-tim 1indtim 1ztim 1t-tim 2indtim 2

LVDS BUS bits .

t-tim 2LASER

indcur 1ficur 1ficur 2 indcur 2 t-cur 2

ztim 2

AUX CHARGE

COU TIM

t-tim 1indtim 1indcur 1

TTIM: Time registered TC barINDTIM: Index of TC barZTIM: Position on the TC bar along the z direction

PSI - Feb. 9th, 2005 27

CPLD : Coolrunner II (XC2C284-10-FG324) • Type1 : CPLD design completed and simulated FPGA : VIRTEX II- PRO (XC2VP20-7-FF1152) • Type1-1: FPGA design with ISE 6.3 completed (Frequency 116

MHz) • Type1-1: FPGA simulation completed • Type1-2 (LXe lateral faces) in progress ~ • Type1-3 (TCs) xPCB :

• import FPGA • Board Schematics • Footprints • Routing in progress ~ • Gerber files x

Type1 Present Status

PSI - Feb. 9th, 2005 28

Type2 Present StatusCPLD : Coolrunner II (XC2C284-10-FG324) • Type1 : CPLD design completed and simulated FPGA : VIRTEX II- PRO (XC2VP40-7-FF1152) • Type2-0 (Final Level): FPGA design with ISE 6.3 completed • Type2-0: FPGA simulation in progress ~ • Type2-1 (LXe inner faces) x• Type2-2 (LXe lateral faces) x• Type2-3 (TCs) xPCB :

• import FPGA • Board Schematics in progress ~ • Footprints • Routing x• Gerber files x

PSI - Feb. 9th, 2005 29

Type2

Type2Type2

CLK 20 MHz

VME

ANCILLARY Mother

ANCILLARY Daughters

to DRS

SYNC RES

START STOP

Ancillary boards

Type1Type1

Type1

Type1Type1

Type1

. . .

START STOP SYNC

RESCLK

5

555

2

2

5

5

to DRS

CLK

Event counterTrigger pattern

from DAQBusy

PSI - Feb. 9th, 2005 30

Full System

2002 2003 2004 2005

Test MilestoneAssemblyDesign Manufactoring

Prototype Board

Final Prototype

Trigger schedule

Prototype Board

Final Prototype

partialinstallation

fullinstall.

Full system

1st lot of components ordered

2nd lot of components

PSI - Feb. 9th, 2005 31

DRS status

PSI - Feb. 9th, 2005 32

Current mode readout• First implemented in DRS2 (DRS1 had charge readout)• Sampled charge does not leave chip• Current readout less sensitive to charge injection

(noise) and cross-talk

writeread

C (200fF)

. . .

R(700 )I

UoutUin

PSI - Feb. 9th, 2005 33

Frequency stabilization

Vspeed

16-bitDACLUT

FPGAFrequencyCounter

• Compensate for temperature drifts• Change Vspeed only between events,

keep stable during acquisition phase• Jitter ~ 150ps• Timing accuracy with 9th channel

<25ps

150ps

PSI - Feb. 9th, 2005 34

Measured DRS2 Parameters•Linear response up to

400mV•Usable range of 1V p-p

•Speed range 0.5 GHz – 4.2 GHz

UIN (mV)

U OUT

(mV)

DRS2 response

f (GH

z)

PSI - Feb. 9th, 2005 35

DAQ BoardsPSI GVME Board

FPGA with2 Power-PC

PSI - Feb. 9th, 2005 36

LP waveforms

2 DRS digitizing LP signals– 8ch for data and 2ch for calib.– 2.5GHz sampling – 1024 sampling cells– Readout at 40MHz 16bit– trigger from LP

DRS inputs– LP: central 12 PMTs– LYSO: two signals for each

DRS

Big spikes

• Big spikes are in phase with the time reference clock

• The cross-talk is on the mezzanine board

• It will disappear with a new redesign board

• The internal cross-talk is already much lower

Xe

Time reference

PSI - Feb. 9th, 2005 38

Small spikes

Charge injection from stage

switch

correct phase

wrong phase

The readout phase is controlled by the FPGA: it can be adjusted

PSI - Feb. 9th, 2005 39

Baseline dependence on cell #

R=700

R=~20

16 x 64 cells

U

Cell # Cell #

U OUT

(mV)

U OUT

(mV)

Intrinsic and expected characteristic

PSI - Feb. 9th, 2005 40

DRS calibration

UIN (mV)

U OUT

(mV)

Needs of individual response function for each cell

41

DRS Calibration•Calibrations of the two DRS chips used in the CEX test were completed by MS and implemented in the “lpframework”.•Very helpful especially for analyzing small signal (alpha event)•There’s still spike structure left, which is expected to disappear in the next version of the DRS.

Xe(γ)

Xe(α)

PSI - Feb. 9th, 2005 42

Signal-to-noise ratio

mV

mV

• 1 V DC input signal, common mode subtracted

• Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit)

• Integration over 100 ns PMT pulse (250 bins) has RMS of0.16 mV → SNR = 6200:1 (12.6 bit)

• Could be improved by better analog design of Mezzanine board

Waveforms

LYSO Xe(γ) Xe(α)

44

Analysis examples• Alpha events are clearly discriminated from gamma event.• LYSO time resolution is approaching intrinsic resolution

determined by TDC

γ

Pulse height [mV]

Tim

e co

nsta

nt

Pulse shape discrimination LYSO time resolution

45

Averaged Waveform•Averaged waveform can be used for waveform fitting as a template, for simulating pileup and for testing analysis algorithm, etc.•The measured waveforms are averaged after synchronizing them with T0 calculated by waveform fitting so as not to smear leading edge.

Average

Xe Xe

LYSO LYSO

Average

46

Fitting with Averaged Waveform

• Averaged waveform is nicely fitted to waveform of any height.

• Pulse shape seems to be fairly constant from event to event for gamma event.

47

Pileup Rejection• Overlapping pulses are simulated using averaged

waveform to test rejection algorithm.• Real baseline data obtained by the DRSs is used.

Npe1=2000phe Npe2=1000phe (3000phe is typical for 50MeV gamma)

ΔT=-30nsec

ΔT=+30nsec

ΔT=+60nsec

PSI - Feb. 9th, 2005 48

Plans

• Correct wrong sampling phase • New analog design of mezzanine board in progress ~ • New order of DRS2 issued on Jan 22nd 2005

– Chips will arrive ~May 2005– 2000 channels in total– Enough for LXe calorimeter– Will be replaced with DRS3

• Redesign of DRS2 in spring 2005. DRS3 will be available at the end of 2005

– Better SNR (12 bit vs. 9 bit ?)– Smaller readout dead time

PSI - Feb. 9th, 2005 49

Schedule2002 2003 2004 2005

Test MilestoneAssemblyDesign Manufactoring

DRS2

DRS2 test board

DRS3

VME boards

400 chn 1600 chn

Mass Production3000 chn

DRS1

2nd Prototype

Tests

Boards & Chip Test

DRS1

DRS2

Full System

installation

DRS2 production1600 chn