Status of 3D-IC Technology Research and Development in Japan

Nanoelectronics Research Institute

TIPP2011 3D Satellite Workshop 2011. 6. 14 1

Status of 3D-IC Technology Research and Development in Japan

Masahiro Aoyagi

Nanoelectronics Institute (NeRI)

National Institute of Advanced Industrial Science and Technology (AIST)



Outline

1) Introduction of 3D LSI Chip Stacking Technology

2) National R&D Project Functionally Innovative 3D-Integrated Circuit

(Dream Chip) Technology

3) AIST R&D Activities


TIPP2011 3D Satellite Workshop 2011. 6. 14

IP ChipPackageIP Block

System on ChipSOC Technology

System in Package SIP Technology

Interconnections between IP Blockswith On-Chip Wiring

Internal Low Signal Level Connections in LSI

Interconnections between IP Blockswith In-PKG Wiring

I/O Buffer &ESD Circuits

External High Signal Level Connections in PKG

LSI Chip

3D LSI Chip StackingSystem Technology

IP Chip

ThroughSi ViaTSV

Interconnections between IP Blockswith TSV

Internal Low Signal Level Connections between Chips

High Performance &Low Power Dissipation

Increase of Design & Manufacturing Cost

Low Performance &High Power Dissipation

Reduction of Design &Manufacturing Cost

Reduction of Design &Manufacturing Cost

High Performance &Low Power Dissipation

Comparison of System Integration Technology



Cutting Edge Healthcare/Bio

Advanced Futuristic Consumer Electronics

Futuristic Robots

Laptop Super Computers

Auto-Pilot for Cars

Simultaneous translation capabilityTV-equipped mobile phones

Wall-mounted TVs enabling viewing of foreign films in

Japanese

Capsule endoscopes, artificial organs, behavior management monitors, smart shirts for medical care etc. AI robots, neuro-computers,

household robots

Laptop Super Computers

Automatic travel to destination and automatic driving features

Ubiquitous Computing

Wearable computers, sensor networks

High-performance next-generation

game machines

Ultra High-Performance

Games

Virtual keyboard

Human InterfacesSpeech recognition

Ultra high-speed, high-precision cameras

Future Consumer Products with 3D LSI Chip Stacking System

Combination of MEMS, analog, logic and memory chips etc.



National R&D Project:Development of Functionally Innovative

3D-Integrated Circuit (Dream Chip) Technology



The New Energy and Industrial Technology Development Organization

Joint Research and Development System

National R&D Project:Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology



2006

2007

Technical Survey

Preliminary Research

　　 Main Research

(Dream Chip)

Project Name: “Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology”

Research Topics: 1) High-Density 3D-Integration Technology for Multifunctional Devices

2) 3D Reconfigurable Device Technology

3) 3D Integrated RF Device Technology for Multi-band Communication Systems

Main Project term: FY2008 ~ FY2012 (5 years)Research Fund: FY2008 ≒ 850 million yen FY2009 2≒ .3 billion yen　

Research Overview

Project Schedule

2012-

2008



ASET (Industrial consortium: 21 companies)

-(Advantest) -(Dai Nippon Printing)-Ibiden 　　　　　 -Toppan Printing-(Zycube) 　　　 -(Tokyo Electron)-Shinko Electric -(Yamaichi Electronics)

-(NEC Electronics)-(Renesas) Renesas Electronics-Elpida Memory-Toshiba-Rohm

-NEC - Fujitsu-Sharp-(Nac Image Technology)-IBM Japan-Panasonic-Hitachi - Denso

Universities

-Kyoto University-Shizuoka University-University of Tokyo-Tohoku University-Toyama Prefectural University-Shibaura Institute of Technology-Meisei University-Tokyo Institute of Technology

AIST

Joint Research

Basic Fundamental

Research

Materials/System

Manufacturers etc.

Device Manufacturers

Electronic Equipment

ManufacturersResearchInstitute

Member Companies of the Project and its Organizations

Research Partners(9 Institutions)

~FY2012

（ The National Institute of Advanced Industrial Science and Technology ）



①-A R&D on Design Environment Technology

①- Ｂ R&D on Interposer Technology

②- Ａ R&D on Chip Test Technology

② - Ｂ　 R&D on Cooling and Stacking/Bonding Technology

② - Ｃ　 R&D on Thin Wafer Technology

③- Ａ　 R&D on Demonstration Devices Design and Process Development

1

2

3

4

5

6

Development Themes



（ 1B1 ）　 R&D on Signal Integrity(SI) Technology and Power Integrity(PI) Technology

-1) Design and fabrication of I/F chips (driver, serial-parallel conversion)

-2) Design and fabrication of prototype interposer for high-speed I/O driver　　　　 * Prototyping of surface mount, embedded component, Si interposer　　　　 * Prediction of achieving 20Gbps SI by improving master design of simulation base - 3) Design and fabrication of of power noise evaluation system using FPGA 　　　　

20Gbps transmission impossible

Simulation

20Gbps transmission possible

Simulation

Driver chip mounted

Example of SI improvement by countering Z0 mismatch at via

Prototype interposer for high-speed driver IC

Power noise evaluation system

FPGA

①- Ｂ R&D on Interposer Technology



Wafer Probe ConceptSpecifications: 300,000 electrodes　 15Gbps 5kA,10kW/Wafer

被測定ウェハ

data(Tx)

data(Rx,150um2)

data(Rx,100um2)

data(Rx,80um2)

(Measurement situation)

(Transmission waveforms <1Gbps>)

01020304050607080

0 100 200 300 400 500 600 700 800 9001000

[um

]

伝送速度[Mbps]

X方向

01020304050607080

0 100 200 300 400 500 600 700 800 900 1000

[um]

伝送速度[Mbps]

Y方向

(2A1: Non-contact probing) (2A3: Non-contact connector)

-Basic operation of C coupled receiving circuit-1Gbps signal transmission

(Transmission waveforms <1Gbps>)

(Measurement situation)

(Shape prototype appearance)

-Basic operation of C coupled receiving circuit-Signal transmission exceeding 500Mbps

data(Tx)

data(Rx)

X direction Y direction

Transmission speed [Mbps] Transmission speed [Mbps]

(Permissible position accuracy <±30um @1Gbps>) In case of data(Rx,80um2)

②- Ａ R&D on Chip Test Technology



② -B R&D on Cooling and Stacking/Bonding Technology

両者の温度分布（熱抵抗）は大きく異なる

接合と空気接合空気空気

100m200m

200m

熱流束熱流束

実際の構造と等しいﾏｲｸﾛ・ｽｹｰﾙﾓﾃﾙ゙

接合と空気接合空気空気

100m200m

200m

熱流束熱流束

平面方向の連続体（複合体）モデル

接合と空気との複合熱伝導率

ｼﾘｺﾝ(50μ mthick)

200μ m

9μm

接合の熱伝導率

ｼﾘｺﾝ(50μ mthick)

200μ m

空気の熱伝導率

100μ m

空気の熱伝導率

モデル

モデリング結果（温度分布）

(2B1)-1 R&D on Thermal Evaluation and Cooling Technologies 　

　・ Design Technology Optimization for High thermal Transfer of Chip stacking Structure　・ High Accuracy Thermal Characteristics Evaluation Technology for Micro Structure and Ultra Thin wafer bonding Structure 　・ Micro Structure -High Accuracy Simulation Technology　・ High Thermal Conductivity Space Filling Material　・ Propose a Optimum Thermal Design Criteria for the Integrated Structure　・ Small and High Efficiency Cooling Structure

(2B1)-2 R&D on the Evaluation and Analysis Technologies for the Stacking/ Bonding

　・ Highly Reliable Bonding Technology between Chips of Multiple Micro Bondings (Bump Diameter to be less than 5μm and Number of Bumps to be more than 10,000)

　・ Non Destructive Inspection and Evaluation/ Analysis Technologies for Submicron Failures

・ Optimum Design Criteria for High Yield Integration Process/Structure/Material

Simulation(Temperature distribution)

Si

Compound (Bonding & Air)Thermal Resistance

Individual Bonding & AirThermal Resistance

Modeling



Prototype vision system for FY2010

This large scale frame memory is not included in the plan for FY2010

Desirable structure and dimensions were determined through design studies in FY2008

Image sensor layer

CDS S/H layer

ADC layer

Sensor/ADC Frame memory Processor

Interposer

Reconfigurable processor Memory

③- Ａ　 R&D on Demonstration Devices/Device Design

Interface chip

Sensor chip

TSV 5μm

Organic substrate interposer 110μm pitch

70μm pitch

CDS chip

ADC Chip

30μm

30μm10 ～ 30μm

TSV 35μm 35μm pitch

※CDS ： Correlated Double Sampling



AIST R&D Activities in3D LSI Stacking Technology



National Institute of Advanced Industrial Science and Technology (AIST), led by President Dr. Nomaguchi, is funded by Japanese government. AIST is a rather new research organization established in 2001. Headquarters of AIST are located in Tsukuba and Tokyo. AIST has over 50 research units in various innovative research fields. About 2500 research scientists (about 2000 with tenure) and well over 3000 visiting scientists, post doctoral fellows and students are working in AIST.

National Institute of AIST

TsukubaResearchCenter



LC Embedded Interposer for High-speed Signal & Power Delivery

TSV for Signal

TSV for Power

Fine Bump Joints

Interfilling Layers

Electroless Plating Bridge Connection

Thin CMOS-LSI Chips

External Interface(Electrical & Optical)

Power Delivery

R & D in AIST

Fundamental R& D of 3D LSI Chip Stacking System

Technology

・ Fine Micro Bump Joint Technology・ LC Embedded Interposer Technology・ Heat Spreading Technology



3D R&D Projects in Nanoelectronics Institute

1 ） High-Density Wiring Interposer with High-Speed Signal Transmission and Power Delivery for 3D LSI Chip Stacking Tehcnology （ NEDO R&D Projects: Electronic System Integration, Dream Chip etc. ）

10 micron multilayer wiring 、 20Gbps high-speed transmission line, passive device embedded interposer, power delivery network evaluation system etc.

2) 10 micron pitch micro bump connection （ NEDO R&D Projects: Energy Saving etc. ）

10-5 micron fine bump formation, submicron accuracy flip-chip joint

3) 3D LSI Chip Stacking Technology with High Thermal Conductive Layers （ NEDO R&D Projects: Energy Saving etc. ）

Hot Spot Suppression with TSV and High Thermal Conductive Layers

4) Energy Efficient Multi Core Architechture with 3D LSI Chip Stacking Technology （ NEDO R&D Projects: Energy Saving etc. ）

Multi Bus Interface with High Pin Count Chip-to-Chip TSV Connection



Fine Pitch Fine Bump Connection Technology



10m

10m

10m

5m

10m

20m

15

10

5

015105 3025200m

m

15

10

5

015105 3025200m

m15

10

5

015105 3025200m

m

Shape of Fine Bumps: Electroless Au Plating Bath XG



・ Specific resistance 1000 　 cm high resistive Si ( r=12 , h=380 m)・ Wiring material is Cu

Margin for bump position shift signal line width w=22 m line thickness t=3 m, line spacing g=18 m

Characteristic Impedance Z0 = 50

Several g values are prepared for fabrication tolerance .

Transmission Line Design: Coplanar Waveguide Structure

CPW transmission lineBump joint 1

Contact pad

Open end

CPW Test Device for Fine Bump Connection

Bump joint 2



Device Substrate

30m pitch ， 10m ， 10m heightAu bumps

30m pitch ， 20m□ ， 3m heightAu pads

Cu Coplanar Waveguide

Bump height uniformity well controlled on Cu wiring

bumps

~

Fine Au Bump on CPW Transmission Line



Cross sectional of daisy chain

Cross Sectional of bump joint on signal lines

Pretreatment: O2 PlasmaBonding Condition: Temperature 375℃Load 17N (1.5g per bump)

Confirmed electrical properties of bump joints

Cross Sectionals of Fine Bump Connections



Through two bump joints (Z0 : 56 )Only transmission line (Z0 :52 )

Achieved clear eye diagram for 10Gbps signalLittle effect of bump joints

10Gbps 10Gbps

92% opening

High Speed Signal Transmission Characteristics through Fine Bump Connection



Passive Device Embedded Interposer for 3D LSI Stacking



High Performance Low-Power LSI System with Ultra High Pin Count TSV Connections

1 x2 x3 x4 x5 x60

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Simple formulaSimulation

Normalized # of pins (delivering fixed aggregate bps)

Base design

Max speedMax VDD

No

rmal

ized

en

erg

yp

er b

it t

ran

sfer

90nm CMOS (ASPLA)

Lower speedLower VDD

VDD=1V

0.9V

0.8V

0.7V

0.6V0.5V

Low-Power Operationwith Ultra High Pin Count

Parallel Signal Transmission

Internal Parallel Bus（ >1K bit 、 >500Mbp

s ）

External Serial I/F（ 64 bit 、 16Gbp

s ）

Power Voltage Deviation （ Large di/dt ）

Embedded Decoupling Devices（ Core Power ： <3% 、 I/O 　 Powe

r ： <5% ）

3D LSI Stacking System



Comparison of Decoupling Capacitor Performance with Embedding Method

・ TEG Designed With Three kinds of Embedding Method (SMT, Organic, Silicon)・ TEG Size: 20mm□ , Embedding Area: Central10mm□ , Same Probe Pad Layout ・ Capacitor Values: 1~3F

Device Embedding Method FabricatedTEG

Chip C Mountedon Reverse Side

Contact ProbePads

After Dicing

A-A’ Cross Section

T1T21

T3T23

T25

T2T22

T11

T15T5

T4T24

A A’10mm

20mm

Measurement Contact Probe Pad

Z21

Z11

Interposer TEG Design

Passive Device Embedded Interposer TEG

Capacitor Embedding Area



Connected Seamlessly Two Kinds of Impedance Analyzers

into One System

Ultra Low Impedance Measurement System

(Upper ： 8722ES, Lower ：P4800)

10Hz ～ 40GHz Wideband Ultra-Low Impedance Measurement System with Two Impedance Analyzers Seamlessly Connected

Wideband Widerange Accurate Impedance Measurement & Evaluation Technology

10Hz ～ 40GHz Wideband Ultra-Low Impedance Measurement System with Two Impedance Analyzers Seamlessly Connected

Wideband Widerange Accurate Impedance Measurement & Evaluation Technology

Wideband Ultra-Low Impedance Measurement System

Capacitor Embedded Interposer



Heat Spreading Technology with High Thermal Conductive Layers



Heat Sink

Interposer

ThinLSI Chip

Heat Spreader

Heat Spot Suppression

Heat Spot

CuTSV

Heat Spread Technology with High Thermal Conductive Material

Introduction of New Heat Spreader with High Thermal Conductive Materials



Hot　SpotEmulation

Chip　Carrier

Test　Device

Hot　Spot　Test　DeviceHot　Spot　Test　DeviceHot　Spot　Test　DeviceHot　Spot　Test　DeviceOverlap　ImageOverlap　ImageOverlap　ImageOverlap　ImageIR　ImageIR　ImageIR　ImageIR　Image

IR　Video　ImageIR　Video　ImageIR　Video　ImageIR　Video　Image

9　Heater　Devices（ 10х10　mm）

180m/pixel

Thermal Management Evaluation Using IR Imaging

Ring Oscillator

8m/pixel



Thickness:380 µm Thin substrate :100 µm

The thermal dispersion is enough and there is no hot spot.

There is a hot spot!

Max. 45℃ Max. 119℃

The hot spot is occured in thin Si substrate.

Micro heater deviceChip size : 3×3mmHeater size 1×1mmAmbient temperature: 23˚CHeating value: 0.3W

Hot Spot Problem in Thin Si Substrate



Cross sectional TEM imageof multilayer nanofilms

10µ

m

Wafer

Si:5nmC:7nm

Si:5nmC:7nm

・・・

Si buffer layer:20nm

Si:5nmC:7nm

Si:5nmC:7nm

・・・

Si Buffer layer:20nm

Si:5nmC:7nm

Si:5nmC:7nm

・・・

Si:5nm

A Structure (Thickness ： 492nm)

B Structure 18cycle

B Structure(thickness ： 507nm)

Multilayer Nanofilm Stack



• Raman spectroscopic analysis

FWHM of G-peak :119cm-1

*FWHM of G-peak at single carbon layer: 112cm-1

→ The thermal conductivity of multilayer nanofilms is 800~1000W/mK

Crystallinity of multilayer nanofilms



Tem

pera

ture

(°C

)

Time (ms)

Micro heater deviceChip size : 3×3mmHeater size 1×1mmAmbient temp.: 23˚CHeating value: 0.1W

Transient behavior of temperature at central part in hot spot

Hot Spot Suppression by Nanofilm Back Coating



Low Power Multi Core Architecture with 3D LSI Stacking



Z Direction Connection of TSV & Micro Bump Joint

Speed: 1~100Gbps

Z Direction Connection ofWireless Method

Robust Easy Maintenance

System

High Performance System

Z Direction Connectionof Optical Method

Speed: 10G~1Tbps

Speed: 100G~10Tbps

Ultra High Performance

System

IP Chip

OpticalInter-connection

TSV & Micro Bump JointInter-connection

Inductive/Capacitive/Electro-magneticInter-connection

IP Chip IP Chip

PKG Wiring & Solder BallInter-connection

Z Direction Connection of PKG Level

Low Cost System

IP Chip

Speed: 1~100Gbps

Signals ： 100-10000

Signals ： 10-1000Signals ： 10-1000 Signals ： 10-1000

3D LSI Chip Stacking System Technology



COOL System – Ultra Low Power Flexible & Extendable Hardware

　 NEDO　『 Energy　Saving　Technology　R&D』　　 Collaborative　Research　with　Tops　

Systems　Corp.　

Target ：　 Ultra Low Power System ・ Small Volume Production ・ Short System Development Period

　 COOL Chip : Ultra Low Power Heterogeneous Multi Chip 　【 3D LSI Stacking Emulation FPGA Board 】

　 Reduction of Power Consumption with 1/10 Clock Frequency Heterogeneous Multi Core/Multi Chip

　 COOL Interconnect : Ultra Low Power Parallel Bus Interface 　【 Interface Test Chip 　】

　 Scalable Connection with Heterogeneous Chips

　 COOL Software ：　 Functional Distribution Processing

　 Improved signal processing efficiency with KPN Model

情報処理学会　　　２０１０．１２．６組込システム研究発表会（熊本大）で発表電子情報通信学会２０１１．３．２VLSI 設計技術研究会（沖縄）で発表予定



３ D LSI Chip Stacking Process Linewith Minimal Fab System



Minimal LSI Fab System Proposed from AIST

200m

3m30cm

500 Billion Yen

Without Clean Room

Type1: Mega Fab SystemType1: Mega Fab System

3m12”

Wafer

500 Million Yen

Wafer 0.5”

1/10

00

1/10

00Type2: Minimal Fab SystemType2: Minimal Fab System



Minimal Clean Shuttle Production System

R&D of Minimal LSI&3D Process Equipment

MinimalDeep Etching

MinimalTesting

MinimalWafer

Thinning

minimal PLAD minimal PLADminimal PLAD

ミニマルシャトル

MinimalPE-CVD

minimal PLAD

MinimalWafer

Bonding

minimal PLAD

PLAD ： Particle Lock Air-tight Docking

minimal PLAD minimal PLAD

MinimalCu ViaFilling

MinimalBumping

3D LSI Production/R&D

LSI Production/R&D

Minimal Wet

Etching

MinimalSuppteringDeposition

MinimalPlasmaEtching

MinimalFurnace

MinimalLithography

MinimalCoating/

Developing

MinimalCleaning

minimal PLAD

minimal PLAD

minimal PLAD

minimal PLAD

minimal PLAD

minimal PLAD

minimal PLAD

30cm

FY-2010

minimal PLAD

FY-2011

Minimal･･･

Minimal Fab Consortium

3D Minimal Fab Consortium



SEMICON Japan 2010

700 Visitors in AIST Booth Minimal Fab EquipmentConcept Model



10cm

10cm15cm

Preparation Chamber ： Size Reduction Achieved

Preparation Chamber

新開発超小型直線移動機構･･

PLAD: Particle Lock Air-tight Docking

Dust particles and gases can be isolated.Localized clean space transfer system

40cm

Minimal Shuttle



Thank you for your attention.



Documents

Status of 3D-IC Technology Research and Development in Japan