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Status and Improvements of TDCB project TDAQ working group meeting 09.12.2009 Andrea Burato (INFN Pisa) On behalf of TDCB working group

Status and Improvements of TDCB project TDAQ working group meeting 09.12.2009 Andrea Burato (INFN Pisa) On behalf of TDCB working group

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Status and Improvements of TDCB project

TDAQ working group meeting

09.12.2009

Andrea Burato (INFN Pisa)On behalf of TDCB working group

Summary / Outline

Status of the TDC Board Updates concerning the old

PCB version Cables and connectors The new FPGA JTAG Programming

Status of TDC Board

• 128-channels TDC daughter card for TELL1 (512 ch/TELL1)• 4xHPTDC (100 ps resolution)• New FPGA: Cyclone III EP3C120F780C8N• New connectors (4 connectors/board, 2 on each side)• Firmware: trigger mode under debugging, other parts almost stable

TDCB version 3 prototype ready on January

Pre-production of about 20 pieces

TDCB v.2

(Let us know who needs them)

PCB updates

• Supply circuitry: fixed wrong voltage to TDC core and fixed the TDCB supply control from TELL1;• Termination resistors are moved near to the TDC (LVDS receiver) in order to reduce the reflection on the lines on the PCB; • Spares from TDC channels (possibility to talk with the front-end with LVDS or LVTTL standard);• Introduced the possibility of change TDC Core voltage;• Led (new definition);• Protection Resistors for the FPGA agaist overshoot;• New FPGA: Cyclone III

Main modification:

Cables and connectorsBrief reminder of the “saga”:

Present “black” cable About 140€/16 channels

Samtec cable 570€/64 channels

“Blue” (ALICE) Amphenol cable 150€/32 channels (>> ALICE)

Cheap twisted flat solution About 80€/32 channels

Since then:• cheap plastic connectors solution? (no ground on connector)• Nice Samtec connector & flat cable (to leave possibility for Samtec high-performance cable?): not possible• Last offer for “blue” (ALICE) cable, 150€/32 channels, is retracted by Amphenol

October meeting:• 34 pairs (32 channels + ground + 1 user-defined pair to front-end)

• Cheap twisted-pair solution seems good enough

Cables and connectors

• Right-Angle VHDCI Connector• 68 pins (one connector for each TDC)• Through-hole PCB mounting

Connectorsfemale

male

• 30 AWG• Mechanical stability• Soldered mounting

• Easy assembly• Crimped mounting(for preliminary test)

Cables and connectorsCables

1) “Blue” (ALICE) Amphenol skewclear cable• Halogen free• 34 differential pairs individually shielded and globally shielded• High performance cable (jitter < 30ps for channel)• About 200€/32 channels (Amphenol offer for 100 pieces)• About 170€/32 channels (Amphenol offer for 500 pieces)• Few prototype ordered (20 pieces) / let us know who needs them

2) Flat cable twisted pairs shielded• Halogen free• Flat cable rolled with a global shielding• 34 differential pairs • About 70-80€/32 channels (evaluation on constructor price)• To be built

Cables and connectors

Same connector: each sub-detector can choose cheap or high-performance cable

(for test)

FPGA

Present design is quite powerful

Cost reduction with no expected performance degradation

Want to keep power for possible onboard processing:• DSP blocks unused• High-speed differential I/O no necessary

Change to Cyclone III

Stratix II FPGA (underutilized)

• Possible onboard processing with embedded multipliers• Fast I/O features• less expensive FPGA

FPGA

Stratix II Cyclone IIII/O Pin 492 531

Logic elements 60440 119088

Total RAM embedded (Kbits)

2,485 3,888

PLL 6 4

Supply voltage 1.2 V (core), 2.5 V (Pll),

3.3 V (I/O bank)

1.2 V (core), 2.5 V (Pll),

3.3 V (I/O bank)

“Price” (from Altera website)

1325 $ 418 $

Jtag Programming

New firmware feature:

Using the JTAG interface it will be possible to program all configuration devices present on TELL1 and on TDC Board

• Serial FlashLoader (SFL) megafunction is introduced in the Quartus II user design• The SFL megafunction creates a bridge between Jtag interface and active serial interface in the FPGA• After FPGA configuration the new firmware is transfered in the configuration device and the programming is completed

Jtag ProgrammingMain Jtag chain

Programming fromexternal terminal viaJtag (tested working)

Scheduling of the new version

Dec.

2009

Jan.

2010

Feb.

2010

Mar.

2010

Apr.

2010

May

2010

Jun.

2010

Jul.

2010

Aug.

2010

Sep.

2010

Oct.

2010

Pre-production

Preliminary Test

Firmware test

Final debug

Production

When the production? How many boards will be required?

Conclusion

• New TDC Board ready on january with Cyclone III (less expensive)

• Pre-production of about 20 TDCB + 20 cables (1/board)

• Two alternative for cables and connectors

• New firmware feature: Jtag programming

• Updates regarding the old PCB version

Spare

Jtag Programming

• SFL megafunction is a simple megafunction available with the Quartus II software• Introducing this block in your project it is possible to program serial configuration device by Jtag interface• All comunication between serial device and FPGA is managed automatically